Title:
A method for forming an insulating gate bipolar transistor device, a semiconductor device, and the device
Document Type and Number:
Japanese Patent JP6027192
Kind Code:
B2
Abstract:
A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.
Inventors:
Sando, Christian Philip
Niedernost Heide, Franz Josef
Fun Creek, Vera
Niedernost Heide, Franz Josef
Fun Creek, Vera
Application Number:
JP2015125995A
Publication Date:
November 16, 2016
Filing Date:
June 23, 2015
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG
International Classes:
H01L29/739; H01L21/336; H01L29/12; H01L29/41; H01L29/78
Domestic Patent References:
| JP2008503081A | ||||
| JP2008507838A | ||||
| JP2008205168A | ||||
| JP2006332662A | ||||
| JP2013062461A | ||||
| JP11103057A | ||||
| JP2011258898A |
Foreign References:
| US20080029909 | ||||
| US20060273389 | ||||
| US6118149 | ||||
| US20110303972 |
Attorney, Agent or Firm:
Sonoda/Kobayashi Patent Business Corporation
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