Title:
厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法
Document Type and Number:
Japanese Patent JP2005526399
Kind Code:
A
Abstract:
In one illustrative embodiment, the method comprises forming a sacrificial layer of material above a substrate comprised of silicon, performing a wet etching process to remove the sacrificial layer, implanting fluorine atoms into selected portions of the substrate after the sacrificial layer is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers above the substrate, the gate insulation layers formed above the fluorine implanted selected portions of the substrate having a thickness that is greater than a thickness of the gate insulation layers formed above portions of the substrate not implanted with fluorine.
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Inventors:
James F. Buehler
John Dee. Cheek
John Dee. Cheek
Application Number:
JP2004506080A
Publication Date:
September 02, 2005
Filing Date:
December 17, 2002
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
H01L21/316; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L29/78; (IPC1-7): H01L21/8234; H01L21/316; H01L21/8238; H01L27/088; H01L27/092; H01L29/78
Attorney, Agent or Firm:
Masatake Suzuki
Ryota Sano
Yoshito Muramatsu
Ryota Sano
Yoshito Muramatsu