Title:
ウェハ接合技術を用いて欠陥のない高Ge含有量のSiGeオン・インシュレータ(SGOI)基板を製造する方法
Document Type and Number:
Japanese Patent JP4906727
Kind Code:
B2
Abstract:
A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
Inventors:
Chu, Jack, Oh
Cobb, Michael, A
Sanders, Philip, A
Shy, Rezen
Cobb, Michael, A
Sanders, Philip, A
Shy, Rezen
Application Number:
JP2007531153A
Publication Date:
March 28, 2012
Filing Date:
March 15, 2005
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/20; H01L21/02; H01L21/265; H01L27/12
Domestic Patent References:
| JP2003017705A | ||||
| JP2006519489A | ||||
| JP2006519488A | ||||
| JP2004507084A | ||||
| JP2004531054A |
Foreign References:
| WO2004077553A1 | ||||
| WO2004077552A1 | ||||
| WO2002071495A1 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi