Title:
A multi-port memory provided with agreement address control
Document Type and Number:
Japanese Patent JP6278554
Kind Code:
B2
Abstract:
In a multiple port SRAM (10), a first bit cell (38) is coupled to first and second word lines (WL0A/WLOB and a first (BL0A/BL0Ab and second bit line pair (BL0B/BLOBb). A second bit (40) cell is coupled to the first and second word lines and a third (BL1A/BL1Ab) and fourth bit line pair (BL1 B/BL1 Bb). A first data line pair (DLA/DLAb) is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair (DLB/DLBb) is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.
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Inventors:
Perry H. Perry
Application Number:
JP2013265276A
Publication Date:
February 14, 2018
Filing Date:
December 24, 2013
Export Citation:
Assignee:
NXP USA,Inc.
International Classes:
G11C11/418; G11C7/10; G11C8/16
Domestic Patent References:
| JP10021687A | ||||
| JP2005346837A | ||||
| JP1178193A |
Attorney, Agent or Firm:
Atsushi Honda
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