Title:
A parallel device which performs LZ77 tokenization of high compression, and Huffman encoding at high speed for Deflate compression
Document Type and Number:
Japanese Patent JP5945291
Kind Code:
B2
Abstract:
Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.
Inventors:
Milne, Andrew
Vicesar, ceilesh
Merrell, Quinn W.
Moser, Lok Plavin Bee.
Vicesar, ceilesh
Merrell, Quinn W.
Moser, Lok Plavin Bee.
Application Number:
JP2014043707A
Publication Date:
July 05, 2016
Filing Date:
March 06, 2014
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F9/38; G06F5/00; H03M7/40; H03M7/42
Domestic Patent References:
| JP7111460A | ||||
| JP8069370A | ||||
| JP7297728A | ||||
| JP2010268146A | ||||
| JP2005175940A | ||||
| JP2005521938A |
Foreign References:
| WO2012090584A1 |
Other References:
田中 望 他,「LZH法による並列データ圧縮技報」,情報処理学会第52回(平成8年前期)全国大会),日本,情報処理学会,1997年 3月 8日,6-133頁~6-134頁
Attorney, Agent or Firm:
Longhua International Patent Service Corporation