Title:
A programmable circuit and FPGA
Document Type and Number:
Japanese Patent JP6232038
Kind Code:
B2
Abstract:
It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
Inventors:
Yasuhiko Takemura
Shunpei Yamazaki
Shunpei Yamazaki
Application Number:
JP2015239187A
Publication Date:
November 15, 2017
Filing Date:
December 08, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/177; G09G3/30
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