Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3212884
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce noise caused by the coupling capacitance between adjacent digit line pairs by arranging first and second digit line pairs so that first and second digit line pairs to be simultaneously selected do not become adjacent each other.
SOLUTION: Digit selection circuits YSW are alternately arranged every two digit line pairs at up and down of a plurality of digit line pairs (D, the inverse of D). The digit selection circuits YSW are selected by digit selection lines Y1, Y2... in the order of Y1, Y2.... Consequently, digit line pairs (D01, the inverse of D01) and (D11, the inverse of D11) to be selected simultaneously do not become adjacent to digit line pairs (D02, the inverse of D02) and (D12, the inverse of D12). Thus, since digit line pairs which are not selected enter between the digit line pairs to be selected simultaneously to become a form shielding coupling noise, the lowering of a voltage margin and the deteriorating of a characteristic caused by the coupling noise are suppressed.
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Inventors:
Hiroyuki Takahashi
Application Number:
JP22873296A
Publication Date:
September 25, 2001
Filing Date:
August 29, 1996
Export Citation:
Assignee:
NEC
International Classes:
G11C11/41; G11C5/14; G11C7/10; G11C11/4074; H01L21/8244; H01L27/11; (IPC1-7): G11C11/41; G11C11/413
Domestic Patent References:
| JP337888A |
Attorney, Agent or Firm:
Naoki Kyomoto