Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2023093164
Kind Code:
A
Abstract:
To provide a technique capable of detecting a substrate bias voltage with low power consumption.SOLUTION: A technology includes a booster circuit (CP1) that outputs a boosted voltage on the basis of a first clock signal (CLKP) of a first frequency (FCLKP), a step-down circuit (CP2) that outputs a step-down voltage on the basis of a second clock signal (CLKN) of a second frequency (FCLKN), and a logic circuit block (CL) that compares the first frequency and the second frequency and outputs a comparison result (CMPOUT) between the first frequency and the second frequency according to a predetermined standard.SELECTED DRAWING: Figure 1
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Inventors:
YAYAMA KOSUKE
Application Number:
JP2021208627A
Publication Date:
July 04, 2023
Filing Date:
December 22, 2021
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L21/822; H01L21/8238
Attorney, Agent or Firm:
Polaire Patent Attorneys Corporation