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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2023165124
Kind Code:
A
Abstract:
To improve performance of a semiconductor device.SOLUTION: A wiring board 10 includes: an insulation layer 10A2; a conductor layer CL2 formed on an upper surface A1t of the insulation layer 10A2; an insulation layer 10A1 formed on the upper surface A1t of the insulation layer 10A2; a conductor layer CL1 formed on the insulation layer 10A1; a conductor layer CL3 formed on a lower surface A1b of the insulation layer 10A2; an insulation layer 10A3 formed on the lower surface A1b of the insulation layer 10A2; and a conductor layer CL4 formed on the insulation layer 10A3. When it is assumed that an occupancy of a conductor pattern CP2 in the conductor layer CL2 is a first occupancy, an occupancy of a conductor pattern CP1 in the conductor layer CL1 is a second occupancy, an occupancy of a conductor pattern CP3 in the conductor layer CL3 is a third occupancy, and an occupancy of a conductor pattern CP4 in the conductor layer CL4 is a fourth occupancy, each of the first occupancy and the third occupancy is larger than each of the second occupancy and the fourth occupancy.SELECTED DRAWING: Figure 5

Inventors:
KARASHIMA TAKASHI
Application Number:
JP2022075783A
Publication Date:
November 15, 2023
Filing Date:
May 02, 2022
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L23/12; H01L21/60
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office