Title:
半導体装置
Document Type and Number:
Japanese Patent JP7411839
Kind Code:
B2
Abstract:
An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.
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Inventors:
Hiroyuki Miyake
Application Number:
JP2023024997A
Publication Date:
January 11, 2024
Filing Date:
February 21, 2023
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K3/356; G09G3/20; G09G3/3233; G09G3/3266; G09G3/3275; G09G3/36; G11C19/28; H03K19/0175; H03K19/094
Domestic Patent References:
| JP201191375A | ||||
| JP2011124561A |
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