Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP7226016
Kind Code:
B2
Abstract:
To provide a semiconductor integrated circuit that can inspect a scan path circuit without slowing down even if a terminal that cannot operate at high speed is also used as an inspection terminal.SOLUTION: A semiconductor integrated circuit 1 includes an internal comparator 3 in which a data Shift_OUT output by a scan path circuit 2 according to a test data Shift_IN input to an input terminal IN by an inspection device is compared with a data "OUT expectation value" output to the input terminal IN by the inspection device. A scan operation controller 5 switches the path of a scan path circuit 2 and controls the output of a comparison result by the internal comparator 3.SELECTED DRAWING: Figure 1
Inventors:
Isshin Matsuo
Kaichi Sakaguchi
Kaichi Sakaguchi
Application Number:
JP2019063314A
Publication Date:
February 21, 2023
Filing Date:
March 28, 2019
Export Citation:
Assignee:
株式会社デンソー
International Classes:
G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP2006023225A | ||||
| JP2011163961A | ||||
| JP59200353A | ||||
| JP2004093426A | ||||
| JP61217839A | ||||
| JP2014132384A |
Attorney, Agent or Firm:
Patent Attorney Corporation Sato