半導体メモリ素子

Japanese Patent JP7345244

B2

A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

WO/2023/241295	FERROELECTRIC MEMORY AND MANUFACTURING METHOD FOR FERROELECTRIC MEMORY
WO/2024/042404	SEMICONDUCTOR DEVICE
WO/2023/242664	SEMICONDUCTOR DEVICE AND STORAGE DEVICE

Lee Ki-seok
Kim Joon-soo
Hee Jung Kim
Kim Hoshu
Satoru Yamada
Lee Gyeong-soo
Han Sung Hee
Hong Zhen
Huang Yusho

JP2018195074A

September 15, 2023

October 16, 2018

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Samsung Electronics Co.,Ltd.

H10B53/20; H01L21/336; H01L29/788; H01L29/792; H10B12/00

JP2013168639A
JP2013026289A
JP2015028966A

US20140054538
US20160322368

Patent Attorney Corporation Kyosei International Patent Office

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