Title:
A system and a method for the Boyd control in a soldered joint part
Document Type and Number:
Japanese Patent JP6203731
Kind Code:
B2
Abstract:
In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.
Inventors:
Coop, Paul Jay
Miheel, De Monty
Tomei, Ellen S
Miheel, De Monty
Tomei, Ellen S
Application Number:
JP2014532095A
Publication Date:
September 27, 2017
Filing Date:
September 25, 2012
Export Citation:
Assignee:
ALPHA ASSEMBLY SOLUTIONS INC.
International Classes:
H05K3/34
Domestic Patent References:
| JP2000332398A | ||||
| JP2004154827A | ||||
| JP2000068637A | ||||
| JP2001015901A | ||||
| JP5172772A | ||||
| JP2000323830A |
Foreign References:
| US5088007 |
Attorney, Agent or Firm:
Fukami patent office
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