Title:
A system and a method of programming a memory cell
Document Type and Number:
Japanese Patent JP6084308
Kind Code:
B2
Abstract:
An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.
Inventors:
Xia Li
Bin Yang
Bin Yang
Application Number:
JP2015555449A
Publication Date:
February 22, 2017
Filing Date:
January 31, 2014
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
H01L21/8246; G11C17/14; H01L27/112
Domestic Patent References:
| JP2006059919A | ||||
| JP2010113746A | ||||
| JP2005504434A | ||||
| JP2012520574A | ||||
| JP2001102456A | ||||
| JP2012043970A | ||||
| JP2009193660A |
Foreign References:
| US20070258311 | ||||
| US20100110750 | ||||
| US20040008538 | ||||
| WO2003025944A1 | ||||
| US20100237463 | ||||
| WO2010107772A2 | ||||
| US20090283814 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei
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