Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
A system and a method of programming a memory cell
Document Type and Number:
Japanese Patent JP6280164
Kind Code:
B2
Abstract:
An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

More Like This:
WO/2011/008385CROSS POINT NON-VOLATILE MEMORY DEVICES WITH A PLURALITY OF PILLARS HAVING ROUNDED CORNERS AND METHOD OF MANUFACTURING
WO/2022/042836VERIFIABLE ONE-TIME PROGRAMMABLE MEMORY DEVICE
JP2005039833USE OF APPARATUS AND AT LEAST ONE POWER SWITCHING ELEMENT FOR IMPRESSING AT LEAST ONE ELECTRIC MODULE WITH ENERGY PULSE TO PERMANENTLY CHANGE ELECTRICAL PROPERTIES OF THE ELECTRIC MODULE
Inventors:
Xia Li
Bin Yang
Application Number:
JP2016136610A
Publication Date:
February 14, 2018
Filing Date:
July 11, 2016
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Qualcomm, Inc.
International Classes:
G11C17/16; H01L27/10
Domestic Patent References:
JP2006059919A
JP2009503901A
JP5013776A
JP2010198685A
Foreign References:
US20060054952
US20120008364
US20040047218
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei



 
Previous Patent: A medical examination device for medical science

Next Patent: JPS6280165