Title:
A system and a method for reducing the intersection joint effect
Document Type and Number:
Japanese Patent JP6158277
Kind Code:
B2
Abstract:
A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
Inventors:
Baker S. Mohammad
Paul Dee Basset
Martin Saint-Laurent
Paul Dee Basset
Martin Saint-Laurent
Application Number:
JP2015231635A
Publication Date:
July 05, 2017
Filing Date:
November 27, 2015
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
G06F3/00; H03K19/0175; H03K19/0185
Domestic Patent References:
| JP2003195992A | ||||
| JP2004241930A | ||||
| JP2006352741A | ||||
| JP10187093A | ||||
| JP2009296119A |
Foreign References:
| US20100030924 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei