Title:
A system and a method for reducing the power consumption of an oscillator
Document Type and Number:
Japanese Patent JP5996510
Kind Code:
B2
Abstract:
An apparatus for generating an oscillating signal including a negative-resistance circuit, a crystal, and a component to modify a series resonance of the crystal to decrease power consumption of the negative-resistance circuit in generating the oscillating signal. The component may include a positive-reactance circuit, one or more inductive elements, or pair of inductive elements coupled to the crystal. The apparatus may further include a frequency-tuning component for adjusting a frequency of the oscillating signal, such as a variable capacitor coupled to the crystal. The negative-resistance circuit may include a digital inverter circuit, an inverting analog amplifier, or a self-regulating circuit. The apparatus may further include a quiescent current source to supply a steady-state current to the negative-resistance circuit, and a start up current source to supply a boost current to the negative-resistance circuit only during start up to expedite the oscillating signal in reaching a defined steady-state condition.
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Inventors:
George A. Garcia
Todd Moyer
Todd Moyer
Application Number:
JP2013229851A
Publication Date:
September 21, 2016
Filing Date:
November 05, 2013
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03B5/32
Domestic Patent References:
| JP59196610A | ||||
| JP654308U | ||||
| JP2006197143A | ||||
| JP1075119A |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro