Title:
WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE
Document Type and Number:
Japanese Patent JP2016162887
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a wiring board in which insulation reliability and connection reliability are improved.SOLUTION: A wiring board includes: a core layer comprising a plate-like body and a plurality of liner conductors penetrating the plate-like body in a thickness direction; a wiring layer selectively formed onto a first surface of the plate-like body; and an insulation layer formed onto the first surface and coating the wiring layer, and an interval of the liner conductors apart from a diameter of each of the plurality of liner conductors is small, and the plurality of liner conductors includes a first liner conductor that is disposed to a positioned overlapped with the wiring layer in plane view and conducts to the wiring layer; and a second liner conductor that is disposed to the positioned which is not overlapped with the wiring layer in plane view. An end surface of a first surface side of the first liner conductor is flush with the first surface, the end surface of the first surface side of the second liner conductor is located at a position recessed from the first surface, a vacancy is formed between the end surface of the first surface side of second liner conductor and the first surface, and the vacancy is filled with the insulation layer.SELECTED DRAWING: Figure 1
Inventors:
FUKAZAWA AKIRA
Application Number:
JP2015040367A
Publication Date:
September 05, 2016
Filing Date:
March 02, 2015
Export Citation:
Assignee:
SHINKO ELECTRIC IND CO
International Classes:
H01L23/12; H05K1/05; H05K1/11; H05K3/40; H05K3/44; H05K3/46
Domestic Patent References:
| JP2011171531A | 2011-09-01 | |||
| JP2011151185A | 2011-08-04 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito