Title:
ACTIVE MATRIX SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2016/195001
Kind Code:
A1
Abstract:
In order to reduce wiring resistance in an active matrix substrate, the present invention comprises: a substrate 31; a plurality of gate wires Gj arranged on the substrate 31 and extending in a first direction; a plurality of source wires Si arranged on the substrate 31 and extending in a second direction different from the first direction; a transistor 2 arranged corresponding to each intersection between the gate wires and the source wires Si and connected to the gate wires Gj and the source wires Si; an insulating layer; and expansion conductive films (51, 52, 61). At least either the gate wires Gj or the source wires Si are connected to the expansion conductive films, via a contact hole provided in the insulation layer, and form a laminated structure.
Inventors:
MIYAMOTO TADAYOSHI
NAKANO FUMIKI
NAKANO FUMIKI
Application Number:
PCT/JP2016/066363
Publication Date:
December 08, 2016
Filing Date:
June 02, 2016
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
H01L29/786; H01L21/3205; H01L21/768; H01L23/522; H01L27/146
Foreign References:
| JP2006323333A | 2006-11-30 | |||
| JPH06160904A | 1994-06-07 | |||
| JP2007241237A | 2007-09-20 | |||
| JP2014078651A | 2014-05-01 | |||
| JP2000353808A | 2000-12-19 | |||
| JP2010067762A | 2010-03-25 |
Attorney, Agent or Firm:
KAWAKAMI Keiko et al. (JP)
Keiko Kawakami (JP)
Keiko Kawakami (JP)
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