ADAPTIVE INPUT LOGIC FOR PHASE ADJUSTMENTS - LATTICE SEMICONDUCTOR CORP

Title:

ADAPTIVE INPUT LOGIC FOR PHASE ADJUSTMENTS

Document Type and Number:

WIPO Patent Application WO2004073175

Kind Code:

A3

Abstract:

Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

Inventors:

ANDREWS WILLIAM
SCHOLZ HAROLD
BRITTON BARRY

Application Number:

PCT/US2004/001556

Publication Date:

January 20, 2005

Filing Date:

January 16, 2004

Export Citation:

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Assignee:

LATTICE SEMICONDUCTOR CORP (US)

International Classes:

H03H11/26; H03K5/13; H03L7/081; H04L7/033; H03K5/00; H04B; (IPC1-7): H03H11/26

Foreign References:

US5457718A	1995-10-10
US6628154B2	2003-09-30
US5515403A	1996-05-07
US6491634B1	2002-12-10

Other References: