SELIVERSTOV ANATOL (US)
| US20010052762A1 | 2001-12-20 | |||
| US6548991B1 | 2003-04-15 | |||
| US20020075710A1 | 2002-06-20 | |||
| US20040051509A1 | 2004-03-18 |
CLAIMS 1. A voltage regulator system for providing a regulated voltage supply, said voltage regulator system comprising: a power supply input node for receiving a power supply input voltage; a regulated voltage output node for providing a regulated output voltage; and a feedback circuit coupled to said regulated output voltage node and to a voltage regulator input node wherein a non-zero voltage is provided by said voltage regulator input node.
2. The voltage regulator system as claimed in claim 1, wherein said feedback circuit further includes a first resistor coupled to a feedback node and to said regulated voltage output node; and a second resistor coupled to said feedback node and to a voltage regulator input node wherein said voltage regulator input node provides a non-zero input voltage.
3. The voltage regulator system as claimed in claim 1, wherein said non-zero voltage at the voltage regulator input node is provided by a digital signal processor.
4. The voltage regulator system as claimed in claim 3, wherein said regulated voltage output node provides a core voltage to said digital signal processor.
5. The voltage regulator system as claimed in claim 2, wherein the regulated output voltage node provides the output voltage (V ou t), a voltage reference node V re f receives a reference voltage, the first and second resistors have resistor values of Ri and /?2 respectively, and the output voltage V out = V re f (I+R1/R2) - Vtnc (R1IR2) where V inC is the non-zero input voltage.
6. The voltage regulator circuit as claimed in claim 2, wherein said voltage regulator circuit further includes a third resistor coupled to said feedback node and to ground.
7. The voltage regulator circuit as claimed in claim 6, wherein the regulated output voltage node provides the output voltage (V out ), a voltage reference node V re / receives an reference voltage, the first, second and third resistors have resistor values of Ri, R2 and R3 respectively, and the output voltage Y om - V re f (I+R1/R2+R1/R3) - Vine (R1/R2) where Y in c is the non-zero input voltage.
8. A voltage controller circuit for a switched mode voltage controller, said voltage controller circuit comprising: a switched mode controller including a voltage input node, a switched mode voltage output node, a voltage reference node, and a feedback node; and a feedback circuit coupled to said feedback node, said feedback circuit comprising: a first resistor coupled to said feedback node and to said switched mode voltage output node; a second resistor coupled to said feedback node and to a voltage controller input node wherein said voltage controller input node provides a non-zero input voltage.
9. The voltage controller circuit as claimed in claim 8, wherein said first resistor is coupled to said switched mode voltage output node via an inductor.
10. The voltage controller circuit as claimed in claim 8, wherein said non-zero voltage at the voltage controller input node is provided by a digital signal processor.
11. The voltage controller circuit as claimed in claim 10, wherein said switched mode voltage output node provides a pulse width modulated signal that is subsequently low pass filtered to provide a core voltage to said digital signal processor.
12. The voltage controller circuit as claimed in claim 8, wherein the switched mode output node is coupled to an output voltage node via a low pass filter, and the voltage output node provides an output voltage (V om ), the voltage reference node V re / receives a reference voltage, the first and second resistors have resistor values of R] and R 2 respectively, and the output voltage V out = V re / (1+R 1 IR 2 ) - Yi n c (R 1 /R2) where Vj π c is the non-zero input voltage.
13. The voltage controller circuit as claimed in claim 8, wherein said voltage controller circuit further includes a third resistor coupled to said feedback node and to ground.
14. The voltage controller circuit as claimed in claim 13, wherein the switched mode output node is coupled to an output voltage node via a low pass filter, and the voltage output node provides an output voltage (V oιa ), the voltage reference node V re / receives a reference voltage, the first, second and third resistors have resistor values of R;, R2 and R3 respectively, and the output voltage V 0 ,,, = Vr e /(1+R;/R 2 +R//R3) - Vmc (R1/R2) where V inC is the non-zero input voltage.
15. A method of providing a switched mode voltage supply at a switched mode output voltage node, said method comprising the steps of: receiving a power supply input voltage; providing a pulse width modulated signal at the switched mode output voltage node; and coupling said switched mode output voltage node and a voltage controller input node to a feedback node wherein a non-zero voltage is provided by the voltage controller input node.
16. The method as claimed in claim 15, wherein said step of coupling said pulse width modulated signal and the voltage controller input node to a feedback node includes the step of coupling said pulse width modulated signal to said feedback node with an inductor and a first resistor, and coupling said voltage controller input node to the feedback node with a second resistor.
17. The method as claimed in claim 16, wherein the switched mode output voltage node is coupled to a low pass filter that provides a low pass filtered pulse width modulated output voltage (V ou t), a voltage reference node V re f receives a reference voltage, the first and second resistors have resistor values of R] and R 2 respectively, and the output voltage Vout = Vref il+RifR∑) - Vine (R1/R2) where V inC is the non-zero input voltage.
18. The method as claimed in claim 16, wherein said step of coupling said switched mode output voltage node and the voltage controller input node to a feedback node further includes the step of coupling said feedback node to ground with a third resistor.
19. The method as claimed in claim 18, wherein the switched mode output voltage node is coupled to a low pass filter that provides a low pass filtered pulse width modulated output voltage (V out ), a voltage reference node V re / receives a reference voltage, the first, second and third resistors have resistor values of Rj, R 2 and R 3 respectively, and the output voltage V out = V re f(l+RilR2+RilR3) - Vine (R1/R2) where Vmc is the non-zero input voltage.
20. The method as claimed in claim 15, wherein said switched mode output voltage is changed by adjusting the non-zero input voltage. |
ADJUSTABLE VOLTAGE REGULATOR SYSTEM, PARTICULARLY FOR DSP
PRIORITY INFORMATION
The present invention claims priority to U.S. Utility Application Serial No. 11/247,776, filed on October 11, 2005 which is incorporated herein by reference in its entirety.
BACKGROUND
The invention generally relates to power supply control systems, and relates in particular to adjustable control of voltage regulators. Conventional controllers for voltage regulators, such as switched mode controller systems, include a controller interposed between a power source and a load, such as a digital signal processor. For example, as shown in Figure 1, a conventional switched mode controller system includes an adjustable voltage regulator such as a switched mode converter 10 that couples a power supply 12 to a digital signal processor 14. The switched mode converter 10 receives a power supply input voltage 16 from the power supply 12 at a Vi np s node and provides a pulse width modulated signal at output node sw. The pulse width modulated (pwrri) signal is then low pass filtered by an inductor 20 and capacitor 24 to provide an output voltage 18 (V ou t) to the digital signal processor 14.
The input voltage Vi nps is typically provided to the converter 10 using a filter capacitor 22 that is also coupled to ground, and the output voltage is typically provided to the digital signal processor 14 using the filter capacitor 24 that is also coupled to ground. The controller 10 also includes a reference voltage 26 at a V re / node, and receives a feedback signal 28 at a feedback fb node.
The feedback signal is provided by a voltage divider circuit that includes a first resistor 30 (R]) that is coupled to the output signal 18, and a second resistor 32 (R 2 ) that is coupled to ground. The voltage reference signal may be either provided via an external connection as shown or may be provided internally. The feedback signal 28 and the voltage reference signal are provided to a differential amplifier 13, and the output of the differential amplifier is provided to apwm generation unit 11.
The pwm signal at the node sw is provided by the pwm generation unit 11 responsive to the output of the differential amplifier is employed to control the output of the supply input voltage Vι nps as well as the output of the differential amplifier.
The voltage V out is provided by the relationship V out = V re / (I+RI/RT)- The voltage Vout is typically adjusted by changing the values of the resistors Rj and i?2- The voltage
V 0U t however, may not be made to be less than V re / and such adjustments must be made by physically changing resistors or adjusting potentiometers. Certain further switched mode controllers employ a digital potentiometer that may be adjusted by changing a digital wiper value on the digital potentiometer using a digital control interface. Although the use of such a digital potentiometer may permit the controller to switch a power supply voltage in real time, the control circuit requires additional complex digital circuitry.
There is a need, therefore, for a more efficient and economical adjustable voltage controller system. There is further a need for an adjustable voltge controller that may be adjusted in real time and may be fully adjusted such that V oιλ may be adjusted to be less than V ref .
SUMMARY
The invention provides a voltage regulator system for providing a regulated voltage supply. The voltage regulator system includes a power supply input node for receiving a power supply input voltage, a regulated voltage output node for providing a regulated output voltage, and a feedback circuit coupled to the regulated output voltage node and to a voltage regulator input node wherein a non-zero voltage is provided by the voltage regulator input node.
In accordance with another embodiment, the invention provides a voltage controller circuit for a switched mode voltage controller. The voltage controller circuit includes a switched mode controller and a feedback circuit. The switched mode controller includes a voltage input node, a switched mode voltage output node, a voltage reference node, and a feedback node. The feedback circuit is coupled to the feedback node and includes a first resistor coupled to the feedback node and to the switched mode voltage output node, and a second resistor coupled to the feedback node and to a voltage controller input node. The voltage controller input node provides a non-zero input voltage.
In accordance with another embodiment, the invention provides a method of providing a switched mode voltage supply at a switched mode output voltage node. The method includes the steps of receiving a power supply input voltage, providing a pulse width modulated signal at the switched mode output voltage node, and coupling the
switched mode output voltage node and a voltage controller input node to a feedback node wherein a non-zero voltage is provided by the voltage controller input node.
BRIEF DESCRIPTION OF THE DRAWINGS The following description may be further understood with reference to the accompanying drawings in which:
Figure 1 shows an illustrative diagrammatic view of a switched mode controller of the prior art;
Figure 2 shows an illustrative diagrammatic view of a switched mode controller in accordance with an embodiment of the invention; and
Figure 3 shows an illustrative diagrammatic view of a switched mode controller in accordance with another embodiment of the invention.
The drawings are shown for illustrative purposes only.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
The invention provides the ability to fully change a core voltage of a digital signal processor in real time in accordance with an embodiment. The control may be achieved by an additional serial communication link from a controller. The system provides in an embodiment that a conventional switched mode converter may be used, together with a single control line that may be provide to the digital signal processor. The system further permits the output voltage to be set below the level of the internal voltage reference V r φ
A system in accordance with an embodiment of the invention is shown in Figure 2. The system includes a switched mode converter 40 that couples a power supply 42 to a digital signal processor 44. The switched mode converter 40 receives a power supply input voltage 46 from the power supply 42 at a V, π/W node and provides a pulse width modulated signal at output node sw. The pwm signal is then low pass filtered by an inductor 50 and capacitor 54 to provide an output voltage 48 (V ou t) to the digital signal processor 44.
The input voltage Vi nps is typically provided to the converter 40 using a filter capacitor 52 that is also coupled to ground, and the output voltage is typically provided to the digital signal processor 44 using the filter capacitor 54 that is also coupled to ground. The controller 40 also includes a reference voltage 56 at a V re f node, and receives a feedback signal 58 at a feedback fb node. The feedback signal is provided by a voltage divider circuit that includes a first resistor 60 (Ri) that is coupled to the output signal 48, and a second resistor 62 (R 2 ) that is coupled to a controller voltage source Vι nC . The
controller input voltage may be provided by the processor 44 itself (as shown at C), or may be provided by another independent voltage source. The voltage reference signal may be either provided via an external connection as shown or may be provided internally.
The feedback signal 58 and the voltage reference signal are provided to a differential amplifier 43, and the output of the differential amplifier is provided to a pwm generation unit 41. The output voltage at the node sw is provided by the pwm generation unit 41 responsive to the output of the differential amplifier 43 is employed to control the output of the supply input voltage V mps as well as the output of the differential amplifier.
The voltage V 0 ,,, is now provided by the relationship V out = Vref (1+R 1 ZR 2 ) - V inC (RlZR 2 )
The voltage V out , therefore, may be changed by changing Vi n& and may further be made to be less than V re f.
A system in accordance with another embodiment of the invention is shown in Figure 3. The system includes a. switched mode converter 70 that couples a power supply 72 to a digital signal processor 74. The switched mode converter 70 receives a power supply input voltage 76 from the power supply 72 at a Vi, ιps node and provides a pwm signal at output node sw. The pwm signal is then low pass filtered by an inductor 80 and capacitor 84 to provide an output voltage 78 (V 0 ,,,) to the digital signal processor 74. The input voltage Vi nps is typically provided to the converter 70 using a filter capacitor 82 that is also coupled to ground, and the output voltage is typically provided to the digital signal processor 74 using the filter capacitor 84 that is also coupled to ground.
The controller 70 also includes a reference voltage 86 at a V re /node, and receives a feedback signal 88 at a feedback yfr node. The feedback signal is provided by a voltage divider circuit that includes a first resistor 90 (Ri) that is coupled to the output signal 78, and a second resistor 92 (R 2 ) that is coupled to a controller voltage source Vι n c- The system of Figure 3 further includes a third resistor 94 (R 3 ) that is coupled between the feedback node fl> and ground. Again, the controller input voltage may be provided by the processor 74 itself, or may be provided by another independent voltage source. The voltage reference signal may be either provided via an external connection as shown or may be provided internally.
The feedback signal 88 and the voltage reference signal are provided to a differential amplifier 73, and the output of the differential amplifier is provided to pwm generation unit 71. The output voltage at the node sw is provided by the pwm generation unit 71 responsive to the output of the differential amplifier 73 is employed to control the output of the supply input voltage Vi nps as well as the output of the differential amplifier.
The voltage V ou t is now provided by the relationship V out = V^(I + R 1 IR 2 + R 1 IR 3 ) - Vine (RiIR 2 )
Again, the voltage V ou t, therefore, may be changed by changing V m - c, and may further be made to be less than V re f.
Those skilled in the art will appreciate that numerous modifications and variations may be made to the above disclosed embodiments without departing from the spirit and scope of the invention.
What is claimed is:
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