ALL-DIGITAL PHASE-LOCKED LOOP CIRCUIT - SONY SEMICONDUCTOR SOLUTIONS CORP

Title:

ALL-DIGITAL PHASE-LOCKED LOOP CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2023/195329

Kind Code:

A1

Abstract:

The present disclosure pertains to an all-digital phase-locked loop circuit which can be designed more easily. Provided is an all-digital phase-locked loop circuit comprising, in parallel: a first time-to-digital converter for detecting a phase difference with a first resolution; and a second time-to-digital converter for detecting a phase difference with a second resolution finer than the first resolution. The second time-to-digital converter can be disabled. The first time-to-digital converter outputs, to a clock synchronization unit that generates a clock signal for a digital unit, a clock synchronization selection signal to be used for reference clock signal synchronization.

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Inventors:

BUNSEN KEIGO (JP)
TAMURA MASAHISA (JP)
PHAM TUAN VAN (JP)
YOSHIMI NAOKI (JP)

Application Number:

PCT/JP2023/010811

Publication Date:

October 12, 2023

Filing Date:

March 20, 2023

Export Citation:

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Assignee:

SONY SEMICONDUCTOR SOLUTIONS CORP (JP)

International Classes:

H03L7/085

Domestic Patent References:

WO2012153375A1

2012-11-15

Foreign References:

JP2019004330A	2019-01-10
US20200192301A1	2020-06-18
US7888973B1	2011-02-15

Attorney, Agent or Firm:

NISHIKAWA Takashi et al. (JP)

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