Title:
AMPLIFICATION CIRCUIT AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/070736
Kind Code:
A1
Abstract:
An amplification circuit (1), which receives a plurality of discrete power supply voltages, comprises: a carrier amplifier (12); a peak amplifier (22); a synthesizing circuit (40) that synthesizes a high frequency signal output from the carrier amplifier (12) and a high frequency signal output from the peak amplifier (22); a bias circuit (50) that supplies a first bias current to the peak amplifier (22); digital control terminals (140 and 150) that receive digital control signals based on an envelope signal; and a switch (23) that is connected to the digital control terminals (140 and 150) to switch between connection and disconnection of the bias circuit (50) and the peak amplifier (22). Each of the carrier amplifier (12) and the peak amplifier (22) includes a plurality of cascode-connected amplification elements.
Inventors:
TAHARA KENJI (JP)
YAMAMOTO KAE (JP)
YAMAMOTO KAE (JP)
Application Number:
PCT/JP2023/033567
Publication Date:
April 04, 2024
Filing Date:
September 14, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03F1/02; H03F1/22; H03F3/68
Domestic Patent References:
| WO2008075561A1 | 2008-06-26 |
Foreign References:
| JP2016149751A | 2016-08-18 | |||
| US20170310282A1 | 2017-10-26 | |||
| JP2015533065A | 2015-11-16 | |||
| JP2021166376A | 2021-10-14 |
Attorney, Agent or Firm:
YOSHIKAWA, Shuichi et al. (JP)
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