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Title:
AN AMPLIFICATION CIRCUIT AND AN OSCILLATOR COMPRISING SAID CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1999/050953
Kind Code:
A2
Abstract:
The invention relates to an amplification circuit, comprising: a differential amplifier (241) having a first input node (236) and a second input node (240) for receiving respectively first and second input signals and an output node for producing an output signal; and active bias circuitry (250) connected to said differential amplifier (241) for drawing a bias current therefrom, wherein said active bias circuitry (250) is configured to draw an increased current when said first and second input signals are substantially equal. An oscillator comprising said amplification circuit and a circuit comprising an oscillator of said type is also part of the invention.

Inventors:
MARNFELDT GOERAN (SE)
Application Number:
PCT/SE1999/000535
Publication Date:
October 07, 1999
Filing Date:
March 30, 1999
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ASTRA AB (SE)
MARNFELDT GOERAN (SE)
International Classes:
H03F3/30; H03F3/45; (IPC1-7): H03B5/00; H03F3/45
Foreign References:
US4843341A1989-06-27
US4599575A1986-07-08
EP0792013A11997-08-27
EP0472340A11992-02-26
Attorney, Agent or Firm:
ASTRAZENECA AB (Global Intellectual Property Patents Södertälje, SE)
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Claims:
CLAIMS
1. An amplification circuit, comprising: a differential amplifier 241 having a first input node 236 and a second input node 240 for receiving respectively first and second input signals and an output node for producing an output signal; and active bias circuitry 250 connected to said differential amplifier 241 for drawing a bias current therefrom, wherein said active bias circuitry 250 is configured to draw an increased current when said first and second input signals are substantially equal.
2. An amplification circuit as claimed in claim 1, wherein said active bias circuitry 250 is arranged to continuously draw at least a constant minimum bias current.
3. An amplification circuit as claimed in claim 1 or 2, wherein said active bias circuitry 250 comprises a first constant current source and a second variable current source connected in parallel.
4. An amplification circuit as claimed in any preceding claim, wherein the active bias circuitry 250 comprises first and second transistors 252,254 connected in parallel and a first control signal 238 controls the first transistor and a second control signal 242 controls the second transistor.
5. An amplification circuit as claimed in claim 4, wherein said second transistor is larger than said first transistor.
6. An amplification circuit as claimed in claim 4 or 5, wherein said first input node supplies said first control signal and said second input node supplies said second control signal.
7. An amplification circuit as claimed in any of claims 4 to 6, wherein the first and second transistors are FETs.
8. An amplification circuit as claimed in claim 7, wherein the FETs are nchannel.
9. An amplification circuit as claimed in any preceding claim, wherein the differential amplifier 241 comprises third 242 and fourth 246 transistors connected in series between a first voltage source 232 and the active bias circuitry 250, and fifth 244 and sixth 248 transistors connected in series between the first voltage source 232 and the active bias circuitry 250, wherein the gates of the third 242 and fifth 244 transistors are connected to a node 243 between the third 242 and fourth 246 transistors to form a current mirror and the first input node 236 is connected to the gate of the fourth transistor 246, the second input node is connected to the gate of the sixth transistor 248, and the output node 245 is connected between the fifth 244 and sixth 248 transistors.
10. An amplification circuit as claimed in claim 9, wherein said third 242 and fifth 244 transistors are pchannel FETs and the fourth 246 and sixth 248 transistors are n channel FETs.
11. An amplification circuit as claimed in any preceding claim, further comprising an additional amplifier having an output 266, said amplifier comprising seventh 262 and eighth 269 transistors connected in series, wherein the output node 245 of the differential amplifier 241 is connected to control the seventh transistor, the input to the first input node 238 is supplied to control the eighth transistor 269 and the output 266 of the additional amplifier is provided from a node 266 between the seventh 262 and eighth 269 transistors.
12. An amplification circuit as claimed in claim 11, wherein the seventh transistor 262 is a pchannel FET and the eighth transistor 269 is an nchannel FET.
13. An oscillator, comprising: an amplification circuit 230 as claimed in any preceding claim; and reference voltage means for providing a constant reference voltage at said first input node and control means for providing a time varying voltage at said second input node.
14. An oscillator as claimed in claim 13, wherein said control means is arranged to provide a periodic voltage waveform.
15. An oscillator as claimed in claim 14, wherein said periodic voltage waveform is a saw toothed voltage waveform.
16. An oscillator as claimed in claim 13, wherein said control means comprises a capacitor, means for charging said capacitor at a constant rate and means for discharging said capacitor, and the voltage across said capacitor provides said time varying voltage waveform.
17. An oscillator as claimed in claim 16, wherein said means for charging said capacitor comprises a constant current source.
18. An oscillator as claimed in claim 16 or 17, wherein said means for charging said capacitor comprises a transistor controlled by a constant voltage provided by said reference voltage means.
19. A circuit comprising an oscillator as claimed in any of claims 13 to 18, wherein said reference voltage means comprises: first and second voltage nodes for receiving first and second applied voltages respectively; first and second intermediate nodes for producing reference voltages; a linear current mirror circuit comprising a first transistor controlled in accordance with the voltage level at the second intermediate node and connected between the first voltage node and the first intermediate node and a second transistor controlled in accordance with the voltage level at the second intermediate node and connected between the first voltage node and the second intermediate node; and a nonlinear current mirror circuit comprising a third transistor controlled in accordance with the voltage level at the first intermediate node and connected between the second voltage node and the first intermediate node and a fourth transistor, larger than the third transistor, controlled in accordance with the voltage level at the first intermediate node and connected in series with a resistive element, said serially connected fourth transistor and resistive element being connected between the second intermediate node and the second voltage node, wherein the resistive element comprises a combination of at least two resistive components having different thermal characteristics.
20. A circuit as claimed in claim 19, wherein, for said reference voltage means, said reference voltages at the first and second intermediate nodes are determined by a stable operating point defined by the combination of the linear and nonlinear current mirrors, said resistive element 226 being configured to have a temperature coefficient of resistance determined to substantially prevent the variation of said operating point with temperature.
21. A circuit as claimed in claim 19 or 20, wherein, in said reference voltage means, said resistive element 226 is configured to have a predetermined temperature coefficient of resistance for compensating variations in the operating characteristics of the linear current mirror and the third and fourth transistors with temperature.
22. A circuit as claimed in claim 21, wherein, in said reference voltage means, said combination comprises a serial combination of said at least two resistive components 228a, 228b.
23. A circuit as claimed in claim 21 or 22, wherein, in said reference voltage means, a first resistive component is made from ntype silicon and a second resistive component is made from polysilicon.
24. A circuit as claimed in claim 21 or 22, wherein, in said reference voltage means, a first one of the resistive components has a positive temperature coefficient of resistance and a second one of the resistive components has a negative temperature coefficient of resistance.
25. A circuit as claimed in any of claims 21 to 24, wherein, in said reference voltage means, said resistive element has a value of approximately 1 MOhm.
26. A circuit as claimed in any of claims 21 to 25, wherein, in said reference voltage means, said first and second transistors are identical.
27. A circuit as claimed in any of claims 21 to 26, wherein, in said reference voltage means, the first and second transistors are FETs with their gates connected to the second output node.
28. A circuit as claimed in any of claims 21 to 25, wherein, in said reference voltage means, said third and fourth transistors are FETs with their gates connected to the first output node.
29. A circuit as claimed in claim 28, wherein, in said reference voltage means, said fourth transistor has the same channel width and half the channel length of the third transistor.
30. A circuit as claimed in claim 28 or 29 when dependent upon claim 27, wherein, in said reference voltage means, said first and second transistors have the same channel width and channel length.
31. A circuit as claimed in claim 27 or any preceding claim when dependent upon claim 27, wherein, in said reference voltage means, said first input node is at a positive voltage, the first transistor is a pchannel transistor and its drain and source are connected respectively to the first output node and the first input node and the second transistor is a pchannel transistor and its drain and source are connected respectively to the second output node and the first input node.
32. A circuit as claimed in claim 28 or any preceding claim when dependent upon claim 28, wherein, in said reference voltage means, said second input node is at ground, the third transistor is an nchannel transistor and its drain and source are respectively connected to the first output node and the second input node and the fourth transistor is an nchannel transistor and its drain and source are connected respectively to the second output node and second input node.
33. A circuit as claimed in any preceding claim, wherein said reference voltage means further comprises a capacitor connected between the first and second output nodes.
34. A circuit comprising an oscillator as claimed in any of claims 13 to 18, wherein said reference voltage means comprises: first and second voltage nodes for receiving first and second applied voltages respectively; first and second intermediate nodes for producing reference voltages; a linear current mirror circuit comprising a first transistor 216 controlled in accordance with the voltage level at the second intermediate node 217 and connected between the first voltage node 212 and the first intermediate node and a second transistor 218 controlled in accordance with the voltage level at the second intermediate node 217 and connected between the first voltage node 212 and the second intermediate node 217; and a nonlinear current mirror circuit comprising a third transistor 220 controlled in accordance with the voltage level at the first intermediate node and connected between the second voltage node 214 and the first intermediate node and a fourth transistor 222, larger than the third transistor 220, controlled in accordance with the voltage level at the first intermediate node and connected in series with a resistive element 226, said serially connected fourth transistor 222 and resistive element 226 being connected between the second intermediate node 217 and the second voltage node 214, wherein the resistive element 226 is configured to have a predetermined temperature coefficient of resistance for compensating variations in the operating characteristics of the linear current mirror and third and fourth transistors with temperature.
35. A circuit comprising an oscillator as claimed in any of claims 13 to 18, wherein said reference voltage means comprises: first and second voltage nodes for receiving first and second applied voltages respectively; first and second intermediate nodes for producing reference voltages; a linear current mirror circuit comprising a first transistor 216 controlled in accordance with the voltage level at the second intermediate node 217 and connected between the first voltage node 212 and the first intermediate node and a second transistor 218 controlled in accordance with the voltage level at the second intermediate node 217 connected between the first voltage node 212 and the second intermediate node 217; and a nonlinear current mirror circuit comprising a third transistor 220 controlled in accordance with the voltage level at the first intermediate node and connected between the second voltage node 214 and the first intermediate node and a fourth transistor 222, larger than the third transistor 220, controlled in accordance with the voltage level at the first intermediate node and connected in series with a resistive element 226, said serially connected fourth transistor 222 and resistive element 226 being connected between the second intermediate node 217 and the second voltage node 214, wherein the reference voltages at the first and second intermediate nodes are determined by an operating point defined by the combination of linear and nonlinear current mirrors, said resistive element 226 being configured to have a temperature coefficient of resistance determined to substantially prevent the variation of said operating point with temperature.
Description:
AN AMPLICATION CIRCUIT AND AN OSCILLATOR COMPRISING SAID CIRCUIT The present invention relates to amplification circuitry.

Amplifiers are commonly made by combining a differential amplifier with bias circuitry for biasing the differential amplifier. Once common type of circuitry having this configuration is the well known long tail pair where the bias circuitry is a resistor which draws a constant current from the differential amplifier. A variation on this circuitry replaces the resistor with a constant current source. In these circuits the differential amplifier will amplify a small difference between the signal provided at its inputs to produce a large signal at its output, the value of the signal at the output will depend upon the difference between the values of the signals providing inputs to the differential amplifier and the sense of the difference between the values of the signals input to the differential amplifier.

When the relative sizes of the input signals to the differential amplifier varies the sense of the difference changes a rapid change in the output signal of the differential amplifier is required. However, stray capacitance within the differential amplifier may reduce the switching speed. One way of increasing the switching speed is to use a more powerful bias circuitry such as a constant current source which draws a larger current. However, one problem with this approach is that the larger constant current source will continually draw a larger current which uses up power when it is not required to increase the switching speed of the amplifier. It would be desirable to provide an amplifier which has increased switching speed and which does not use excessive power.

Accordingly, the present invention provides an amplification circuit, comprising: a differential amplifier having a first input node and a second input node for receiving respectively first and second input signals and an output node for producing an output signal; and active bias circuitry connected to said differential amplifier for drawing a bias current therefrom, wherein said active bias circuitry is configured to draw an increased current when said first and second input signals are substantially equal.

The present invention also provides an oscillator which comprises the above-described amplification circuit and reference voltage means for providing a constant reference voltage at said first input node and control means for providing a time varying voltage at said second input node.

A preferred embodiment of the present invention will now be described hereinbelow by way of example only with reference to the accompanying drawings, in which: Figure 1 illustrates an oscillator 200; Figure 2 illustrates the output signal 201 of the oscillator 200 and the signal 231 developed across the capacitor 290 in the oscillator 200; Figure 3 illustrates how the output reference signal 213 and the bias signal 211 of the voltage reference source 210 vary with the applied voltage Vdd; Figure 4 illustrates a reference voltage source 210 which is a component of the oscillator 200 illustrated in Figure 1; Figure 5 illustrates the operating characteristics of the linear and non-linear current mirrors which form part of the reference voltage source 210; and Figure 6 illustrates an operational amplifier 230 which is a component of the oscillator 200 illustrated in Figure 1.

Referring to Figure 1, an oscillator 200 provides an output signal 201 having a form illustrated in Figure 2. The oscillator 200 has a reference voltage source 210 connected between a first input 212 at a positive voltage Vdd and a second input 214 which is grounded. The voltage source 210 produces a bias output signal 211 and a reference output

signal 213. The bias output signal 211 is connected to the gate of a p-channel field effect transistor 270 which has its source connected to a positive voltage Vdd and its drain connected to a node 202. The reference output signal 213 is supplied as an input to both a non-inverting input 236 and a first bias input 238 of an operational amplifier 230. The node 202 is connected to an inverting input 240 and a second bias input 242 of the operational amplifier 230 and supplies signal 231 thereto. The operational amplifier 230 is connected between a positive voltage Vdd and ground by respective terminals 232 and 234.

The output signal 201 of the operational amplifier 230 is provided to the gate of an n- channel field effect transistor 280 and as the output of the oscillator. The field effect transistor 280 has its drain connected to the node 202 and has its source connected to ground. The node 202 is connected via a capacitor 290 to ground.

The operational amplifier 230 in combination with the capacitor 290 operates as a oscillator producing an output signal 201 as illustrated in Figure 2. The period of the oscillating signal 201 is determined by the value of the capacitor 290.

The bias output signal 211 (Vp) has a determined relationship to the reference output signal 213 (Vref) for a particular supply voltage (Vdd) applied across the first and second inputs 212,214 of the reference voltage source 210 as illustrated in Figure 3. This figure illustrates how the outputs from the reference voltage source 210 vary with applied battery voltage Vdd. The value of Vdd in use is about 1 V. At this value reference signal 213 (Vref) is constant at 680 mV. Referring to Figure 3, it can be seen that above an applied voltage Vdd of approximately 1 V the voltage at terminal 212 (Vdd) minus the bias voltage signal 211 (Vp) is a constant, that is, Vdd-Vp = 1020 mV, and that the reference voltage signal 213 (Vref) minus the voltage at terminal 214 (earth) is a constant, that is, Vref is 680 mV above ground. Consequently, the bias voltage signal 211 supplies a constant voltage with respect to Vdd and the reference voltage signal supplies a constant voltage with respect to ground. The transistor 270 is controlled by bias signal 211 and acts as a constant low current (-10 nA) source. This low current charges the capacitor 290. The voltage developed across the capacitor, the signal 231, is illustrated in Figure 2. When the voltage

across the capacitor increases above the value Vref of the reference signal 213, output signal 201 of the operational amplifier 230 increases very quickly. A feedback loop containing the transistor 280 is used to quickly bring the high output signal 201 back to zero. A high value for signal 201 switches on transistor 280 which rapidly discharges the capacitor, rapidly decreasing the voltage across the capacitor 290 and causing the output signal 201 of the oscillator to return to zero, which switches off the transistor 280. The current source 270 continues to charge the capacitor 290 and the voltage at node 202 rises again. The constant current source transistor 270 is smaller than, that is, has a smaller channel width to channel length ratio than, the transistor 280.

Referring to Figure 4, the voltage reference source 210 is illustrated in further detail. The circuit has: a p-channel field effect transistor 216 whose source is connected to a positive voltage Vdd at the input node 212 and whose drain is connected to a first output node 215 which produces the output reference signal 213; an n-channel field effect transistor 220 whose drain is connected to the first output node 215 and whose source is connected to ground at the input node 214; another p-channel field effect transistor 218 whose source is connected to a positive voltage at the input node 212 and whose drain is connected to a second output node 217 which supplies the bias signal 211; and another n-channel field effect transistor 222 whose drain is connected to the second output node 217 and whose source is connected in series with a resistor 226 to ground at the input node 214. The gates of the p-channel transistors 216 and 218 are interconnected and in addition are connected to the second output node 217. The gates of the n-channel transistors 220 and 222 are interconnected and in addition are connected to the first output node 215. The output node 215 and output node 217 are interconnected via a capacitor 224.

The p-channel transistors 216 and 218 are identical and form part of a symmetric current mirror. The transistors 216 and 218 have channel widths of 10 um and channel lengths of 50 um. The n-channel transistors 220 and 222 are not identical and with the resistor 226 form part of an asymmetric non-linear current mirror. The transistor 222 is larger than the transistor 220, that is, it has a larger channel width to channel length ratio. The transistor

222 in this embodiment has a width of 50 um and a length of 5 pm whereas the transistor 220 has a width of 50 um and a width of 10 um. The operating characteristics of the current mirrors are illustrated in Figure 5. Curve A is associated with the non-linear current mirror. Curve B is associated with the linear current mirror. There are two stable operating points X and Y. The capacitor 224 is used to ensure that the point Y is the actual operating point as opposed to the point X. The output signals 213 and 211 are illustrated in Figure 3. It will be appreciated that for an applied voltage Vdd of greater than about 1 V the output voltage signals 213 is independent of fluctuations in the voltage supply. The value of the resistance 226 and the characteristics of the transistors 220 and 222 determine the shape of curve A in Figure 2e. The value of the resistance 226 is chosen so that the operating point X is correctly located. Thermal characteristics of the resistor are chosen such that they compensate for the change in the operating characteristics of the transistors 220 and 222 with a change in temperature. This allows the characteristics of the non-linear current mirror to remain stable with temperature and for the operating point X in Figure 2d to remain stable with temperature. Consequently, the resistor 226 allows the voltage reference 210 to produce reference voltages which are substantially independent of the applied voltage Vdd and substantially independent of the ambient temperature. The resistor 226 is composed of a resistor 228a connected in series with a resistor 228b. The resistor 228a has a positive temperature coefficient and the resistor 228b has a negative temperature coefficient. The combination of positive and negative temperature coefficients of the resistors 228a and 228b results in the combined resistance 226 having a chosen temperature coefficient and chosen resistance. According to one example, the resistor 228a may be formed from n-doped silicon having a resistance of 821 kOhms and a temperature coefficient of 6.7 mV/K, the resistor 228b is formed from polysilicon and has a temperature coefficient of-1.7 mV/K and a value of 179 kOhms. This results in the resistance 226 having a value of 1 MOhm with a temperature coefficient of 5.2 mV/K. The resistor 226 has a temperature coefficient which is intermediate of the two resistors 228a and 228b. The characteristics of the resistor 226 is varied by adding different component resistors in series. In this manner a desired temperature coefficient can be obtained.

Alternatively, the resistor 226 can have a designed temperature coefficient which

compensates for variations in the operation of the transistor 270 (Figure 1) and/or the operational amplifier 230 (Figure 1) and/or the transistors 216,218,220 and 226 of the reference voltage source 210 (Figure 4) with temperature. Consequently the oscillator 200 may have operational characteristics substantially independent of temperature variations.

Referring to Figure 6, the operational amplifier 230 is described in further detail. A differential amplifier 241 is connected between a positive voltage Vdd at terminal 232, through an active bias 250 to earth at terminal 234. The differential amplifier 241 has a first input 236 and a second input 240. The first input 236 receives the reference signal 213 illustrated in Figure 2d. The second input receives the signal 231 developed across capacitor 290, illustrated in Figure 2c. The differential amplifier has an output node 245.

The active bias circuitry 250 has a first bias input 238 and a second bias input 242. The first bias input 238 receives the reference signal 213 and the second bias input 242 receives the signal 231. The output of the differential amplifier 241 is passed through an amplifier 260 having a p-channel transistor 262 with a gate connected to the output node connected in series via an output node 266 with an n-channel transistor 264 whose gate is connected to the first bias input 238. The output of the amplifier 260 passes through inverting amplifier 266, and inverting amplifier 268 to produce the output signal 201 of the operational amplifier 230.

The differential amplifier 241 has: a first p-channel transistor 242 with its source connected to the positive voltage Vdd at the terminal 232 and its drain connected to an intermediate node 243, a first n-channel field effect transistor 246 with its source connected to the intermediate node 243 and its drain connected to a node 247, a second p-channel field effect transistor 244 with its source connected to the positive voltage Vdd at the terminal 232 and its drain connected to an output node 245, and a second n-channel field effect transistor 248 with its drain connected to the output node 245 and its source connected to the node 247. The gates of the p-channel transistors 242 and 244 are interconnected and in addition connected to the intermediate node 243. The gate of the first n-channel transistor 246 is connected to the first input 236 of the operational amplifier 230 and receives the

reference signal 213. The gate of the second n-channel field effect transistor 248 is connected to the second input 240 of the operational amplifier 230 and receives the signal 231 developed across capacitor 290. The node 247 is connected to the active load 250.

The p-channel transistors 242 and 244 have channel widths of 1 um and channel lengths of 1 um. The n-channel transistors 246 and 248 have channel widths of 10 um and channel lengths of 1 um. The first p-channel transistor 242 and the second p-channel transistor 244 form a current mirror. The first n-channel transistor 246 and the second n-channel transistor 248 from the input stage of the differential amplifier 241. The first p-channel transistor 242 loads the first n-channel transistor. The second p-channel transistor 244 loads the second n-channel transistor.

The active bias circuitry 250 has: a first n-channel transistor 252 connected between the node 247 and the earth 234 and a second n-channel transistor 254 connected between the node 247 and the earth 234. The gate of the first n-channel transistor 252 is connected to the first bias input 238 and receives the reference signal 213. The gate of the n-channel transistor 254 is connected to the second bias input 242 and receives the signal 231 developed across the capacitor 290. The signal 231 is illustrated in Figure 2c. The signal 213 is illustrated in Figure 2d and is a constant reference level of 680 mV. The transistor 252 acts as a constant current source and is always on. The transistor 254 is normally not fully switched on. However, when the signal 231 reaches a value greater than the reference signal 213, that is, 680 mV, the transistor 254 turns fully on allowing node 245 to be quickly pulled to a low voltage and allowing the output signal 201 to go high. The increase in the output signal 201 causes the signal 231, via transistor 280, to decrease. The operational amplifier 230 acts as a comparator. The operational amplifier 230 only draws appreciable current while the output signal 201 pulses high for a few microseconds. The amplifier therefore uses little power while providing a fast switching speed. The n-channel transistor 252 has a channel length of 2pm and a channel length of 5 pm. The n-channel transistor 254 has a channel length of 0.6 um and a channel width of 10 Mm.

Finally, it will be understood that the present invention has been described in its preferred embodiments and can be modified in many different ways within the scope of the appended claims.




 
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