Title:
ANTI-FUSE STRUCTURE, ANTI-FUSE ARRAY AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/000664
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure are an anti-fuse structure, an anti-fuse array and a preparation method therefor. The anti-fuse structure comprises: a substrate; a switch device, comprising a first gate structure, a second gate structure, a first doped region, a second doped region and a third doped region, wherein the first gate structure and the second gate structure are arranged on the substrate, the first doped region and the second doped region are respectively located in the substrate on two sides of the first gate structure, and the second doped region and the third doped region are respectively located in the substrate on two sides of the second gate structure; and an anti-fuse device, comprising a third gate structure and the third doped region, wherein the second gate structure and the third gate structure are respectively located on the substrate on two sides of the third doped region, and the doped regions are used for forming source electrodes or drain electrodes therein.
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Inventors:
HOU CHUANGMING (CN)
Application Number:
PCT/CN2022/105529
Publication Date:
January 04, 2024
Filing Date:
July 13, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/525
Foreign References:
| CN108336058A | 2018-07-27 | |||
| CN113496988A | 2021-10-12 | |||
| CN106469726A | 2017-03-01 | |||
| CN106067459A | 2016-11-02 | |||
| US9589971B1 | 2017-03-07 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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