The present invention is related to the field of the processing of very large scale integrated (VLSI) circuits, and particularly concerns the fabrication of an inter-silicide capacitor in such VLSI circuits.

Background Art Various capacitor structures have been investigated for use in VLSI circuits. For example, in the prior art a poly-to-poly capacitor, a metal-to-poly capacitor and a metal-to-polycide capacitor have been suggested and used. See for example, C. Kaya, H. Tigelaar, J. Paterson, M. de Wit, J. Fattamso, D. Hester, S. Kiriakai, K. Tan, F. Tsay, Polvcide/Metal Capacitors for High Precision A/D Converters. IEDM, 1988, pp. 782-785.

The voltage linearity of a capacitor is the change in normalized capacitance of the capacitor per unit change in the voltage across the capacitor. A smaller linearity implies a more stable capacitance, which is desirable. In poly-to-poly capacitors, increasing doping concentration of the polysilicon electrodes of a capacitor reduces the voltage linearity of the capacitor. However, as the circuit density of VLSI circuits increases, high doping of polysilicon can result in an increased potential for a leakage current through the oxide. See, for example, T. Ono, T. Mori, T. Ajioka, T. Takayashiki, Studies of Thin Polv Si

Oxides for E and E pRQM. IEDM, 1985, pp. 380-383, and T. lida, M. Nakahara, S. Gotoh and H. Akiba, Precise Capacitor Structure Suitable for Submicron Mixed Analog/Digital ASICs. Custom Integrated Circuits Conference, 1990, pp. 18.5.1-18.5.4. Additionally, the fabrication of poly-to-poly capacitors generally requires high temperature doping and oxidation steps, which can adversely affect reliability and performance of the integrated circuit components. Also, the metal-to-poly capacitor and the metal-to-polycide require additional processing steps which add to the complexity of the circuit and in many cases adversely

affect reliability, or compromise performance. For poly-to-poly capacitors in which the top electrode is polycide, the capacitor has poor characteristics which require additional processing. The additional processing can be cost prohibitive.

Disclosure of the Invention In accordance with the preferred embodiment of the present invention, a method is presented for producing a capacitor during the course of integrated circuit fabrication. On a substrate, a polysilicon layer is formed over an insulating region. A first metal-silicide layer is formed on top of the polysilicon layer. A dielectric layer is formed on top of the first metal-silicide layer. A second metal-silicide layer is formed on top of the dielectric layer. The second metal- silicide layer and the dielectric layer are etched to form a top electrode and dielectric region. The first metal-silicide layer and the polysilicon layer are etched to form a bottom electrode.

In the preferred embodiment of the present invention, the first metal suicide layer and the second metal suicide layer are composed of Tungsten- silicide. The dielectric layer is, for example, a deposited silicon oxide using TEOS as the source of the silicon (also referred to as TEOS oxide). The first metal-silicide layer is etched so that the bottom electrode has a greater area than the top electrode. The polysilicon layer and the first metal suicide layer are also used to form gates for transistors on the integrated circuit.

The present invention has several advantages over the prior art processes. For example, the present invention provides for a method which is simple, practical and fully compatible with current VLSI processes. Integrating the capacitor of the present invention into a polycide-gate integrated circuit process does not perturb the characteristics of the integrated circuit components. Moreover, the resulting capacitor has superior linearity and low current leakage.

The superior linearity results from the high conductivity of the capacitor electrodes. Further, the steps which are additional to conventional processing may be performed at relatively low processing temperatures, preserving reliability and performance of the VLSI circuitry.

Brief Description of the Drawings Figures 1 , 2, 3 and 4 illustrate a method for producing an inter-silicide capacitor for use in integrated circuits in accordance with the preferred embodiment of the present invention. Figures 5 and 6 illustrate methods for producing a capacitor for use in integrated circuits in accordance with alternate embodiments of the present invention

Description of the Preferred Embodiment The present invention provides a method for fabricating a capacitor which is simple, practical and fully compatible with current VLSI processes. In the discussion below, conventional implant steps, such as implants for threshold voltage and substrate doping adjustments, or implants to form source/drain regions and isolation regions, are omitted as they are not germane to the formation of capacitors according to the preferred embodiment of the present invention.

Figure 1 shows the result of conventional semiconductor processing. On a substrate 20, a local oxidation of silicon (LOCOS) process or other process is used to form an insulating layer 25 of, for example, field oxide on the substrate as shown. For example, in a LOCOS process, a layer of pad oxide is formed. On top of the pad oxide, a layer of nitride is formed. The nitride is patterned and etched. Field oxide is grown on the substrate at places where the nitride has

been etched to expose the substrate. The nitride and pad oxide are then removed.

After insulating layer 25 is formed, a layer of gate oxide 35 is placed (i.e. grown or deposited) on exposed portions of the substrate. A layer of polysilicon 26 is deposited over the layer of gate oxide 35 and insulating layer 25. For example, the deposition may be a chemical vapor deposition (CVD). The polysilicon is doped, for example, with n-type atoms at approximately 10 ² 0 atoms per cubic centimeter. The doping may be performed using POCI3. Alternately, an implant of Phosphorus or Arsenic atoms may be used. A metal- suicide layer 27 is formed on top of polysilicon layer 26, for example by chemical vapor deposition at approximately 400 degrees Centigrade or by sputtering at approximately 200 degrees Centigrade. For example, the metal-silicide may be Tungsten-silicide. The metal used for metal-silicide layer 27 may alternately consist of, for example, Titanium (W) Molybdenum (Mo), Chromium (Cr), Nickel (Ni), Cobalt (Co), or Tantalum (Ta).

Figure 2 and Figure 3 illustrate additional processing steps which, when added to conventional processing, allow for the formation of an inter-silicide oxide capacitor. As illustrated by Figure 2, a dielectric layer 28 is formed on top of metal-silicide layer region. Dielectric layer 28 may be, for example, a deposited silicon oxide using TEOS as the source of the silicon (also referred to as TEOS oxide). When deposited, the TEOS oxide is approximately 0.1 microns thick. Alternate source of silicon for the deposited oxide are silane and dichlorosiiane. Alternative to the use of deposited oxide, thermally grown oxide may be used. Also, as an alternative to using an oxide dielectric, a sandwich of oxide, nitride and oxide sub-layers may be used for dielectric layer 28. As is understood in the art, the formation of the oxide, nitride and oxide sublayers may be achieved using processing operating at temperatures below 850 degrees Centigrade.

A metal-silicide layer 29 is formed on top of dielectric layer 28, for example by chemical vapor deposition at approximately 400 degrees Centigrade or by sputtering at approximately 200 degrees Centigrade. For example, the metal-silicide may be Tungsten-silicide. The metal used for metal- suicide layer 29 may alternately consist of, for example, Titanium (W)

Molybdenum (Mo), Chromium (Cr), Nickel (Ni), Cobalt (Co), or Tantalum (Ta). When formed, metal-silicide layer 29 is, for example, 0.2 microns thick.

As illustrated by Figure 3, a conventional mask and etch process is used to form a top electrode 129 and a dielectric region 128. As is understood in the art, dimensions for top electrode 129 and dielectric region 128 can vary significantly depending, for example, on the size of the capacitor required by the integrated circuit design. Once the etch is complete, the resist mask is removed. The depth of the etch of metal-silicide layer 29 and dielectric layer 28 to form top electrode 129 and dielectric region 128 is controlled so that the etch stops at layer 27.

As illustrated by Figure 4, conventional processing steps are resumed. A conventional mask and etch process is used to form a conventional gate consisting of a dielectric region 235, polysilicon region 226 and metal-silicide region 227. During this mask and etch, a bottom electrode for the capacitor is formed. The bottom electrode consists of a metal-silicide region 127 on top of a polysilicon region 126. Further processing is conventional. For example, an insulating layer of a BPSG layer on top of a deposited silicon oxide layer are deposited over the wafer. For example, the deposited silicon oxide layer is .15 microns and the BPSG layer is .4 microns. The insulating layer is masked and etched to produce connection holes. A metal layer is then deposited. The metal layer, through the connection holes, is electrically connected to metal suicide region 127, metal suicide region 129 and metal suicide region 227.

The present invention has several advantages over the prior art processes. For example, the present invention provides for a method which is simple, practical and fully compatible with current VLSI processes using polycide transistor gates. The performance characteristics of the integrated circuit components are unperturbed. The resulting capacitor has superior linearity and low current leakage. Further, the additional steps which are additional to conventional processing may be performed at relatively low processing temperatures (e.g., less than 850 degrees Centigrade), preserving reliability of the VLSI circuitry. Several alternate embodiments of the present invention exist. For example, instead of metal-silicide layer 29, a doped polysilicon layer may be formed. The remaining processing steps remain the same. The resulting structure is shown in Figure 5 where a resulting top electrode 329 is doped polysilicon. Additionally, the present invention may be utilized when the gate is formed of doped polysilicon. In this case, the formation of metal suicide layer 27 is omitted. Polysilicon layer 26 is doped, for example, with n-type atoms at approximately 5 x 10 ²⁰ atoms per cubic centimeter. The doping may be performed using POCI3. Alternately, an implant of Phosphorus or Arsenic atoms may be used. The resulting structure is shown in Figure 6. There, a conventional polysilicon gate structure is shown to consist of a doped polysilicon region 426 placed over dielectric region 235. The bottom electrode for the capacitor consists of a doped polysilicon region 326.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly,

the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.