BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5 th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various operations for on-chip communication at a baseband chip.

SUMMARY

[0003] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a first set of baseband circuits configured to perform a first set of baseband operations. The baseband chip may include a second set of baseband circuits configured to perform a second set of baseband operations different from the first set of baseband operations. The baseband chip may include a first data interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first data information within the first set of baseband circuits. The baseband chip may include a first control interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first control information within the first set of baseband circuits. The baseband chip may include a second data interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The baseband chip may include a second control interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection.

[0004] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include a radio (RF) chip configured to receive control channel (CCH) information and shared channel (SCH) information from a base station. The apparatus may further include a baseband chip coupled to the baseband chip. The baseband chip may include a first set of baseband circuits configured to perform a first set of baseband operations. The baseband chip may include a second set of baseband circuits configured to perform a second set of baseband operations different from the first set of baseband operations. The baseband chip may include a first data interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first data information within the first set of baseband circuits. The baseband chip may include a first control interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first control information within the first set of baseband circuits. The baseband chip may include a second data interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The baseband chip may include a second control interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection.

[0005] According to still another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include performing, by a first set of baseband circuits, a first set of baseband operations. The method may include performing, by a second set of baseband circuits, a second set of baseband operations different from the first set of baseband operations. The method may include enabling, by a first data interconnection coupled to the first set of baseband circuits, a transfer of first data information within the first set of baseband circuits. The method may include enabling, by a first control interconnection coupled to the first set of baseband circuits, a transfer of first control information within the first set of baseband circuits. The method may include enabling, by a second data interconnection coupled to the second set of baseband circuits, a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The method may include enabling, by a second control interconnection coupled to the second set of baseband circuits, a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection. [0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 A illustrates a block diagram of an example baseband chip.

[0009] FIG. IB illustrates a block diagram of the example baseband chip of FIG. 1A with power-gating applied to interconnect subsystems and baseband circuits.

[0010] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0011] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0012] FIG. 4 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0013] FIG. 5A illustrates a detailed view of a first exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure.

[0014] FIG. 5B illustrates a detailed view of the first exemplary baseband chip of FIG. 5 A with power-gating applied to various baseband circuits and interconnect subsystems, according to some embodiments of the present disclosure.

[0015] FIG. 5C illustrates a detailed view of a second exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure.

[0016] FIG. 5D illustrates a detailed view of the second exemplary baseband chip of FIG. 5B with power-gating applied to various baseband circuits and interconnect subsystems, according to some embodiments of the present disclosure.

[0017] FIG. 5E illustrates a detailed view of a third exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure.

[0018] FIG. 5F illustrates a detailed view of the third exemplary baseband chip of FIG. 5E with power-gating applied to various baseband circuits and interconnect subsystems, according to some embodiments of the present disclosure.

[0019] FIG. 5G illustrates a detailed view of a fourth exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure. [0020] FIG. 5H illustrates a detailed view of a fifth exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure.

[0021] FIG. 51 illustrates a detailed view of a sixth exemplary baseband chip of the apparatus of FIG. 4, according to some embodiments of the present disclosure.

[0022] FIG. 6 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0023] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0024] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0025] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0026] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0027] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0028] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0029] As used herein, the term “baseband circuit” may refer to an integrated circuit (IC) formed on a baseband chip and configured to perform one or more operations and/or computations associated with baseband signal processing. Still further, as used herein, a “set of baseband circuits” may refer to one or more baseband circuits coupled to the same data interconnection and control interconnection. In some embodiments, the set of baseband circuits may be grouped based on whether they remain active during a reduced-traffic scenario and/or whether they are deactivated during a reduced-traffic scenario. However, one or more baseband circuits may be grouped into a set based on any other reason without departing from the scope of the present disclosure.

[0030] As used herein, the term “interconnection” may refer to any type of infra-chip (also referred to herein as “on-chip”) or inter-chip communication subsystem and/or network that carries data information and/or control messages between circuits, firmware, or software located on the same chip die or separate chip dies. For example, the interconnection(s) described herein may include, e.g., a network-on-chip (NoC) interconnection, a bus interconnection, a point-to-point interconnection, an Advanced Interface Bus (AIB) interconnection, a Universal Interface Bus (UIB) interconnection, a HyperTransport interconnection, a Low-voltage-In-Package- INterCONnect (LIPINCON), a Cache Coherent Interconnect for Accelerators (CCIX), a Gen-Z interconnection, an Open Coherent Accelerator Processor Interface (OpenCAPI) interconnection, an optical interconnection, an electrical interconnection, a wired interconnection, a wireless interconnection, a mesh interconnection, just to name a few. In some embodiments, an interconnection may be configured to carry either data information or control information. An interconnection that communicates data information may be referred to as a “data interconnection, and an interconnection that communicates control information may be referred to as a “control interconnection.”

[0031] As used herein, the term “data information” may refer to any type of baseband information or a baseband signal that is generated by, e.g., a baseband circuit, a baseband hardware accelerator, a baseband firmware, a baseband processor, etc., using baseband signal processing. As used herein, the term “control message” may refer to any type of command, instruction, control data, etc., that is sent between baseband circuits, baseband hardware accelerators, baseband firmware, baseband processors, or a combination thereof, for example.

[0032] For example, a first baseband circuit may perform first baseband signal processing of an input signal to generate data information, which may be output to a second baseband circuit via a data interconnection. In some examples, the first baseband circuit may send a control message that includes a command or instruction to the second baseband circuit via a control interconnection. The control message may cause the second baseband circuit to initiate second baseband signal processing of the data information received via the data interconnection, in some embodiments. [0033] Accordingly, a first data interconnection coupled to a first set of baseband circuits may be configured to communicate data information between the baseband circuits in the first set of baseband circuits. A first control interconnection coupled to the first set of baseband circuits may be configured to communicate control information between the baseband circuits in the first set of baseband circuits. A second data interconnection coupled to a second set of baseband circuits may be configured to communicate second data information between the baseband circuits in the second set of baseband circuits. A second control interconnection coupled to the second set of baseband circuits may be configured to communicate second control information between the baseband circuits of the second set of baseband circuits.

[0034] In some embodiments, the first data interconnection and the second data interconnection may be coupled by a first wired or wireless connection and configured to communicate data information between the first set of baseband circuits and the second set of baseband circuits. Similarly, the first control interconnection and the second control interconnection may be coupled by a second wired or wireless connection and configured to communicate control information between the first set of baseband circuits and the second set of baseband circuits.

[0035] In wireless communication, a user equipment typically performs operations associated with cell searching/measurement, control channel (CCH) processing, and shared channel (SCH) processing using its baseband chip. To perform such functions, some baseband chips may be designed with dedicated baseband circuits each configured to perform a specific operation associated with baseband signal processing. The transfer of information between the baseband circuits may be accomplished using an interconnection subsystem, which acts as the on- chip communication backbone of the baseband chip.

[0036] Some interconnection subsystems suffer from various challenges, however. For example, some interconnection subsystems lack scalability and predictability. Consequently, these interconnection subsystems may not achieve the desired performance for a baseband chip with a multi -baseb and circuit architecture. Thus, to meet these design productivity and signal integrity challenges, various other interconnection subsystems have been proposed. One such example is depicted in FIGs. 1A and IB.

[0037] As shown, FIG. 1A illustrates a block diagram 100 of a baseband chip 150 that includes a multi-baseband circuit architecture with data and control interconnections. FIG. IB illustrates a block diagram 101 of the baseband chip 150 of FIG. 1 A operating in a reduced-power mode.

[0038] Referring to FIGs. 1A and IB, baseband chip 150 includes a data interconnection 120 to facilitate the on-chip transfer of data information and a control interconnection 130 to facilitate the on-chip transfer of control messages. The multi-baseband circuit architecture of baseband chip 150 may include, e.g., a digital front-end (DFE) circuit 102, a physical (PHY) layer transmitter (TX) 104, a demodulator (DMD) circuit 106, a decoder (DEC) circuit 108, a cell search/measurement (SRCH) circuit 110, and a feedback (FB) circuit 112, for example. Each of the baseband circuits may be configured to perform one or more baseband signal processing, as described below.

[0039] For example, DFE circuit 102 may be coupled to an RF chip (not shown) and configured to convert an analog-to-digital converter (ADC) output signal to a fast Fourier transform (FFT) input signal and to convert an inverse-FFT (iFFT) output signal to an ADC input signal. DMD circuit 106 may perform channel estimation and de-mapping of a multiple-input multiple-output (MIMO) constellation to generate log-likelihood ratio (LLR) metrics associated with an estimated bit-stream transmitted by the base station. DEC circuit 108 may decode code blocks into information bits. SRCH circuit 110 may acquire cell identification (ID), frequency and timing error through synchronization sequences, such as a primary synchronization sequence (PSS) and a secondary synchronization sequence (SSS).

[0040] As mentioned above, the information output by one baseband circuit may be used as the input to another baseband circuit. Thus, data information and control messages may be transferred between baseband circuits via data interconnection 120 and control interconnection 130, respectively. While the inclusion of data interconnection 120 and control interconnection 130 helps to avoid some of the above-mentioned problems of interconnection subsystems, the example interconnections of FIGs. 1A and IB still consume an undesirable amount of power and cause leakage current. This is due to the length of these interconnections. For instance, baseband circuits may be spread out across the baseband chip die, and the amount of power consumed by an interconnection may be, in part, related to its length. Moreover, a longer interconnection may create more leakage current than a shorter interconnection, in some instances. These powerconsumption and leakage current challenges may be made worse during certain reduced-traffic reception conditions, e.g., such as discontinuous reception (DRX) (e.g., connected-mode DRX (CDRX), idle-mode DRX (IDRX), etc.), low throughput and physical downlink control channel (PDCCH)-only reception.

[0041] As depicted in FIG. IB, when baseband chip 150 enters a reduced-traffic mode (e.g., CDRX mode, IDRX, PDCCH-only mode, etc.), certain baseband circuits (e.g., PHY TX 104, FB circuit 112, DMD circuit 106, DEC circuit 108, etc.) may be power-gated to conserve power, while others remain active. Because information is communicated between active baseband chips while in reduced-traffic mode, power-gating of data interconnection 120 and control interconnection 130 may not be possible. Therefore, these interconnections not only use power unnecessarily in regions proximate to power-gated baseband circuits, but they also create leakage current along the entirety of their lengths, which further exacerbates the power-consumption problem of baseband chip 150.

[0042] Thus, there exists an unmet need for an on-chip interconnection subsystem that facilitates on-chip information transfer between active baseband circuits but that consumes less power and creates less leakage current, as compared to the interconnections depicted in FIGs. 1 A and IB.

[0043] To overcome these and other challenges, the present disclosure provides an on-chip communication subsystem that includes multiple data interconnections and control interconnections of reduced length and coupled to different sets of baseband circuits. For example, the on-chip communication subsystem described herein may include a first data interconnection/first control interconnection coupled to a first set of baseband circuits and a second data interconnection/second control interconnection coupled to a second set of baseband circuits. In some embodiments, the baseband circuits may be grouped based on whether they remain active or are activated during a reduced traffic mode. Then, those inactive baseband circuits and the corresponding data interconnection and control interconnection may be power-gated during the reduced-traffic mode. Not only does this exemplary architecture reduce the overall power consumed by the on-chip communication network via power-gating, but it also reduces the amount of leakage current by shortening the length of the interconnections. Various non-limiting examples of the present multi-baseband circuit/multi-interconnection architecture are provided below in connection with FIGs. 5A-5I.

[0044] Although the following description is directed to two sets of baseband circuits and an on-chip interconnection subsystem with two data interconnections and two control interconnections, the concepts provided herein are not limited to this number. Instead, the following description may be extended to any number of sets of baseband circuits, data interconnections, and control interconnections without departing from the scope of the present disclosure.

[0045] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0046] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0047] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0048] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0049] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0050] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0051] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0052] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0053] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0054] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0055] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0056] Referring back to FIG. 2, in some embodiments, user equipment 202 may include a baseband chip with the exemplary architecture described herein. The exemplary architecture may include an on-chip communication subsystem that uses multiple data interconnections and control interconnections of reduced length, and which are coupled to sets of baseband circuits in a way that limits the power consumption and leakage current while in regular-traffic mode and reduce- traffic mode. For instance, the on-chip communication subsystem may include a first data interconnection/first control interconnection coupled to a first set of baseband circuits and a second data interconnection/second control interconnection coupled to a second set of baseband circuits. In some embodiments, the baseband circuits may be grouped based on whether they remain active or are activated during the reduced-traffic mode. Then, those inactive baseband circuits and the corresponding data interconnection/control interconnection may be power-gated during the reduced-traffic mode. Not only does this exemplary architecture reduce the overall power consumed by the on-chip communication network via power-gating, but it also reduces the amount of leakage current by shortening the length of the interconnections. Various non-limiting examples of the exemplary baseband chip architecture are provided below in connection with FIGs. 5A-5F. [0057] FIG. 4 illustrates a block diagram of an apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. Apparatus 400 may be implemented as user equipment 202 of wireless network 200 in FIG. 2. As shown in FIG. 4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by processor 302 and memory 304, and RF chip 404 is implemented by processor 302, memory 304, and transceiver 306, as described above with respect to FIG. 3. Besides the on-chip memory 418 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC, as described above.

[0058] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 414 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface 414. RF chip 404, through the transmitter (TX), may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404.

[0059] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402.

[0060] Still referring to FIG. 4, baseband chip 402 may include an on-chip communication subsystem that includes, e.g., a first data interconnection 420a, a first control interconnection 422a, a second data interconnection 420b, and a second control interconnection 422b. First data interconnection 420a and first control interconnection 422a may be coupled to a first set of baseband circuits 424. Second data interconnection 420b and second control interconnection 422b may be coupled to a second set of baseband circuits 426. Moreover, a controller 428 coupled to each of the baseband circuits and interconnections may be configured to initiate baseband signal processing of the baseband circuits, power-gate certain baseband circuits and/or interconnections during the reduced-traffic mode, remove power-gating when baseband circuits and/or interconnections are activated, etc.

[0061] Moreover, a DMD circuit of baseband chip 402 may be divided into CCH DMD circuit and SCH DMD circuit. Similarly, a DEC circuit may be divided into a CCH DEC circuit and an SCH DEC circuit. By separating the DMD circuit and DEC circuit based on CCH operations and SCH operations, the CCH circuits of first set of baseband circuits 424 may remain active during the reduce-traffic mode, while power-gating may be applied to the SCH circuits of second set of baseband circuits 426. First set of baseband circuits 424 and second set of baseband circuits 426 may include different groupings of, e.g., a DFE circuit, a CCH DEC circuit, a CCH DMD circuit, an SRCH circuit, an FB circuit, an SCH DMD circuit, an SCH DEC circuit, and a PHY TX, depending on the design and/or implementation. Depending on the grouping of baseband circuits, a trade-off between power-savings and leakage current reduction may be achieved, as described below in connection with FIGs. 5A-5I.

[0062] FIG. 5 A illustrates a block diagram 500 depicting a first exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIG. 5B illustrates a block diagram 501 of the first exemplary architecture depicted in FIG. 5 A with powergating, according to some embodiments of the present disclosure. FIG. 5C illustrates a block diagram 503 of a second exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIG. 5D illustrates a block diagram 505 of the second exemplary architecture depicted in FIG. 5C with power-gating, according to some embodiments of the present disclosure. FIG. 5E illustrates a block diagram 507 of a third exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIG. 5F illustrates a block diagram 509 of the third exemplary architecture depicted in FIG. 5E with power gating, according to some embodiments of the present disclosure. FIG. 5G illustrates a block diagram 511 of a detailed view of a fourth exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIG. 5H illustrates a block diagram 513 of a fifth exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIG. 51 illustrates a block diagram 515 of a sixth exemplary architecture of baseband chip 402 of FIG. 4, according to some embodiments of the present disclosure. FIGs. 5A-5I will be described together.

[0063] Referring to FIGs. 5A-5I, when reduced traffic mode signaling is received, baseband chip 402 may enter reduced-traffic mode (e.g., CDRX mode, IDRX mode, PDCCH-only mode, etc.) to conserve power. While in reduced-traffic mode, baseband chip 402 may periodically and/or intermittently monitor the CCH. Thus, first data interconnection 420a, first control interconnection 422a, and one or more of the first set of baseband circuits 424 may remain in active mode to monitor the CCH and perform CCH baseband operations. However, the SCH may not be monitored unless certain information is received via the CCH, or the SCH may be monitored less frequently. Second set of baseband circuits 426 primarily performs operations associated with the SCH. Thus, when the signaling is received, controller 428 may power-gate second data interconnection 420b, second control interconnection 422b, and second set of baseband circuits 426. However, if first set of baseband circuits 424 receives downlink control information (DCI) via the CCH, controller 428 may activate (e.g., remove power-gating) second data interconnection 420b, second control interconnection 422b, SCH DMD circuit 512, and SCH DEC circuit 514. Once activated, demodulation and decoding of the SCH slot, which may be scheduled by the DCI, may be performed. Additional details of the various exemplary architectures are described below. [0064] For example, in the exemplary architecture of FIGs. 5 A and 5B, first set of baseband circuits 424 may include, e.g., DFE circuit 502, CCH DEC circuit 504, and CCH DMD circuit 506. Second set of baseband circuits 426 may include, e.g., SRCH circuit 508, FB circuit 510, SCH DMD circuit 512, SCH DEC circuit 514, and PHY TX 516. Thus, in this embodiment, first data interconnection 420a and first control interconnection 422a are coupled to DFE circuit 502, CCH DEC circuit 504, and CCH DMD circuit 506. On the other hand, second data interconnection 420b and second control interconnection 422b are coupled to, e.g., SRCH circuit 508, FB circuit 510, SCH DMD circuit 512, SCH DEC circuit 514, and PHY TX 516.

[0065] Referring to FIG. 5B, if a synchronization signal (e.g., PSS and/or SSS) is received via the CCH, controller 428 may activate second data interconnection 420b, second control interconnection 422b, and SRCH circuit 508. Still further, if channel state information (CSI) reference signal(s) (CSI-RS) is/are received via the CCH, controller 428 may activate second data interconnection 420b, second control interconnection 422b, and FB circuit 510. FB circuit 510 may feedback channel measurements based on the CSI-RS to the base station.

[0066] The relative density of CSI-RS, synchronization signals, and physical downlink shared channel (PDSCH) slots within the spectrum is sparse, and monitoring for these signals with the same frequency as other portions of the CCH may be unnecessary. Thus, the exemplary architecture described herein may enable a significant reduction of power consumption, as well as reduction in leakage current, as compared to that of baseband chip 150 shown in FIGs. 1A and IB. [0067] However, in some designs and/or implementations, it may be beneficial to include one or more of SRCH circuit 508 and/or FB circuit 510 in first set of baseband circuits 424 instead of second set of baseband circuits 426. This is because baseband circuit 402 may still perform cell search/measurement and/or feedback operations while in reduced-traffic mode, in some instances. Thus, if SRCH circuit 508 obtains information for feedback to the base station, controller 428 may activate second data interconnection 420b and second control interconnection 422b. Here, second data interconnection 420b and second control interconnection 422b may enable the transfer of cell search/measurement information and/or control messages from SRCH circuit 508 to FB circuit 510, still referring to FIG. 5B.

[0068] However, as shown in FIGs. 5C and 5D, SRCH circuit 508 and FB circuit 510 may be placed in first set of baseband circuits 424. Using this architecture, second data interconnection 420b and second control interconnection 422b may remain power-gated during cell search/measurement information and feedback operations. This may achieve greater powersavings related to second data interconnection 420b and second control interconnection 422b, as compared to FIGs. 5 A and 5B. However, more leakage current may be created in this architecture due to the additional length of first data interconnection 420a and first control interconnection 422a.

[0069] For example, first set of baseband circuits 424 in FIGs. 5C and 5D may include, e.g., DFE circuit 502, CCH DEC circuit 504, CCH DMD circuit 506, SRCH circuit 508, and FB circuit 510. In this embodiment, second set of baseband circuits 426 may include, e.g., SCH DMD circuit 512, SCH DEC circuit 514, and PHY TX 516. Thus, the length of first data interconnection 420a and first control interconnection 422a may be increased to accommodate SRCH circuit 508 and FB circuit 510 into first set of baseband circuits 424.

[0070] As shown in FIG. 5D, controller 428 may power-gate second data interconnection 420b, second control interconnection 422b, each baseband circuit in second set of baseband circuits 426, and SRCH circuit 508 and FB circuit 510 in first set of baseband circuits 424. Here again, if a synchronization signal (e.g., PSS and/or SSS) is received via the CCH while baseband chip 402 operates in reduced-traffic mode, controller 428 may activate SRCH circuit 508, which is located in first set of baseband circuits 424. In this embodiment, SRCH circuit 508 may be coupled to first data interconnection 420a and first control interconnection 422a. Therefore, second data interconnection 420b and second control interconnection 422b may remain power-gated in this embodiment.

[0071] Still referring to FIG. 5D, if CSI-RS is/are received via the CCH while baseband chip 402, controller 428 may activate FB circuit 510, while second data interconnection 420b and second control interconnection 422b remain power-gated. Thus, by including SRCH circuit 508 and FB circuit 510 in first set of baseband circuits 424, the exemplary architecture depicted in FIGs. 5C and 5D may achieve greater power savings in some instances but may increase some leakage current, as compared to the architecture of FIGs. 5A and 5B.

[0072] As mentioned above, there may be a trade-off between power-savings attributed to power-gating second data interconnection 420b and second control interconnection 422b for a longer period of time and an increase in leakage current due to the increased length of first data interconnection 420a and first control interconnection 422a. Accordingly, in some scenarios, it may be beneficial to include FB circuit 510 in second set of baseband circuits 426 to mitigate the leakage current, as shown in FIGs. 5E and 5F.

[0073] For instance, first set of baseband circuits 424 in FIGs. 5E and 5F may include, e.g., DFE circuit 502, CCH DEC circuit 504, CCH DMD circuit 506, and SRCH circuit 508. In this embodiment, second set of baseband circuits 426 may include, e.g., FB circuit 510, SCH DMD circuit 512, SCH DEC circuit 514, and PHY TX 516. Thus, the length of second data interconnection 420b and second control interconnection 422b may be longer in this embodiment than those of FIGs. 5C and 5D. This increase in length may create an increase in the associated leakage current, as compared to FIGs. 5C and 5D.

[0074] Referring to FIG. 5F, if a synchronization signal (e.g., PSS and/or SSS) is received via the CCH while in reduced-traffic mode, controller 428 may activate SRCH circuit 508, which is located in first set of baseband circuits 424 in FIGs. 5E and 5F. Here again, because SRCH circuit 508 is coupled to first data interconnection 420a and first control interconnection 422a, second data interconnection 420b and second control interconnection 422b may remain powergated in this embodiment. However, if CSI-RS is/are received via the CCH, controller 428 may activate FB circuit 510, second data interconnection 420b, and second control interconnection 422b. Information may be passed to FB circuit 510 via a connection between first data interconnection 420a/second data interconnection 420b and first control interconnection 422a/second control interconnection 422b.

[0075] Thus, by including FB circuit 510 in second set of baseband circuits 426, the exemplary architecture depicted in FIGs. 5E and 5F may achieve a greater reduction in leakage current associated with first data interconnection 420a and first control interconnection 422a, as compared with the exemplary architecture shown in FIGs. 5C and 5D. However, a greater amount of power may be consumed by second data interconnection 420b and second control interconnection 422b in FIGs. 5E and 5F if regular feedback to the base station occurs. Thus, depending on the desired trade-off between power-gating and leakage current, various groupings of baseband circuits may be considered. [0076] Still further, additional exemplary architectures of baseband chip 402 are shown in FIGs. 5G-5I. Various performance tradeoffs may be achieved using the architectures of FIGs. 5G- 51 that may be the same or different to those described above in connection with FIGs. 5A-5F.

[0077] In the embodiment depicted in FIG. 5G, first set of baseband circuits 424 may include, e.g., DFE 502, CCH DEC 504, CCH DMD 506, and TX 516. Second set of baseband circuits 426 may include, e.g., FB 510, SCH DMD 512, SCH DEC 514, and SRCH 508.

[0078] In the embodiment depicted in FIG. 5H, first set of baseband circuits 424 may include, e.g., DFE 502, CCH DEC 504, CCH DMD 506, SRCH 508, and TX 516. Here, second set of baseband circuits 426 may include, e.g., SCH DMD 512, SCH DEC 514, and FB 510.

[0079] In each of FIGs. 5G and 5H, one or more of the baseband circuits in first set of baseband circuits 424, first data interconnection 420a, and first control interconnection 422a may remain active during a reduced-traffic mode. In some embodiments, one or more of the baseband circuits in first set of baseband circuits 424, second data interconnection 420b, and second control interconnection 422b may be selectively deactivated by controller 428 during reduced-traffic mode.

[0080] As shown in FIG. 51, baseband chip 402 may include three sets of baseband circuits, namely, first set of baseband circuits 424, second set of baseband circuits 426, and third set of baseband circuits 520. First set of baseband circuits 424 may include, e.g., DFE 502, CCH DEC 504, and CCH DMD 506. Second set of baseband circuit(s) may include, e.g., SRCH 508. Third set of baseband circuits 520 may include, e.g., FB 510, SCH DMD 512, SCH DEC 514, and TX 518. Third set of baseband circuits 520 may be coupled to a third data interconnection 420c and a third control interconnection 422c. During reduced traffic mode, controller 428 may selectively deactivate one or more of SRCH 508, second data interconnection 420b, second control interconnection 422b, third data interconnection 420c, third control interconnection 422c, and one or more of the baseband circuits of third set of baseband circuits 520. Various performance tradeoffs may be achieved using more than two sets of baseband circuits and corresponding data/control interconnections. In some embodiments, second set of baseband circuits 426 may include more than one baseband circuit. In some embodiments, more than three sets of baseband circuits, each connected to a dedicated data interconnection and control interconnection, may be provided without departing from the scope of the present disclosure. Still further, baseband circuits other than those examples provided herein may be grouped into one of the sets of baseband circuits without departing from the scope of the present disclosure. [0081] FIG. 6 illustrates a flowchart of an exemplary method 600 of wireless communication, according to embodiments of the disclosure. Exemplary method 600 may be performed by an apparatus for wireless communication, e.g., such as user equipment 202, node 300, apparatus 400, baseband chip 402, first data interconnection 420a, first control interconnection 422a, second control interconnection 422b, first set of baseband circuits 424, second data interconnection 420b, second set of baseband circuits 426, and/or controller 428. Method 600 may include steps 602-612 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 6.

[0082] At 602, the apparatus may perform a first set of baseband operations using a first set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, first set of baseband circuits 424 may perform operations associated with each of its individual circuits. For example, the first set of baseband operations may include one or more of, e.g., DFE operations, CCH DEC operations, CCH DMD operations, SRCH operations, FB operations, etc.

[0083] At 604, the apparatus may perform a second set of baseband operations using a second set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, second set of baseband circuits 424 may perform operations associated with each of its individual circuits. For example, the first set of baseband operations may include one or more of, e.g., SRCH operations, FB operations, SCH DMD operations, SCH DEC operations, PHY TX operations, etc.

[0084] At 606, the apparatus may enable a transfer of first data information within the first set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, first data interconnection 420a may transfer data information between baseband circuits of the first set of baseband circuits 424.

[0085] At 608, the apparatus may enable a transfer of first control information within the first set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, first control interconnection 422a may transfer control information (e.g., control message(s), control command(s), control instruction(s), control data, etc.) between baseband circuits of the first set of baseband circuits 424.

[0086] At 610, the apparatus may enable second data information within the second set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, second data interconnection 420b may transfer data information between baseband circuits of the second set of baseband circuits 426. [0087] At 612, the apparatus may enable a transfer of second control information within the second set of baseband circuits. For example, referring to FIGs. 4 and 5A-5F, second control interconnection 422b may transfer control information (e.g., control message(s), control command(s), control instruction(s), control data, etc.) between baseband circuits of the second set of baseband circuits 426.

[0088] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a first set of baseband circuits configured to perform a first set of baseband operations. The baseband chip may include a second set of baseband circuits configured to perform a second set of baseband operations different from the first set of baseband operations. The baseband chip may include a first data interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first data information within the first set of baseband circuits. The baseband chip may include a first control interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first control information within the first set of baseband circuits. The baseband chip may include a second data interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The baseband chip may include a second control interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection.

[0089] In some embodiments, the baseband chip may further include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the baseband chip may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gating the second set of baseband circuits, the second data interconnection, and the second control interconnection.

[0090] In some embodiments, the first set of baseband circuits may be configured to receive the reduced traffic mode signaling from a base station. In some embodiments, the first set of baseband circuits may be configured to enter a reduced traffic mode based on the reduced traffic mode signaling. In some embodiments, the first set of baseband circuits may be configured to send information associated with the reduce traffic mode signaling to the controller.

[0091] In some embodiments, the reduced traffic mode may include a DRX mode or a PDCCH-only mode. [0092] In some embodiments, the first set of baseband circuits includes a DFE circuit, a CCH decoder, and a CCH demodulator. In some embodiments, the second set of baseband circuits may include a cell search/measurement circuit, an SCH decoder, an SCH demodulator, and a PHY layer TX.

[0093] In some embodiments, the first set of baseband circuits may include a DFE circuit, a CCH decoder, a CCH demodulator, and one or more of a cell search/measurement circuit or a feedback circuit. In some embodiments, the second set of baseband circuits includes an SCH decoder, an SCH demodulator, and a PHY TX.

[0094] In some embodiment, the baseband chip may include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gate the one or more of the cell search/measurement circuit or the feedback circuit of the first set of baseband circuits, the second set of baseband circuits, the second data interconnection, and the second control interconnection during a first period. In some embodiments, the controller may be configured to in response to the CCH decoder receiving DCI, activate from the SCH decoder and the SCH demodulator of the second set of baseband circuits, the second data interconnection, and the second control interconnection during a second period subsequent to the first period.

[0095] In some embodiments, the first set of baseband circuits may be configured to receive the reduced traffic mode signaling and the DCI from a base station. In some embodiments, the first set of baseband circuits may be configured to enter a reduced traffic mode based on the reduced traffic mode signaling. In some embodiments, the first set of baseband circuits may be configured to send information associated with the reduced traffic mode signaling and the DCI to the controller.

[0096] In some embodiments, the controller may be further configured to, in response to the first set of baseband circuits receiving a synchronization sequence, activate from the cell search/measurement circuit during the second period. In some embodiments, the controller may be further configured to, in response to the cell search/measurement circuit receiving a CSI-RS, activate from the feedback circuit during the second period.

[0097] In some embodiments, the first set of baseband circuits may be configured to receive the synchronization sequence and the CSI-RS from a base station. In some embodiments, the first set of baseband circuits may be configured to send information associated with the synchronization sequence and the CSI-RS to the controller.

[0098] In some embodiments, the first set of baseband circuits may include the cell search/measurement circuit. In some embodiments, the second set of baseband circuits may include the feedback circuit.

[0099] In some embodiments, the baseband chip may further include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gate the cell search/measurement circuit of the first set of baseband circuits, the second set of baseband circuits, the second data interconnection, and the second control interconnection during a first period. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving a synchronization sequence, activate from the cell search/measurement circuit during a second period. In some embodiments, the controller may be configured to, in response to the cell search/measurement circuit receiving a CSI-RS, activate from the second data interconnection, the second control interconnection, and the feedback circuit during a second period subsequent to the first period.

[0100] In some embodiment, each of the first data interconnection, the first control interconnection, the second data interconnection, and the second control interconnection may be associated with at least one of an NoC interconnection, a bus interconnection, a point-to-point interconnection, an AIB interconnection, a UIB interconnection, a HyperTransport interconnection, a LIPINCON interconnection, a CCIX, a Gen-Z interconnection, an OpenCAPI interconnection, an optical interconnection, or an electrical interconnection.

[0101] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include an RF chip configured to receive CCH information and SCH information from a base station. The apparatus may further include a baseband chip coupled to the baseband chip. The baseband chip may include a first set of baseband circuits configured to perform a first set of baseband operations. The baseband chip may include a second set of baseband circuits configured to perform a second set of baseband operations different from the first set of baseband operations. The baseband chip may include a first data interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first data information within the first set of baseband circuits. The baseband chip may include a first control interconnection coupled to the first set of baseband circuits and configured to enable a transfer of first control information within the first set of baseband circuits. The baseband chip may include a second data interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The baseband chip may include a second control interconnection coupled to the second set of baseband circuits and configured to enable a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection.

[0102] In some embodiments, the baseband chip may further include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the baseband chip may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gating the second set of baseband circuits, the second data interconnection, and the second control interconnection.

[0103] In some embodiments, the first set of baseband circuits may be configured to receive the reduced traffic mode signaling from a base station. In some embodiments, the first set of baseband circuits may be configured to enter a reduced traffic mode based on the reduced traffic mode signaling. In some embodiments, the first set of baseband circuits may be configured to send information associated with the reduced traffic mode signaling to the controller.

[0104] In some embodiments, the reduced traffic mode may include a DRX mode or a PDCCH-only mode.

[0105] In some embodiments, the first set of baseband circuits includes a DFE circuit, a CCH decoder, and a CCH demodulator. In some embodiments, the second set of baseband circuits may include a cell search/measurement circuit, an SCH decoder, an SCH demodulator, and a PHY layer TX.

[0106] In some embodiments, the first set of baseband circuits may include a DFE circuit, a CCH decoder, a CCH demodulator, and one or more of a cell search/measurement circuit or a feedback circuit. In some embodiments, the second set of baseband circuits includes an SCH decoder, an SCH demodulator, and a PHY TX.

[0107] In some embodiment, the baseband chip may include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gate the one or more of the cell search/measurement circuit or the feedback circuit of the first set of baseband circuits, the second set of baseband circuits, the second data interconnection, and the second control interconnection during a first period. In some embodiments, the controller may be configured to in response to the CCH decoder receiving DCI, activate from the SCH decoder and the SCH demodulator of the second set of baseband circuits, the second data interconnection, and the second control interconnection during a second period subsequent to the first period.

[0108] In some embodiments, the first set of baseband circuits may be configured to receive the reduced traffic mode signaling and the DCI from a base station. In some embodiments, the first set of baseband circuits may be configured to enter a reduced traffic mode based on the reduced traffic mode signaling. In some embodiments, the first set of baseband circuits may be configured to send information associated with the reduced traffic mode signaling and the DCI to the controller.

[0109] In some embodiments, the controller may be further configured to, in response to the first set of baseband circuits receiving a synchronization sequence, activate from the cell search/measurement circuit during the second period. In some embodiments, the controller may be further configured to, in response to the cell search/measurement circuit receiving a CSI-RS, activate from the feedback circuit during the second period.

[0110] In some embodiments, the first set of baseband circuits may be configured to receive the synchronization sequence and the CSI-RS from a base station. In some embodiments, the first set of baseband circuits may be configured to send information associated with the synchronization sequence and the CSI-RS to the controller.

[OHl] In some embodiments, the first set of baseband circuits may include the cell search/measurement circuit. In some embodiments, the second set of baseband circuits may include the feedback circuit.

[0112] In some embodiments, the baseband chip may further include a controller coupled to the first set of baseband circuits and the second set of baseband circuits. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving reduced traffic mode signaling, power-gate the cell search/measurement circuit of the first set of baseband circuits, the second set of baseband circuits, the second data interconnection, and the second control interconnection during a first period. In some embodiments, the controller may be configured to, in response to the first set of baseband circuits receiving a synchronization sequence, activate from the cell search/measurement circuit during a second period. In some embodiments, the controller may be configured to, in response to the cell search/measurement circuit receiving a CSI-RS, activate from the second data interconnection, the second control interconnection, and the feedback circuit during a second period subsequent to the first period.

[0113] In some embodiment, each of the first data interconnection, the first control interconnection, the second data interconnection, and the second control interconnection may be associated with at least one of an NoC interconnection, a bus interconnection, a point-to-point interconnection, an AIB interconnection, a UIB interconnection, a HyperTransport interconnection, a LIPINCON interconnection, a CCIX, a Gen-Z interconnection, an OpenCAPI interconnection, an optical interconnection, or an electrical interconnection.

[0114] According to still another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include performing, by a first set of baseband circuits, a first set of baseband operations. The method may include performing, by a second set of baseband circuits, a second set of baseband operations different from the first set of baseband operations. The method may include enabling, by a first data interconnection coupled to the first set of baseband circuits, a transfer of first data information within the first set of baseband circuits. The method may include enabling, by a first control interconnection coupled to the first set of baseband circuits, a transfer of first control information within the first set of baseband circuits. The method may include enabling, by a second data interconnection coupled to the second set of baseband circuits, a transfer of second data information within the second set of baseband circuits. The second data interconnection may be separate from the first data interconnection. The method may include enabling, by a second control interconnection coupled to the second set of baseband circuits, a transfer of second control information within the second set of baseband circuits. The second control interconnection may be separate from the first control interconnection. [0115] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0116] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0117] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0118] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0119] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.