Field of the invention

The invention relates to a power conditioning apparatus and a method for conditioning electrical power supplied by said power conditioning apparatus to a connected electrical load .

Background of the invention

Electrical loads connected to a power supply system require in many use cases conditioning of the supplied electrical power, in particular to protect the connected electrical loads . Loads connected to the power supply system require overload and overcurrent protection . Further, electrical loads connected to a power supply system need to be turned on or turned of f . As a consequence , electrical power supplied to the connected load has to be conditioned during a turn-on phase or a turn-of f phase of the electrical load . A connected electrical load may comprise di f ferent operation modes requiring adaption or conditioning of the supplied electrical power .

Conventional electrical protection devices can employ current sensors to measure an electrical current flowing to the connected load to detect a critical situation and to trigger automatically an electronic or electromechanical switch in case that such a critical situation is detected . A current measurement element such as a Hall sensor may measure the electrical current and supply corresponding measurement values to an integrated controller which can switch of f matching components of the protection device in case that the measured cur- rent values exceed a predetermined threshold value . Some conventional protection devices use semiconductor switches such as MOSFETs to protect connected loads against overcurrents or against overload .

However, these conventional electrical protection devices require the provision of sensor elements in the current supply path to measure the electrical current flowing to the connected electrical load . These sensor elements might lead to additional energy losses and limit the possibility of miniaturi zation of the respective electrical protection device .

Summary of the invention

Accordingly, it is an obj ect of the present invention to provide a power conditioning apparatus and a corresponding method which allow to condition the electrical power supplied to the connected load without the provision of sensor elements in the power supply path .

This obj ect is achieved according to a first aspect of the present invention by a power conditioning apparatus comprising the features of claim 1 .

The invention provides according to a first aspect a power conditioning apparatus for conditioning an electrical power supplied by said power conditioning apparatus to a connected electrical load, said power conditioning apparatus comprising : an input terminal , an output terminal , a semiconductor switching stage through which the connected load receives a load current and a current mirror evaluation circuit . The output terminal is configured to be connected to the load . The semiconductor switching stage comprises two power switches . The two power switches are arranged in series between the input terminal and the output terminal . The two power switches are arranged such that the power switches have opposite orientations . Each power switch comprises a current mirror circuit . The current mirror circuits are adapted to mirror the load current through the related power switch . Accordingly, each current mirror circuit generates a mirror current , respectively . The current mirror evaluation circuit is adapted to evaluate the generated mirror currents . In particular, the semiconductor switching stage is controlled in response to the evaluated mirror currents to condition the electrical power supplied to the connected load .

The expression " in opposite directions" may be understood such that a drain or emitter of a first power switch is coupled with the input terminal , and a drain or emitter of a second power switch is coupled with the output terminal . The sources or collectors of the two power switches may be connected to ( or : with) each other . The body diodes of the power switches are oriented in opposite directions . In this way, a reliable electrical isolation can be achieved by the power switches , regardless of the polarity of the electrical voltage at the input terminal .

In a possible embodiment , the conditioning of the electrical power comprises an adj ustment of an amplitude and/or time period of an electrical power, in particular an AC power supply phase . Additionally or alternatively, the conditioning may comprise a shaping of a signal form of the electrical power . In a possible embodiment , the input terminal of the power conditioning apparatus is configured to receive electrical power from a power supply system . The power supply system may comprise a power supply grid, in particular, a public power supply grid or a power distribution apparatus . The power conditioning apparatus may be configured to receive AC power at the input terminal .

In a possible embodiment , each current mirror circuit is integrated into its respective power switch . Accordingly, each power switch and the related current mirror circuit may be provided as a single component .

In a possible embodiment , the power switches each comprise a current sensing transistor stage . The current sensing transistor stage is adapted to mirror the load current flowing through said current sensing transistor stage to generate the mirror current , in particular with a predefined current mirror ratio .

In a possible embodiment , at least one power switch comprises an embedded thermal sensor . The embedded thermal sensor may be adapted to generate a temperature sensor signal . The temperature sensor signal may be supplied to a temperature evaluation circuit of said power conditioning apparatus . In this way, thermal problems can be identi fied in time and appropriate measures can be initiated .

In a possible embodiment , the current mirror evaluation circuit comprises a first sensor component adapted to generate an induction voltage corresponding to a current rise speed, dl /dt , of the mirror current generated by the current mirror circuit . In this way, variations in the load current , in particular a fast rise of the load current can be identi fied .

In a possible embodiment , the first sensor component of the current mirror evaluation circuit comprises a measurement coil . The measurement coil may be adapted to generate the induction voltage corresponding to the current rise speed, dl /dt , of the mirror current generated by said current mirror circuit . In this way, variations of the current over time can be easily identi fied .

In a possible embodiment , the current mirror evaluation circuit comprises a second sensor component . The second sensor component may be adapted to generate a voltage corresponding to an amplitude of the mirror current generated by the current mirror circuit .

In a possible embodiment , the second sensor component of said current mirror evaluation circuit comprises a measurement resistor . The measurement resistor may be adapted to generate the voltage corresponding to the amplitude of the mirror current generated by said current mirror circuit .

In a possible embodiment , the power conditioning apparatus comprises a capacitor and a current source . The capacitor may be connected to a driver circuit of the power conditioning apparatus . The current source may be configured to provide a charging current to charge the capacitor . In particular, i f a current rise speed, dl /dt , of the mirror current and/or i f an amplitude of the mirror current exceeds a predefined level , the current source may be triggered to provide a charging current to charge the capacitor . In a possible embodiment the power conditioning apparatus comprises a comparator . The comparator may be configured to compare a voltage of the charged capacitor with a predefined threshold voltage . In particular, i f the voltage of the charged capacitor exceeds the threshold voltage , a switch-of f of at least one of the power switches of the semiconductor switching stage may be triggered by said comparator .

In a possible embodiment , the power conditioning apparatus comprises a capacitor and the recti fier stage . The capacitor may be connected to the driver circuit of the power conditioning apparatus . The recti fier stage may be configured to forward a biased voltage over the semiconductor switching stage to the capacitor .

In a possible embodiment , i f a current rise speed, dl /dt , of the mirror current , IM, and/or i f an amplitude of the mirror current , IM, exceed a predefined level , the recti fier stage of the power conditioning apparatus is switched of f . According to this switch of f of the recti fier stage , a charging current flows into the capacitor . Accordingly, the capacitor is charged .

In a still further possible embodiment of the power conditioning apparatus according to the first aspect of the present invention, the power switch of the semiconductor switching stage comprises a power MOSFET .

In a further possible embodiment of the power conditioning apparatus according to the first aspect of the present invention, the power switch of the semiconductor switching stage comprises an IGBT . According to a second aspect , an electric system is provided . The electric system comprises at least one power conditioning apparatus according to the first aspect , and a load . The load may be connected to the output terminal or terminals of the at least one power conditioning apparatus .

I f the electric system comprises multiple power conditioning apparatuses , each input terminal of a power conditioning apparatus may be configured to receive an input power from a phase of a power source . Each output terminal of the at least one power conditioning apparatus may be configured to provide output power to a phase of a load .

In a possible embodiment , the electric system is configured to be connected to an AC power source and/or an AC load . In particular, the AC power source and/or the AC load may comprise multiple phases , e . g . three phases .

In a possible embodiment , the electric system may be configured to be coupled to an electric machine . Additionally or alternatively, the electric system may be coupled to an electric heating, a semiconductor device or any other electric device .

The invention further provides according to a third aspect a method for power conditioning of electrical power supplied to an electrical load comprising the features of claim 15 .

The invention provides according to a second aspect a method for power conditioning of electrical power supplied to an ( electrical ) load, said method comprising : mirroring a load current flowing through a semiconductor switching stage to the load to generate a mirror current , the semiconductor switching stage comprising two power switches arranged in series between an input terminal and an output terminal connected to the load, the two power switching having opposite orientations , and each power switch comprising a current mirror circuit adapted to mirror the load current through the related power switch to generate a mirror current ; evaluating the generated mirror currents by a current mirror evaluation circuit and controlling the semiconductor switching stage by the current mirror evaluation circuit depending on the evaluated mirror currents to condition the electrical power supplied to the connected load .

Brief description of drawings

In the following, possible embodiments of the di f ferent aspects of the present invention are described in detail with reference to the enclosed figures .

Fig . 1 shows a block diagram of a possible exemplary embodiment of a power conditioning apparatus according to the first aspect of the present invention;

Figs . 2A, 2B show block diagrams for illustrating possible exemplary embodiments of the power conditioning apparatus according to the first aspect of the present invention; Fig . 3 shows a circuit diagram for illustrating a possible exemplary embodiment of a power conditioning apparatus according to the first aspect of the present invention;

Fig . 4 shows a circuit diagram for illustrating a possible exemplary embodiment of a current mirror evaluation circuit according to the first aspect of the present invention;

Fig . 5 shows a further circuit diagram for illustrating a possible exemplary embodiment of a current mirror evaluation circuit according to the first aspect of the present invention;

Fig . 6 shows a further circuit diagram for illustrating a possible exemplary embodiment of a current mirror evaluation circuit according to the first aspect of the present invention;

Fig . 7 shows a further circuit diagram for illustrating a possible exemplary embodiment of a current mirror evaluation circuit according to the first aspect of the present invention;

Fig . 8 shows a block diagram of a possible embodiment of a driver circuit within a power conditioning apparatus according to the first aspect of the present invention .

Figs . 9A, 9B, show signal diagrams for illustrating an operation of a power conditioning apparatus according to the first aspect of the present invention;

Fig . 10 shows a flowchart for illustrating a possible embodiment of a method for conditioning electrical power according to a further aspect of the present invention;

Fig . 11 shows a senseFET equivalent circuit of a sense MOSFET used in a possible implementation of a switching stage ;

Detailed description of embodiments

Fig . 1 illustrates schematically a possible exemplary embodiment of a power conditioning apparatus 1 according to the first aspect of the present invention . In the illustrated embodiment , the power conditioning apparatus 1 comprises an input terminal 2 and an output terminal 3 . The power conditioning apparatus 1 receives at the input terminal 2 electrical power from a power supply system such as a public power supply grid or a power distribution apparatus . For example , an alternating current (AC ) power may be provided at input terminal 2 of the power conditioning apparatus 1 . However, it may be also possible to provide direct current ( DC ) power at the input terminal 2 . At the output terminal 3 of the power conditioning apparatus 1 , an electrical load 4 is connected . For example , the electrical load 4 may be an electrical ma- chine or motor, a heating device or any other kind of electrical load .

The power conditioning apparatus 1 may be , for example , a component of an electrical system such as an automation system or the like with one or more electrical devices . In such a configuration, the electrical load for may be an electrical device such as an actor . For example , the power conditioning apparatus 1 may be included in an electrical cabinet or the like . The invention thus also provides an electrical cabinet , in particular a switching cabinet , comprising the electrical power conditioning apparatus 1 .

The electrical power conditioning apparatus 1 may be used for conditioning electrical energy of a single phase . However, it is also possible to apply the concept of the power conditioning apparatus 1 to multiple phases , for example , a three- phase power line . In particular, the power conditioning apparatus 1 may be used for conditioning AC power and/or DC power . In this context , it is to be emphasi zed that the general concept of conditioning a power according to the present invention is not limited to DC power but can be also applied to AC power .

The power conditioning apparatus 1 comprises in the illustrated embodiment of Fig . 1 a semiconductor switching stage 5 provided in the power supply path between the input terminal 2 and the output terminal 3 of the power conditioning apparatus 1 . A load current I _L flowing to the electrical load 4 connected to the output terminal 3 flows through the semiconductor switching stage 5 as shown in Fig . 1 . The power conditioning apparatus 1, in particular the semiconductor switching stage 5, comprises in the illustrated embodiment of Fig. 1 current mirror circuits 6-1, 6-2 adapted to mirror the load current I _L flowing through the semiconductor switching stage 5 to generate a mirror current I _M with a fixed transfer ratio between the load current I _L and the mirror current I _M . The transfer ratio may be in the range of 1:1000. However, depending on the use case, any other appropriate ratio, for example a higher ratio up to 1:10.000 or even up to 1:1.000.000 may be possible. In other use cases, a lower ratio up to 1:100 or 1:10 may be possible.

The power conditioning apparatus 1 further comprises a current mirror evaluation circuit 7 connected to the semiconductor switching stage 5, in particular the current mirror circuits 6-1, 6-2. The current mirror evaluation circuit 7 is adapted to evaluate in real time the generated mirror current I _M - The semiconductor switching stage 5 is controlled by the current mirror evaluation circuit 7 in response to the evaluated mirror current I _M to condition the electrical power supplied to the connected load 4.

The conditioning of the electrical power by the hardwired power conditioning apparatus 1 can involve the adjustment of the amplitude or time period of the electrical power, in particular an AC power supply phase. The conditioning can also comprise a shaping of the signal form of the electrical power. Because of the hardwired realization the reaction of the power conditioning apparatus 1 to a changing power supply condition is fast. In the illustrated embodiment of Fig. 1, the power conditioning apparatus 1 comprises a single power supply path to provide electrical power to the connected electrical load 4. In other embodiments, the power condition- ing apparatus 1 may comprise several power supply paths with a corresponding number of associated semiconductor switching stages 5 to provide electrical power by means of di f ferent electrical phases to the connected electrical load 4 . The connected electrical load 4 may comprise a resistive load, a capacitive load or an inductive load such as an electrical motor .

The semiconductor switching stage 5 of the power conditioning apparatus 1 can comprise in a possible embodiment at least one power switch having a gate controlled by a control signal CTRL provided by a driver circuit 9 connected directly or indirectly to the current mirror evaluation circuit 7 in response to the evaluated mirror current I _M . In a preferred embodiment , the power switches 8- 1 , 8-2 of the semiconductor switching stage 5 can comprise integrated current mirror circuits 6- 1 , 6-2 . In a possible embodiment , the power switches of the semiconductor switching stage 5 can comprise at least one current sensing power MOSFET 8 adapted to mirror the load current I _L flowing through the respective current sensing power MOSFET to generate the mirror current I _M with a predefined current mirror ratio . In a possible implementation, the current sensing power MOSFET 8 of the semiconductor switching stage 5 can comprise an embedded thermal sensor adapted to generate a temperature sensor signal supplied to a temperature evaluation circuit 11 of the power conditioning apparatus 1 .

Even though in the following description power switches 8- 1 and 8-2 are described by examples of MOSFET , it should be noted that any other appropriate semiconductor switching devices are possible , too . In particular, power switches 8- 1 and 8-2 may be also reali zed by bipolar transistors , such as bipolar transistors with an insulated gate terminal ( IGBT ) .

The current mirror evaluation circuit 7 of the power conditioning apparatus 1 can comprise in a possible embodiment a sensor component such as a coil adapted to generate an induction voltage corresponding to a current rise speed dl /dt of the mirror current I _M provided by the current mirror circuits 6- 1 , 6-2 . The current mirror evaluation circuit 7 can comprise in a further embodiment a sensor component such as a resistor adapted to generate a voltage corresponding to an amplitude of the mirror current I _M generated by the current mirror circuits 6- 1 , 6-2 . The sensor component of the current mirror evaluation circuit 7 can comprise in a possible implementation a measurement coil having a defined inductance adapted to generate an induction voltage corresponding to the current rise speed dl /dt of the mirror current I _M generated by the current mirror circuits 6- 1 , 6-2 . In a possible embodiment , the sensor component of the current mirror evaluation circuit 7 can also comprise a measurement resistor having a defined resistance adapted to generate a voltage corresponding to the amplitude of the mirror current I _M generated by the current mirror circuits 6- 1 , 6-2 .

I f the current rise speed dl /dt of the mirror current I _M measured by the measurement coil or i f the amplitude of the mirror current I _M measured by the measurement resistor exceed a predefined level , a current source I-DESAT is triggered to provide a charge current to charge in a possible embodiment a capacitor 13 connected to the driver circuit 9 of the power conditioning apparatus 1 . The voltage of the charged capacitor 13 can be compared in a possible embodiment by a comparator K- l with a predefined threshold voltage . I f the voltage of the charged capacitor 13 exceeds the predefined threshold voltage , a switch-of f of the at least one power switch 8 of the semiconductor switching stage 5 can be automatically triggered by the comparator K- l . In a possible implementation, the current source I-DESAT and the comparator K- l can be integrated on a high voltage side of the driver circuit 9 as shown in Fig . 8 . In a possible implementation, the driver circuit 9 comprises the high voltage side and a low voltage side where both sides are galvanically separated from each other as also illustrated in Fig . 8 . The low voltage side of the driver circuit 9 can in a possible embodiment be connected to a local controller comprising a microcontroller 50 integrated in the power conditioning apparatus 1 as shown in Fig . 8 .

In a possible embodiment of the power conditioning apparatus 1 , the current mirror evaluation circuit 7 comprises for each power switch of the semiconductor switching stage 5 an associated pair of serially connected sensor components including a measurement coil and a measurement resistor . A Zener diode can be connected in parallel to each pair of sensor components to protect the associated power switch of the semiconductor switching stage 5 against overvoltage spikes . Further, an overvoltage protection circuit 12 can be provided . In a possible implementation, the overvoltage protection circuit 12 of the power conditioning apparatus 1 can comprise a varistor which is connected in parallel to the semiconductor switching stage 5 to provide protection of the power switches 8- 1 , 8-2 of the semiconductor switching stage 5 against overvoltage and a free-wheeling path for the load current .

In a further possible embodiment , i f the current rise speed dl /dt of the mirror current I _M measured by the measurement coil and/or if the amplitude of the mirror current I _M measured by the measurement resistor exceed a predefined level a rectifier stage 15 of the power conditioning apparatus 1 can be switched off such that a charging current provided by a current source flows into a capacitor 13 for charging the respective capacitor 13. In a possible embodiment, the power switches of the semiconductor switching stage 5 can comprise power MOSFETs. In an alternative implementation, the power switches of the semiconductor switching stage 5 can comprise IGBTs .

Fig. 2A shows a circuit diagram for illustrating a possible exemplary embodiment of the power conditioning apparatus 1 according to the first aspect of the present invention.

In the illustrated embodiment of Fig. 2A, the power conditioning apparatus 1 comprises the semiconductor switching stage 5 including two serially connected semiconductor switches 8-1, 8-2 such as MOSFETs. The two semiconductor switches 8-1, 8-2 are arranged in series between the input terminal 2 and the output terminal 3 of the power conditioning apparatus 1. Each semiconductor switch 8-1, 8-2 comprises a diode which is arranged parallel to the respective switch 8-1, 8-2. The diodes may be internal body diodes or separate, external diodes. The two transistors 8-1, 8-2 are arranged with opposite orientations. Thus, the diodes of the two transistors 8-1, 8-2 have opposite reverse directions. If the transistors are MOSFETs, a first transistor 8-1 and a second transistor 8-2 may be connected with each other at the source terminals S, as shown in figure 2A. Alternatively, bipolar transistors, e.g. IGBTs, may be connected with each other at emitter terminals. Such an arrangement makes it possible to ensure that a reliable blocking effect can always be achieved with AC or an inverse DC voltage (i.e. the voltage at output terminal 3 is higher than the voltage at input terminal 2) .

In the illustrated embodiment of Fig. 2A, the power switches 8-1, 8-2 may comprise current sensing power MOSFETs adapted to mirror the load current I _L flowing to the current sensing power MOSFETs 8-1, 8-2, respectively, to generate a mirror current I _M with a predefined current mirror ratio supplied to the current mirror evaluation circuit 7. In the embodiment illustrated in Fig. 2A, the current mirror circuits 6-1, 6-2 are implemented by the provision of current sensing power MOSFETs 8-1, 8-2 within the semiconductor switching stage 5. For example, the power switches 8-1, 8-2 may comprise a silicon carbide instrumented MOSFET such as KE12MI00H700T63 from CALY Technologies. However, any other appropriate semiconductor switch which can provide a mirror current I _M , having a predetermined ratio to the load current I _L may be used, too.

As can be seen in Fig. 2A, a drain of a first MOSFET 8-1 is electrically coupled with the input terminal 2 of the power conditioning apparatus 1, and a drain of second MOSFET 8-2 is electrically coupled with the output terminal 3 of the power conditioning apparatus 1. The source terminal of the first MOSFET 8-1 is electrically connected with the source terminal of the second MOSFET 8-2. If the transistors 8-1, 8-2 comprise a Kelvin source terminal K, the Kelvin source terminals K of the two transistors 8-1, 8-2 may be also electrically connected with each other.

The gates G of the current sensing power MOSFETs 8-1, 8-2 are controlled by a gate driver output of an isolated gate driver circuit 9 of the power conditioning apparatus 1. In the illustrated embodiment of Fig. 2A, the current sensing power MOSFETs 8- 1 , 8-2 comprise each an embedded thermal sensor 10- 1 , 10-2 adapted to generate a temperature sensor signal supplied to a temperature evaluation circuit 11 . The provision of this temperature evaluation circuit 11 is optional .

Further in the embodiment shown in Fig . 2A, the power conditioning apparatus 1 comprises an overvoltage protection circuit 12 having a varistor 12- 1 . Further, the overvoltage protection circuit 12 may comprise a capacitor 12-2 which is arranged in parallel to the varistor 12- 1 . The overvoltage protection circuit 12 is connected in parallel to the semiconductor switching stage 5 to provide protection of the power switches 8- 1 , 8-2 of the semiconductor switching stage 5 against overvoltage .

The current mirror evaluation circuit 7 illustrated in

Fig . 2A can comprise sensor components connected to the current sensing power MOSFETs 8- 1 , 8-2 to receive the mirrored load current I _M - The current sensing components are described in more detail below . In a possible embodiment , the current mirror evaluation circuit 7 of the power conditioning apparatus 1 as shown in Fig . 2A comprises a sensor component adapted to generate an induction voltage corresponding to a current rise speed dl /dt of the mirror current I _M received from the current sensing power MOSFETs 8- 1 , 8-2 . The current mirror evaluation circuit 7 can further comprise a sensor component adapted to generate a voltage corresponding to the amplitude of the mirrored current I _M provided by the current sensing power MOSFETs 8- 1 , 8-2 . In a possible implementation, the sensor component integrated in the current mirror evaluation circuit 7 can comprise a measurement coil adapted to generate an induction voltage corresponding to the current rise speed dl /dt of the mirror current I _M provided by the current sensing power MOSFETs 8- 1 , 8-2 . Further, the sensor component of the current mirror evaluation circuit 7 of the power conditioning apparatus 1 illustrated in Fig . 2A can comprise a measurement resistor adapted to generate a voltage corresponding to the amplitude of the mirror current I _M received from the current sensing power MOSFETs 8- 1 , 8-2 . I f the current rise speed dl /dt of the mirror current I _M measured by the measurement coil of the current mirror evaluation circuit 7 and/or i f the amplitude of the mirror current I _M measured by the measurement resistor of the current mirror evaluation circuit 7 exceed a predefined level , a current source is triggered to provide a charging current to charge a capacitor 13 connected to the driver circuit 9 of the power conditioning apparatus 1 as shown in Fig . 2A. The voltage of the charged capacitor 13 can be compared by a comparator with a predefined threshold voltage . I f the voltage of the capacitor 13 exceeds the threshold voltage , a switch-of f of the at least one MOSFET 8- 1 , 8-2 of the semiconductor switching stage 5 is triggered by the comparator . In a preferred embodiment , the current source used for charging the capacitor 13 and the comparator used for comparing the voltage at the capacitor 13 with a threshold voltage are integrated on a high voltage side of the driver circuit 9 as also illustrated in Fig . 8 . In the illustrated embodiment of Fig . 2A, the driver circuit 9 receives its power supply from a bipolar floating high side supply circuit 14 .

In the illustrated embodiment of Fig . 2A, the power conditioning apparatus 1 comprises a pair of current sensing power MOSFETs 8- 1 , 8-2 within the semiconductor switching stage 5 . The current sensing power MOSFETs 8- 1 , 8-2 can comprise transistor cells in parallel internally . Fig . 11 illustrates the equivalent circuit of a current sensing power MOSFET 8- 1 , 8-2 as used in the embodiment of Fig . 2A. The elements within the power MOSFETs 8- 1 , 8-2 can be identical and the drain current can be shared equally between them . The more transistor cells are provided in parallel for a given chip area, the lower the on-resistance of the current sensing power MOSFET 8- 1 , 8-2 becomes . The current sensing power MOSFET 8- 1 , 8-2 can each be thought of as two transistors connected in parallel with a common gate and common drain but with separate sources as illustrated in Fig . 11 . When the devices are turned on, the load current I _L can be shared in ratio of their on-resistances . The ratio of the electrical current flowing through the main FET and the current flowing through the sense FET forms the sense ratio of the current sensing power MOSFET 8 . This sense ratio is defined as the condition where the source and sense terminals are held at the same electrical potential . An additional ( optional ) Kelvin connection to the source metalli zation of the current sensing power MOSFET 8 enables an accurate determination of the source potential . The current sensing power MOSFETs 8- 1 , 8-2 provide an ef fective way of measuring a load current I _L flowing to the electrical load 4 . The separation is based on a matched devices principle . The on-resistance of individual source cells in the power MOSFET 8- 1 , 8-2 tends to be well-matched . Therefore , i f several out of several thousand cells are connected to a separate sense pin, a ratio between the sense section on-resistance and the power section on-resistance is developed . When the sense FET device is turned on, an electrical current flow splits inversely with respect to the two resistances and a ratio between the electrical sense current and the source current is established . A separate source connection provides the mirroring . In a possible embodiment , the current sensing power MOSFET 8 can be designed such and the ratio between the mirror cells and source cells is on the order of 1:1000. However, any other appropriate ratio is possible as well. For example, the ratio may be a predetermined ratio in a range between 10 and 10.000 or even 1.000.000. In particular, the predetermined range may be given by the configuration of the current mirror properties of the power switches 8-1, 8-2 used in the switching stage 5.

As illustrated in Fig. 11, the current sensing power MOSFET 8 can be equated with two parallel FETs with common gate and drain connections but with separate source leads. The relative size of the two separate devices equated within the current sensing power MOSFET determines how the electrical current is split between the source and mirror terminals of the current sensing power MOSFET. The ratio of source current to mirror current is specified by MR, i.e. the current mirror ratio. The mirror ratio MR is defined for conditions where both source and mirror terminals are held at the same potential. Since the current mirror ratio MR can be, for example, in the order of e.g. 1000:1, the load current I _L flowing to the electrical load 4 is approximately equal to the source current and the current mirror ratio MR also indicates the ratio of load current I _L to the sense current. The mirror current I _M provided by each of the current sensing power MOSFETs 8-1, 8-2 is supplied to the current mirror evaluation circuit 7 as can be seen in Fig. 2A.

Fig. 2B illustrates a further exemplary embodiment of a power conditioning apparatus 1 comprising an additional rectifier stage 15. A first input of the rectifier stage 15 may be electrically coupled via a first diode 20 with the connection between the first power switch 8-1 and the output terminal 3. A second input of the rectifier stage 15 may be electrically coupled via a second diode 21 with the connection between the second power switch 8-2 and the input terminal 2 . An output terminal of the recti fier stage 15 is electrically connected with a terminal of the DESAT filtering capacitor 13 . The other terminal of the capacitor 13 is connected with the ground GND2 . recti fier stage 15 may further comprise a terminal for receiving a disconnect command form current mirror evaluation circuit 7 . Still a further terminal of the recti fier stage 15 may receive the gate driver signal from driver circuit 9 .

I f the current rise speed dl /dt of the mirror current I _M measured by a measurement coil , in particular a measurement coil of the current mirror evaluation circuit 7 and/or i f the amplitude of the mirror current I _M measured by a measurement resistor, in particular a measurement resistor of the current mirror evaluation circuit 7 exceed a predefined level , the recti fier stage 15 of the power conditioning apparatus 1 can be switched of f such that a charging current provided by the current source integrated in the driver circuit 9 does flow into the capacitor 13 for charging the respective capacitor 13 . For this purpose of switching of f the recti fier stage 15 , circuit 7 may output a disconnect command to recti fier stage 15 . In response to this disconnect command, recti fier stage 15 may be switched of f . Accordingly, DESAT filtering capacitor 13 may be charged by the output provided from the DESAT pin of driver circuit 9 .

The remaining components of the power conditioning apparatus 1 illustrated in Fig . 2B correspond to the components illustrated in the embodiment of Fig . 2A. In a possible embodiment , i f the MOSFET forward voltage becomes too big, then also the capacitor 13 is allowed to be charged by the current source . Consequently, both high dynamic and slow dynamic events can be evaluated to protect the MOSFETs 8- 1 , 8-2 from excess electrical stress . The maximum induced voltage can be limited e . g . by means of Zener Diodes in parallel to the inductive components to ensure that no power MOSFET 8- 1 , 8-2 is accidentally turned of f or is operated in a linear mode . Di fferent coils can be located inside the current mirror evaluation circuit 7 . I f the induced voltage on the coils becomes too high, the recti fier block 15 can be switched of f automatically to allow the current source integrated in the gate driver circuit 9 to charge the capacitor 13 .

The measurement coils are not provided within the main power supply path but within the separate current mirror evaluation circuit 7 or outside the current mirror evaluation circuit 7 parallel to the respective connection terminals of the evaluation circuit 7 , thus reducing power dissipation . The mirrored current I _M provided by the current sensing power MOSFETs 8-i is a fixed fraction of the main current , i . e . the load current I _L flowing to the electrical load 4 connected to the output terminal 3 of the power conditioning apparatus 1 .

Fig . 3 shows a further exemplary implementation of a power conditioning apparatus 1 according to the first aspect of the present invention . Fig . 3 shows a possible implementation of the current mirror evaluation circuit 7 having two sensor components 16 , 17 connected serially between the mirror terminals of the power sensing MOSFETs 8- 1 , 8-2 as shown in Fig . 3 . Each sensor component 16 , 17 may be a measurement coil , a measurement resistor, or a combination of a measurement coil and a measurement resistor in series . Preferably, same values may be used for the elements of the first sensor component 16 and the second sensor component 17 . In the illustrated embodiment of Fig . 3 , Zener diodes 18 , 19 are connected in parallel to each pair of sensor components 16 , 17 to protect the associated power switch of the semiconductor switching stage 5 against overvoltage spikes . The measurement coils of the sensor components 16 , 17 can be adapted to measure a current rise speed dl /dt of the mirrored current I _M which is a fixed fraction of the main electrical current flowing to the electrical load 4 . I f the induced voltage of the measurement coils 16 , 17 becomes too big, the recti fier stage 15 is automatically turned of f allowing the current source integrated in the driver circuit 9 to charge the filtering capacitor 13 illustrated in Fig . 13 . The comparator integrated in the driver circuit 9 compares the voltage along the capacitor 13 with a threshold voltage . I f the voltage at the capacitor 13 exceeds the threshold voltage , the comparator integrated in the driver circuit 9 does automatically trigger a switch of f of the power switches 8- 1 , 8-2 within the semiconductor switching stage 5 .

In the example according to Fig . 3 , a diode 40 is arranged between the terminal of the first power switch 8- 1 providing the mirror current and a first node . Accordingly, a further diode 41 is arranged between the terminal of the second power switch 8-2 providing the mirror current and the first node . A resistor is arranged between the first node and the ground . Further, a transistor 32 is arranged between the first node and a control terminal (basis ) of further transistor 32a . The control terminal (basis ) of transi stor 32 may be connected via a diode and a resistor with a supply voltage . A first terminal of the further transi stor 32a may be connected with the OUT pin of the gate driver 9 and the other terminal of the further transistor 32 a may be connected with the disconnect command input of the recti fier stage 15 . In the example illustrated in Fig . 3 , the recti fier stage 15 may comprise four transistors 22 , 23 , 30 , 31 and multiple resistors 24-29 . A first resistor 25 is arranged between the ground and a first node of the rectifier stage 15 . A second resistor 28 is arranged between the ground and a second node of the recti fier stage 15 . A third resistor 24 is arranged between a terminal for receiving the disconnect command input and the first node , and a fourth resistor 27 may be connected between a terminal for receiving the disconnect command input and the second node . A fi fth resistor 26 is arranged between the first node and a third node of the recti fier stage 15 , and a sixth resistor 29 is arranged between the second node and a fourth node of the recti fier stage 15 . Further, the terminal of the recti fier stage 15 which is connected to the node between the first power switch 8- 1 and the input terminal 2 is connected with the fourth node , and the terminal of the recti fier stage 15 which is connected to the node between the second power switch 8-2 and the output terminal 3 is connected with the third node . The first terminal of transistor 30 is connected via a resistor with the fourth node , and the other terminal of this resistor 30 is connected with the output terminal of recti fier stage 15 . Accordingly, the first terminal of further transi stor 31 is connected via a further resistor with the third node , and the other terminal of thi s further resistor 31 is connected with the output terminal of recti fier stage 15 . Still a further transistor 22 is arranged between a third node and the control terminal of transistor 30 , wherein the control terminal of this still further transistor is connected with the first node . Accordingly, another transistor 23 is connected between the fourth node and the control terminal of transistor 31 , wherein the control terminal of this transistor 23 is connected with the second node . As can be further seen in Fig . 3 , a resistor may be arranged between the control terminal of transistors 30, 31 and the output terminal of rectifier stage 15, respectively. For further details, reference is made to the of rectifier stage 15 as illustrated in Fig. 3.

The output terminal of rectifier 15 is connected with a terminal of DESAT filtering capacitor 13. This terminal of capacitor 30 may be also connected to the DESAT pin of driver circuit 9. The other terminal of capacitor 13 is connected with the ground. A diode D may be arranged in parallel to capacitor 13.

As can be seen in Fig. 3 illustrating the rectifier stage 15 within the power conditioning apparatus 1 shown in Fig.2B, the rectifier stage 15 is connected via a diode 20 to the input terminal 2 and via a diode 21 to the output terminal 3 of the power conditioning apparatus 1. These diodes 20,21 are decoupling diodes. If the electrical current flows from the input terminal 2 towards the output terminal 3 the transistor

22 of the rectifier stage 15 is turned on and the transistor

23 is switched off. In contrast, if the current flows in the opposite direction from the output terminal 3 to the input terminal 2 the transistor 23 of the rectifier stage 15 is turned on whereas the transistor 22 of the rectifier stage 15 is switched off. Assuming a positive polarity on the mains terminal 2 and a current flow from terminal 2 to the load terminal 3 both power MOSFETs 8-1, 8-2 are turned on by a sufficient high gate-to-source voltage on the out terminal 3 to ground GND. Due to current flow, the mains terminal 3 potential with respect to ground GND is negative which turns on diode 21 and also transistor 22 is biased by resistors 24, 25, 26 in such a way that it is turned on. As a consequence, transistor 30 does connect diode 20 to the DESAT pin of the driver circuit 9. The control output of the driver circuit 9 controls the gates of the power MOSFETs 8-1, 8-2 within the switching stage 5. If the voltage potential is high (e.g. 15 Volt) , MOSFETs 8-1, 8-2 are switched on. The transistor 23 of the rectifier stage 15 is biased by means of resistors 27, 28, 29 as illustrated in Fig. 3. Accordingly, for negative polarity, the mains terminal of the power conditioning apparatus 1 is working in a similar manner as for positive polarity, but now transistor 31 connects diode 21 to the DESAT input of the driver circuit 9.

Fig. 4 shows a further possible implementation of a current mirror evaluation circuit 7 within a power conditioning apparatus 1 according to the present invention.

Fig. 4 illustrates a possible implementation of the current mirror evaluation circuit 7 as also used in the embodiment of Fig. 2A, i.e. an embodiment of the power conditioning apparatus 1 without the provision of a rectifier stage 15. The mirror current evaluation circuit 7 of Fig.4 comprises resistors 33, 34 adapted to measure an amplitude of the mirrored current .

As can be seen in Fig. 4, a first sensing component, e.g. a first measurement resistor 33 may be arranged between the terminal of the first power switch 8-1 which provides the measurement current I _M and a ground. Accordingly, a second sensing component, e.g. a second measurement resistor 34 may be arranged between the terminal of the second power switch 8-2 which provides the measurement current I _M and the ground. A first Zener diode 37 is arranged parallel to the first sensing component, and a second Zener diode 38 is arranged parallel to the second sensing component. The first diode 40 is arranged between the terminal of the first power switch 8- 1 which provides the measurement current I _M and the first node , and a second diode 41 is arranged between the terminal of the second power switch 8-2 which provides the measurement current I _M and the first node . This first node is further connected with the first terminal of transistor 32 , wherein the first terminal of the transistor 32 is connected via a resistor to the ground . The control terminal of this transistor 32 is also connected via a resistor to the ground, and via a further Zener diode ZD and to the OUT pin of the gate driver 9 . The further terminal of transistor 32 is connected via a resistor to the DESAT filtering capacitor 13 .

Fig . 5 shows a further exemplary embodiment of a current mirror evaluation circuit 7 within an embodiment of the power conditioning apparatus 1 as illustrated in Fig . 2A. The illustrated implementation of Fig . 5 corresponds to the configuration as illustrated in figure 4 , wherein the sensing components of the current mirror evaluation circuit 7 comprise measurement coils 35 , 36 adapted to measure a change dl /dt of the mirrored current .

The illustrated embodiment of Fig . 6 , di f fers from the previous configurations according to Figs . 4 and 5 in that sensing components of the current mirror evaluation circuit 7 of the power conditioning apparatus 1 as shown in Fig . 2A comprises for each power switch 8- 1 , 8-2 of the semiconductor switching stage 5 an associated pair of serially connected sensor components including a measurement coil 35 , 36 and a measurement resistor 33 , 34 . In the illustrated embodiment of Fig . 6 , a Zener diode 37 , 38 is connected parallel to each pair of sensor components to protect the associated power switch of the semiconductor switching stage 5 against overvoltage spikes . In the embodiment of Fig . 6 , the evaluation circuit 7 evaluates a superposition of the current rise speed dl /dt of the mirror current I _M measured by the measurement coil and of the amplitude of the mirror current I _M measured by the measurement resistor . I f the current rise speed dl /dt of the mirror current I _M measured by the measurement coil and/or i f the amplitude of the mirror current I _M measured by the measurement resistor exceeds a predefined level , a charging current provided by the current source integrated in the driver circuit 9 flows into the capacitor 13 for charging the capacitor 13 since the transistor 32 of the current mirror evaluation circuit 7 is cut of f .

Fig . 6 illustrates an implementation of the current mirror evaluation circuit 7 within an embodiment of the power conditioning apparatus 1 according to the first aspect of the present invention as illustrated in Fig . 2A. During normal operation, the Zener diode 37 is reversed biased for load current I _L flowing from the input terminal 2 to the output terminal 3 of the power conditioning apparatus 1 . Diodes 40 , 41 are reverse biased . The transistor 32 is turned on and the current source inside the gate driver circuit 9 is shunted by transistor 32 . I f the current rise speed dl /dt and/or the current amplitude of the mirrored current I _M exceeds a predefined level , diodes 40 , 41 become forward biased and the emitter voltage of transistor 32 is raised until the electrical current cuts of f . As a consequence , the filtering capacitor 13 is charged by the current source of the driver circuit 9 .

Fig . 7 illustrates a further possible exemplary embodiment of a current mirror evaluation circuit 7 within an embodiment of the power conditioning apparatus 1 according to the first aspect of the present invention as illustrated in Fig . 2A. In the illustrated embodiment , the current mirror evaluation circuit 7 comprises a single sensing component such as an inductor or coil 42 connected in series with a measurement resistor 43 between the terminals 6- 1 , 6-2 of the mirror circuits 6- 1 , 6-2 of the semiconductor switching stage 5 . Similar to the configurations according to Fig . 4 or 5 , the sensing component may also comprise only a measurement inductor 42 or only a measurement resistor 43 . The evaluation of the mirror current I _M is based on the use of operational ampli fiers within the current mirror evaluation circuit 7 . The current mirror evaluation circuit 7 comprises in the illustrated embodiment of Fig . 7 a first operation ampli fier 44 and a second operation ampli fier 45 .

The first (positive ) input terminal of the first operation ampli fier 44 may be connected to the terminal of the mirror circuit 6-2 . A second (negative ) input terminal of the first operation of the operational ampli fier 44 may be connected via a resistor to the terminal of current mirror circuit 6- 1 of the first power switch 8- 1 . The output terminal of the first operation ampli fier 44 may be connected via a first diode directly to the first input terminal of the first operation ampli fier 44 .

Further, the output terminal of the first operation ampli fier 44 may be connected via serial connection of a second diode and a resistor to the second input terminal of the first operation ampli fier 44 . A node between this transistor and a second diode is connected via a further resistor to a second (negative ) input terminal of the second operation ampli fier 45 . This second input terminal is further connected via a resistor to the terminal of current mirror circuit 6- 1 of the first power switch 8- 1 , and via still a further resistor to the output terminal of the second operation amplifier 45. The first (positive) input terminal of the second operation amplifier 45 is connected with the terminal of current mirror circuit 6-2 of the second power switch 8-2. The output terminal of the second operation amplifier 45 may be connected to the node between transistor 32 and the resistor as described above in connection with the previous examples.

The usage of the operational amplifiers 44, 45 allows a signal amplification. Both operational amplifiers 44, 45 form a measurement rectifier. In a possible embodiment of the power conditioning apparatus 1 the different implementations of the current mirror evaluation circuit 7 as illustrated in Figs.4,5, 6,7 can be exchanged as a module for different use cases, e.g. use cases where only the amplitude of the load current I _L is monitored (embodiment of Fig.4) , where only the change of the amplitude is monitored (Fig.5) or where both the absolute amplitude I and the change of the amplitude dl/dt of the load current I _L is monitored (Fig.6) .

Fig.8 illustrates a possible embodiment of a driver circuit 9 within a power conditioning apparatus 1. The driver circuit comprises a low voltage side connected to a microcontroller 50 of the power condition apparatus 1 and comprises high voltage side connected to the gates of the power semiconductors 8-1, 8-2 provided in the main power supply path adapted to condition a flow of the electrical load current I _L to the load 4.

ISO-1 block in Fig. 8 is a galvanic isolation unit for signals from the low voltage side of the driver circuit 9 towards the high voltage side of the driver circuit 9. The ISO- 1 block can be implemented by photo-couplers or small trans- formers . An on/of f command for the gates of the MOSFETs given by the microcontroller 50 is shi fted at the ISO- 1 block from the low voltage side to the high voltage side of the driver circuit 9 .

ISO-2 block in Fig . 8 is a galvanic isolation unit for signals from the high voltage side of the driver circuit 9 towards the low voltage side of the driver circuit 9 . It can also be reali zed by photo-couplers or trans formers . A fault signal FLT can be used to inform the microcontroller 50 about an error occurring on the high voltage side of the driver circuit 9 .

The driver circuit 9 shown in Fig . 8 comprises at its high voltage side a gate driver DR- 1 which is disabled by a comparator K- l i f the voltage at capacitor 13 connected to the DESAT pin at the high voltage side of the driver circuit 9 exceeds a predefined threshold voltage UTH . The driver circuit 9 provides a low impedance/ high peak current output for gate control of the MOSFETs 8- 1 , 8-2 .

The driver circuit 9 provides a power semiconductor forward voltage drop supervision . I f the power semiconductor, in particular a MOSFET , is turned on by setting a high level to the OUT pin of the driver circuit 9 a low current DC source I- DESAT being integrated in the driver circuit 9 on the high voltage side and being connected to drain-source terminals of the associated power semiconductors 8 is also turned on by a current source enable signal as illustrated in Fig . 8 . The voltage level at the DESAT pin of the driver circuit 9 which does correspond to the drain voltage level of the activated power semiconductor 8 is monitored by the comparator K- l and compared with an adj ustable threshold voltage UTH . Under nor- mal lead condition the drain source voltage of the activated power transistor 8 is well below the threshold voltage UTH and the current source I-DESAT is shorted to HS-GND (high voltage side ground potential ) by the associated power semiconductor 8 . I f the load current increases the voltage drop of the power semiconductor 8 increases accordingly until the comparator K- l gets activated and consequently disables the gate driver DR- 1 . This disabling is reali zed without invoking low voltage side control and typically the gate remains latched of . The disabling of the power semiconductor 8 is performed in a loop on the high voltage side of the driver circuit 9 without involving the microcontroller 50 and can consequently be performed very fast , e . g . in a reaction time of less than 1- 10 microseconds . The microcontroller 50 gets a status feedback from the high voltage side of the driver circuit 9 , in particular whether the power semiconductor 8 , i . e . the MOSFET 8 has been turned on/of f through the galvanic isolation unit ISO-2 of the driver circuit 9 . This information can also be displayed on a user interface 51 of the power conditioning apparatus 1 connected to the microcontroller 50 of the power conditioning apparatus 1 .

Figs . 9A, 9B, illustrate the operation of a power conditioning apparatus 1 according to the present invention .

Fig . 9A illustrated a normal switching operation of the power conditioning apparatus 1 with a load current I _L flowing thought the power supply path of the power conditioning apparatus 1 to a connected load 4 .

At time tO the gates of the MOSFETs 8- 1 , 8-2 are turned on by the gate drive output of the driver circuit 9 and the electrical load current starts to flow to the connected load 4 . At time tl the load current I _L and the mirror current I _M reach their full amplitude as shown in the first and second diagram of Fig . 9A.

At time t2 the voltage V13 at the capacitor 13 reaches its maximum .

At time t3 the gates of the MOSFETs 8- 1 , 8-2 are turned of f and the load current I _L starts to decrease .

At time t4 the load current I _L has been decreased to zero .

At time t5 the capacitor 13 is completely discharged and its voltage V13 is zero .

Fig . 9B illustrates the operation of a power conditioning apparatus 1 in case of an unforeseen event where the load current I _L does increase signi ficantly .

At time tO the gates of the MOSFETs 8- 1 , 8-2 are turned on by the gate drive output of the driver circuit 9 and the electrical load current I _L starts to flow to the connected load 4 .

At time tl the load current I _L reaches its full rated amplitude and the mirror current I _M does also reach its normal amplitude .

At time t2 the voltage V13 of the capacitor 13 does reach its steady state amplitude . At time t3 load current I _L and the MOSFET forward voltage starts to increase rapidly due to an event such as a short circuit or other failure during operation of the connected load 4 .

At time t4 the turn-of f condition for transistor 32 of the current mirror evaluation circuit 7 is reached and the capacitor 13 can be charged further leading to an increase of its voltage V13 as illustrated in the third diagram of Fig . 9B .

At time t5 the voltage V13 of capacitor 13 reaches the threshold voltage UTH of the comparator K- l triggering a switch of f of the MOSFETs 8- 1 , 8-2 by the driver circuit 9 .

At time t 6 the amplitude of the load current IL has decreased to zero .

At time t7 the capacitor 13 has been fully discharged and its voltages V13 becomes zero .

The reaction time period between time t3 and time t5 can in a possible embodiment be in a range between 1 microsecond and 10 microseconds . The reaction time period for reaction to the event occurring a time t3 depends inter alia on the capacity C of the capacitor 13 and the current strength of the current source integrated in the driver circuit 9 . In a possible embodiment the capacity C of the capacitor 13 can be adj usted depending on the use case . The capacity C may comprise several nF, e . g . , between 1 and 10 nF .

Fig . 10 illustrates a flowchart of a possible exemplary embodiment of a method for power conditioning of electrical power supplied to an ( electrical ) load 4 according to the third aspect of the present invention .

The method may be applied to a power condition apparatus 1 as described above . Thus , the following method may comprise any appropriate method steps to perform an operation as already described above in connection with the power condition apparatus 1 . Further, the above-described power condition apparatus 1 may comprise any appropriate element , unit or device in order to perform the method as described in the following .

In the illustrated embodiment , the method comprises three main steps .

In a first step S I , a load current I _L flowing through a semiconductor switching stage 5 to the load 4 is mirrored to generate a mirror current I _M . For this purpose , the semiconductor switching stage 5 may comprise two power switches 8- 1 , 8- 2 arranged in series between an input terminal 2 and an output terminal 3 connected to the load 4 . The two power switches 8- 1 , 8-2 have opposite orientations . Each power switch 8- 1 , 8-2 comprises a current mirror circuit 6- 1 , 6-2 . The current mirror circuits 6- 1 , 6-2 are adapted to mirror the load current , I _L , through the related power switch 8- 1 , 8-2 . Accordingly a mirror current I _M is generated .

In a further step S2 , the generated mirror currents I _M are evaluated by a current mirror evaluation circuit 7 .

In a final step S3 , the semiconductor switching stage 5 is controlled by the current mirror evaluation circuit 7 depending on the evaluated mirror currents I _M to condition the electrical power supplied to the connected load 4 . The power conditioning apparatus 1 can be provided between a power sup- ply system and a load 4 . The power supply system can comprise an AC power supply system comprising one or more AC power supply phases . The power conditioning apparatus 1 can also in a possible embodiment be integrated on the input side of an electrical load 4 being connected to a power supply system .

The power conditioning apparatus 1 can in a possible embodiment comprise additional entities , in particular a user interface with a display unit adapted to display a momentary state of the semiconductor switching stage 5 , i . e . whether the power supply path is interrupted or not . Further, in a possible embodiment , the threshold values used by the comparator integrated in the driver circuit 9 can be adj usted via the user interface of the power conditioning apparatus 1 . In this way, it is possible to adj ust the sensitivity of the power conditioning apparatus 1 to the respective use case .

The user interface can be connected to a local controller of the power conditioning apparatus 1 . This local controller can be connected to a low voltage side of the driver circuit 9 . The local controller can in a possible embodiment comprise a data memory and a configuration memory . In a possible implementation the mirrored current applied to the current mirror evaluation circuit 7 is also digiti zed by an analog to digital converter ADC to provide mirror current data samples stored in the data memory of the local controller for further processing . In a possible embodiment the power supply path comprises besides the semiconductor switching stage 5 also a serially connected electromechanical stage having a relay controlled by the local controller of the power protection apparatus 1 . In a possible embodiment the mirrored current is evaluated by the hardwired current mirror evaluation circuit 7 of the power protection apparatus 1 to provide a fast reaction to events or faults such as overcurrent or overload or to provide a fast reaction to changing power supply conditions . In a possible embodiment the digiti zed mirrored current is at the same time in parallel evaluated by the local controller comprising a microcontroller 50 to provide additional safety, in particular i f the current mirror evaluation circuit 7 itsel f fails . The mirror current I _M can be digiti zed by an analog to digital converter ADC and mirror current samples provided by the ADC can be stored in a data memory of the microcontroller 50 . The local microcontroller 50 can switch of f the MOSFETs 8- 1 , 8-2 of the power supply path i f the monitored digiti zed mirrored current exceeds a threshold value .

Since the sensor components of the current mirror evaluation circuit 7 have only to measure the mirrored current I _M which is a fraction of the load current I _L , the si ze of the sensor components used in the current mirror evaluation circuit 7 can be very small thus allowing to miniaturi ze the power conditioning apparatus 1 . Further, the power dissipated by the measurement components is minimal because of their small si ze . The power supply path is set up with an absolutely minimal amount of components . In a possible embodiment the load current I _L flowing to the load 4 during normal operation of the power condition apparatus 1 may comprise more than 10 Ampere . At these high load current amplitudes the provision of sensor components within the main power supply path is hardly feasible because these high load current amplitudes would require large sensor components in the main power supply path which cannot be easily integrated and which involve large fabrication ef forts and which cause high electrical power losses during operation .

Summari zing, the present invention relates to a power conditioning apparatus for conditioning electrical power supplied to a load . The power conditioning is performed in response to a mirrored load current flowing through the power conditioning apparatus to the load . A current mirror evaluation circuit analyses the mirror current by means of hardware elements in order to determine an amplitude or a raising speed of the current . Since the whole approach is performed by discrete hardware elements a very fast and reliable response to the load current can be achieved .