Background Art Conventionally, the clock skews, as shown in Fig. 1, are statistically estimated by using a time interval analyzer or a frequency counter. The time interval analyzer measures the time difference of the zero-crossing points between the clock signal under test and a reference clock signal, then measures its fluctuation through a histogram analysis. An example of such a clock skew measurement using a time interval analyzer is described in Jitter Analysis clock Solutions, by Wavecrest Corporation, 1998.

When evaluating reliability of a microprocessor, for example, it is effective to determine whether the probability of the peak-to-peak value in the clock skews distributed within the microprocessor exceeds the predetermined value, or to confirm that the occurrence probability of the peak-to-peak value in

the clock skews will not exceed the predetermined value. However, since the occurrence probability of the peak-to-peak value of the clock skews have never been theoretically analyzed, the traditional method requires an enormous amount of data to estimate the occurrence probability of the peak-to-peak value of the clock skews, and thus, the probability estimation requires a large amount of time.

Furthermore, there is a problem in this clock skew measurement method using the time interval analyzer that it takes a long time to acquire a number of data required for the histogram analysis since, it requires an intermediate dead-time until clock skew measurement can be repeated. In addition, in the clock skew measurement method using the time interval analyzer, a skew between clocks having different frequencies cannot be measured. Therefore, a new clock skew measurement method is required for a precise control of a local clock and a global clock.

Disclosure of Invention Therefore, it is an obj ect of the present invention to provide an apparatus and method for measuring and probability estimating for clock skews which overcome the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.

According to the first aspect of the present invention,

an apparatus for estimating occurrence probability of peak-to-peak values in clock skews among several clock signals under test, comprising: a clock skew estimator for estimating clock skew sequences among several clock signals under test ; and a probability estimator for determining and outputting the occurrence probability of the peak-to-peak values in the clock skews among the signals under test based on the clock skew sequences.

The probability estimator may determine and output the occurrence probability of the peak value in the clock skews among the signals under test based on said clock skew sequences.

The probability estimator may include: an RMS (root mean square) detector fordetermininganRMSvaluebasedonthesupplied clock skew sequences ; a memory for storing a predetermined value ; and a probability calculator for determining and outputting the probability of the peak-to-peak clock skews among the signals under test which exceeds the predetermined value based on said predetermined value and said RMS value.

The probability estimator may include; an RMS detector for determining an RMS value of the supplied clock skew sequence ; a Peak-to-peak detector for calculating the maximum and minimum values of said clock skew sequence data to determine the peak-to-peak value ; and a probability calculator for determining and outputting the probability of the clock skews between the signals under test which exceeds the peak-to-peak value based

on said peak-to-peak value and said RMS value of the clock skew sequence data.

The clock skew estimator may include; a timing jitter estimator for estimating the timing jitter sequences of a plurality of clock signals under test ; and a clock skew calculator for receiving a plurality of said timing jitter sequences and calculating timing difference sequences therebetween to output the clock skew sequences.

The clock skew estimator may further include a second clock skew calculator for receiving said clock skew sequences as inputs to determine the difference sequence between the plurality of said clock skew sequences.

The clock skew estimator may further include a frequency multiplier for receiving said timing jitter sequences and outputting timing jitter sequences, the frequency of which is a multiple of the frequency of said signals under test.

The clock skew estimator may further include a deterministic clock skew estimator for estimating timing errors between ideal clock edges of a plurality of clock signals under test to output the deterministic components of said clock skews.

The timing jitter estimator may include: an analytic signal transformer for transforming the signals under test into

complex analytic signals; an instantaneous phase estimator for determining instantaneous phases of said analytic signals ; a linear trend remover for removing linear phases from said instantaneous phases to obtain instantaneous phase noise; and a zero-crossing resampler for receiving said instantaneous phase noise and resampling only the ones closest to zero-crossing timings of the real part of said analytic signals to output the timing jitter sequences.

The analytic signal transformer may include: a band-pass filter for receiving the signals under test and extracting only the components closest to the fundamental frequency from the signals under test to band-limit said signals under test; and a Hilbert transformer for Hilbert-transforming the output signals of said band-pass filter to generate Hilbert pairs of the input signals.

The analytic signal transformer may include : a time domain to frequency domain transformer which is provided with the signals under test for transforming the signals under test to both-side spectra signals in the frequency domain; a bandwidth limiter for extracting only the spectral signal components closest to the positive fundamental frequency from those both-side spectra signals; and a frequency domain to time domain transformer for transforming the outputs of said bandwidth limiter back to the time domain signals.

The analytic signal transformer may include: a buffer memory which receives the signals under test and stores the signals therein, and is structured by means for sequentially extracting the signals stored in the buffer memory while overlapping the extracted signals with a part of the previously extracted signals ; <BR> means for multiplying a window function with each of saidextracted signals; means for transforming the multiplied extracted signals to both-side spectra signals in a frequency domain; a bandwidth limiter for extracting only the components closest to the positive fundamental frequency of the signals under test from said both-side spectra signals transformed into the frequency domain ; means for transforming the outputs of said bandwidth limiter back to the time domain signals; and means for multiplying an inverse window function with the signals transformed into the time domain to obtain band-limited analytic signals.

The clock skew estimator may further include an AD (analog-to-digital) converter for receiving said signals under test and converting the analog signals to digital signals.

The clock skew estimator may further include a waveform clipper for receiving said signals under test and removing the amplitude modulation components of the signals under test and extracting only the phase modulation components of the signals under test.

The analytic signal transformer may have an adjustable

pass band for the signals under test.

The clock skew estimator may further include a random clock skew estimator for estimating random components of said clock skews based on said timing jitter sequences of said plurality of signals under test.

According to the second aspect of the present invention, a method for estimating occurrence probability of peak-to-peak values in clock skews among a plurality of clock signals under test, comprising steps of: estimating the clock skew sequences among the plurality of clock signals under test; and determining and outputting the occurrence probability of a peak-to-peak value of the clock skews among the plurality of signals under test based on said clock skew Sequences.

According to the third aspect of the present invention, a method for estimating the occurrence probability of the peak-to-peak value in clock skews among a plurality of clock signals under test, comprising steps of: estimating the clock skew sequences among the plurality of clock signals under test; and determining and outputting the occurrence probability of the peak value of the clock skews among the plurality of signals under test based on said clock skew Sequences.

The step of determining the occurrence probability of said peak-to-peak clock skews may include: a step of determining an

RMS value of the supplied clock skew sequence data; and a step of determining the probability of the peak-to-peak clock skews among the plurality of signals under test that exceeds the predetermined value based on said predetermined value and said RMS value.

The step of determining the occurrence probability of said peak-to-peak clock skews may include: a step of determining the RMS value of the supplied clock skew sequence data, a step of calculating the difference between the maximum and minimum values of said clock skew sequence data to determine the peak-to-peak value; and a step of determining the probability of the clock skews among the signals under test that exceeds the peak-to-peak value based on said peak-to-peak value and said RMS value of said clock skew sequence data.

The step of estimating said clock skew sequences may include: a step for estimating the timing jitter sequences of the plurality of clock signals under test ; and a step for receiving several of the timing jitter sequences and calculating the differences among them to estimate the clock skew sequences.

The step of estimating said clock skew sequences may include a step of receiving said clock skew sequences and determining the difference sequence among the plurality of the clock skew sequences, thereby estimating the probability of peak-to-peak clock skews.

The step of estimating said clock skew sequences may further include a step of receiving said timing jitter sequences to estimate timing jitter sequences of the frequency multiplied signals under test.

The step of estimating the clock skew sequences may further include a step of estimating the timing errors among the ideal clock edges of said plurality of clock signals under test to estimate the deterministic components of said clock skews.

The step of estimating said timing jitter sequences may further include: a step of transforming the signals under test into complex analytic signals ; a step of determining the instantaneous phase of the signals under test based on said analytic signals; a step of removing the linear phase from said instantaneous phase to estimate the instantaneous phase noise; and a step of receiving said instantaneous phase noise and resampling only the instantaneous phase noise data closest to zero-crossing timings of the real part of said analytic signals to output the timing litter sequences.

The step of transforming said signals under test into said analytic signals may include: a step of removing only the components closest to the fundamental frequency from said signals under test to band-limit said signals under test; and a step of Hilbert-transforming the output signals of said bandwidth

limiter to generate the Hilbert pair of the input signals.

The step of transforming said signals under test into said analytic signals may include : a step of transforming said signals under test into both-side spectra signals in a frequency domain; a step of removing only the components closest to the positive fundamental from said both-side frequency spectra signals; and a step of transforming the band-limited spectra signals back into time domain signals.

The step of transforming said signals under test into said analytic signals may include: a step of storing the signals under test in a buffer memory; a step of sequentially extracting the signals from the buffer memory while overlapping a part of said extracted signals with the previously removed signals; a step of multiplying a window function with each of said extracted signals; a step of transforming each of said multiplied signal into both-side spectra signals in the frequency domain; a step of extracting only the components closest to the positive fundamental frequency of the signals under test from said both-side spectra signals transformed in the frequency domain; a step of transforming said band-limited spectra signals back to the time domain signals; and a step of multiplying an inverse of said window function with the signals transformed into the time domain to obtain band-limited analytic signals.

The step of estimating the deterministic components of

the clock skews among said signals under test may include a step of finding the deterministic components of the clock skews by receiving the linear instantaneous phase of said plurality of signals under test and determining the difference among the initial phase angles of said linear instantaneous phase.

The step of estimating the deterministic components of the clock skews among said signals under test may further include a step of estimating the clock edges corresponding to one another and determining the offset value of said clock edges by receiving the timing jitter sequences of said plurality of signals under test and determining the correlation among them.

The step of estimating the deterministic components of the clock skews among said plurality of signals under test may include a step of finding the deterministic components of the clock skews by receiving said plurality of signals under test and determining the average value of the errors in the zero-crossing timings among said plurality of signals under test.

The step of estimating said clock skew sequences may include a step of conducting waveform clippings for the signals under test to remove the amplitude modulation components in said signals under test and to extract only the phase modulation components in said signals under test.

The step of estimating the clock skew sequences may further

include a step of estimating random components of said clock skews based on said timing jitter sequences of said plurality of signals under test.

According to the fourth aspect of the present invention, an apparatus for measuring a clock skew between a plurality of clock signals under measurement comprising: a timing jitter estimator to which the plurality of clock signals under measurement are inputted for estimating their respective timing jitter sequences ; and a clock skew estimator to which the plurality of timing jitter sequences are inputted for calculating a timing difference sequence between those timing jitter sequences to output a clock skew sequence.

The apparatus may further comprise a second clock skew estimator to which a plurality of the clock skew sequences are inputted for obtaining a difference sequence between the plurality of clock skew sequences.

The apparatus may further comprise a frequency multiplier to which the timing jitter sequence is inputted for multiplying a frequency of the timing jitter sequence to output the frequency-multiplied timing jitter sequence to said clock skew estimator.

The apparatus may further comprise a frequency multiplier to which the timing jitter sequence is inputted for multiplying

a frequency of the timing jitter sequence to output the frequency-multiplied timing jitter sequence to said clock skew estimator.

The apparatus may further comprise a deterministic clock skew estimator for estimating a timing error between ideal clock edges of the plurality of clock signals under measurement to output a deterministic component of clock skew to said clock skew estimator, wherein said clock skew estimator is an estimator for adding the deterministic component of clock skew to the timing difference sequence to output the summed values as the clock skew sequence.

The apparatus may further comprise a clock skew detector to which the clock skew sequence is inputted for obtaining clock skew values of the clock signals under measurement from the clock skew sequence.

The clock skew detector may include one or a plurality of a peak-to-peak detector for obtaining a difference between <BR> the maximum value and the minimum value of the clock skew sequence, an RMS detector for obtaining a root-mean-square value of the clock skew sequence, and a histogram estimator for obtaining a histogram of the clock skew sequence.

The timing jitter estimator may include; an analytic signal transformer for transforming a clock signal under

measurement into a complex analytic signal; an instantaneous phase estimator for obtaining an instantaneous phase of the analytic signal; a continuous phase converter for converting the instantaneous phase into a continuous instantaneous phase; a linear phase estimator for estimating, from the continuous instantaneous phase, its linear instantaneous phase; a subtractor for removing the linear instantaneous phase from the continuous instantaneous phase to obtain an instantaneous phase noise; and a zero-crossing sampler for sampling its input at timings close to zero-crossing timings of a real part of the analytic signal to output the sampled signal, said zero-crossing sampler being inserted in series to any one of connection points between said instantaneous phase estimator and said continuous phase converter, between said continuous phase converter and said linear phase estimator/subtractor, and at an output side of said subtractor, and wherein a timing jitter sequence of the clock signal under measurement is outputted as an output of said timing jitter estimator.

The deterministic clock skew estimator of the plurality <BR> of clock signals under measurement maybe an estimator that obtains a difference between initial phase angles of the linear instantaneous phases to obtain a deterministic component of clock skew.

The analytic signal transformer may change a pass bandwidth of the clock signal under measurement. The analytic

signal transformer may have an adjustable pass band for the signals under test.

The apparatus may further include a random clock skew estimator for estimating random components of said clock skews <BR> based on said timing j itter sequences of said plurality of signals under test.

The apparatus may further comprise a waveform clipper to which the clock signal under measurement is inputted for removing amplitude modulation components of the clock signal under measurement in the state that phase modulation components are retained in the clock signal under measurement to output the clock signal under measurement from which the amplitude modulation components have been removed.

According to the fifth aspect of the present invention, a method of measuring a clock skew between a plurality of clock signals under measurement comprising : a step of estimating timing jitter sequences of the respective clock signals under measurement; and a step of calculating a timing difference sequence between the plurality of timing jitter sequences to estimate a clock skew sequence.

The method may further comprise a step of obtaining a difference sequence between the plurality of clock skew sequences to estimate a clock skew sequence.

The method may further comprise a step of assign each timing jitter of the timing jitter sequence M times to estimate a timing jitter sequence that is created by multiplying a frequency of the corresponding clock signal under measurement by (M+1).

The method may further comprise a step of assign each timing jitter of the timing jitter sequence M times to estimate a timing jitter sequence that is created by multiplying a frequency of the corresponding clock signal under measurement by (M+1).

The method may further comprise a step of estimating a timing error between ideal clock edges of the plurality of clock signals under measurement to estimate a deterministic component of clock skew, wherein said step of estimating a clock skew sequence is a step of adding the deterministic component of clock skew to the timing difference sequence to obtain the summed values as the clock skew sequence.

The method may further comprise a step of obtaining clock skew values of the clock signals under measurement from the clock skew sequence.

The step of obtaining a clock skew may comprise one or a plurality of a step of obtaining a difference between the maximum value and the minimum value of the clock skew sequence to calculate a peak-to-peak value, a step of obtaining a root-mean-square

value of the clock skew sequence to calculate an RMS value, and a step of obtaining a histogram data of the clock skew sequence.

The step of estimating a timing jitter sequence may comprise; a step of transforming a clock signal under measurement into a complex analytic signal; a step of obtaining an instantaneous phase of the clock signal under measurement from the analytic signal ; a step of converting the instantaneous phase into a continuous instantaneous phase; a step of estimating, from the continuous instantaneous phase, its linear instantaneous phase ; a step of removing the linear instantaneous phase from the continuous instantaneous phase to obtain an instantaneous phase noise; and a step of sampling any one of the instantaneous phase, the continuous instantaneous phase, and the phase noise waveform at timings close to zero-crossing timings of a real part of the analytic signal, and wherein a timing jitter sequence of the clock signal under measurement is eventually obtained.

The step of estimating a deterministic component of clock skew between the clock signals under measurement may be a step of obtaining a difference between initial phase angles of linear instantaneous phases of the plurality of clock signals under measurement to obtain a deterministic component of clock skew.

The step of estimating a deterministic component of clock skew between the clock signals under measurement may comprise:

a step of obtaining an offset signal in which either a correlation between timing j itter sequences of the plurality of clock signals under measurement or a correlation between instantaneous phase noises of the plurality of clock signals under measurement shows the maximum value to obtain an offset value of clock edge; and a step of obtaining a sum of the offset value and the difference between the initial phase angles to obtain the deterministic component of clock skew.

The step of estimating a deterministic component of clock skew between the clock signals under measurement may be a step of obtaining a mean value of differences of zero-crossing timings between the plurality of signals under measurement to obtain a deterministic component of clock skew.

The method may further include a step of estimating random components of said clock skews based on said timing jitter sequences of said plurality of signals under test.

The method may further comprise a step of performing a waveform clipping in the state that phase modulation components of the clock signal under measurement are retained to remove amplitude modulation components of the clock signal under measurement, and moving to the step of estimating a timing jitter sequence.

This disclosure of the invention does not necessarily

describe all necessary features so that the invention may also be a sub-combination of these described features.

Brief Description of Drawings Fig. 1 is a diagram showing an example of clock skew measurement using a time interval analyzer.

Fig. 2A is a schematic diagram showing a clock network for distributing clock signals.

Fig. 2B is a schematic diagram showing the timings in the clock skews.

Fig. 3 is a schematic diagram showing a relationship between the timing jitters and the clock skews.

Fig. 4 is a diagram showing an example of clock signal under test.

Fig. 5A is a diagram showing an example of timing jitter A ßi [n] of the clock signal xj (t) under test.

Fig. 5B is a diagram showing an example of timing jitter d k [n] of the clock signal Xk (t) under test.

Fig. 6 is a diagram showing an example of clock skew between the clock signal under test measured by the clock skew measurement method of the present embodiment.

Fig. 7 is a diagram showing an example of histogram of the clock skew between the clock signal under test measured by the clock skew measurement method of the present embodiment.

Fig. 8 is a schematic diagram showing a clock distribution network with different clock domains.

Fig. 9 is a schematic diagram showing principle of clock

skew measurement involving frequency multiplication.

Fig. 10 is a diagram showing an example of power spectra of a clock signal in a microprocessor.

Fig. 11 is a diagram showing an example of timing jitter histogram of a clock signal in a microprocessor.

Fig. 12 is a diagram showing a probability density function of the Rayleigh distribution.

Fig. 13 is a diagram showing a right-tail probability of the Rayleigh distribution.

Fig. 14 is a diagram showing a relationship between the number of events and the observed peak-to-peak clock skew values.

Fig. 15 is a diagram showing an example of clock signal under test.

Fig. 16 is a diagram showing an analytic signal of the clock signal under test.

Fig. 17 is a diagram showing an example of waveform of the instantaneous phase of the clock signal under test.

Fig. 18 is a diagram showing an example of waveform of the instantaneous phase noise of the clock signal under test.

Fig. 19 is a diagram showing an example of waveform of the timing jitter of the clock signal under test.

Fig. 20 is a diagram showing an example of clock signal under test.

Fig. 21 is a diagram showing a transformed analytic signal.

Fig. 22 is a diagram showing an example of instantaneous phase signal having a discontinuous instantaneous phase.

Fig. 23 is a diagram showing an example of continuous

instantaneous phase signal which has been unwrapped.

Fig. 24 is a diagram showing an example of digitized clock signal under test.

Fig. 25 is a diagram showing an example of both-side power spectra of the clock signal under test obtained through FFT.

Fig. 26 is a diagram showing an example of one side of the band-limited power spectra of the clock signal.

Fig. 27 is a diagram showing an example of analytic signal derived through FFT that is band limited.

Fig. 28 is a diagram showing an example of adaptive zero-crossing points of the clock signal under test.

Fig. 29 is a diagram showing an example of clock signal under test having AM components.

Fig. 30 is a diagram showing an example of clock signal under test without having AM components.

Fig. 31 is a diagram showing an example of structure in an apparatus for estimating probability of peak-to-peak clock skew in the present embodiment.

Fig. 32 is a flow chart showing an example of method for estimating probability of peak-to-peak clock skew in the present embodiment.

Fig. 33 is a diagram showing another example of structure in an apparatus for estimating probability of peak-to-peak clock skew in the present embodiment.

Fig. 34 is a flow chart showing another example of method for estimating a probability of peak-to-peak clock skew.

Fig. 35 is a diagram showing an example of structure in

a clock skew estimator in the present embodiment.

Fig. 36 is a flow chart showing an example of clock skew estimation method in the present embodiment.

Fig. 37 is a diagram showing an example of structure in the deterministic clock skew estimator in the present embodiment.

Fig. 38 is a flow chart showing an example of deterministic clock skew estimation method in the present embodiment.

Fig. 39 is a diagram showing another example of structure in the clock skew estimator in the present embodiment.

Fig. 40 is a flow chart showing another example of clock skew estimation method in the present embodiment.

Fig. 41 is a diagram showing a further example of structure in the clock skew estimator in the present embodiment.

Fig. 42 is a flow chart showing a further example of clock skew estimation method in the present embodiment.

Fig. 43 is a diagram showing an example of structure in the timing jitter estimator used in the clock skew estimator in the present embodiment.

Fig. 44 is a flow chart showing a further example of timing <BR> <BR> <BR> <BR> <BR> j itter estimating method used in the clock skew estimating method in the present embodiment.

Fig. 45 is a diagram showing an example of structure in the analytic signal transformer used in the clock skew estimator in the present embodiment.

Fig. 46 is a flow chart showing an example of analytic signal transformation method used in the clock skew estimating method in the present embodiment.

Fig. 47 is a diagram showing another example of structure in the analytic signal transformer used in the clock skew estimator in the present embodiment.

Fig. 48 is a flow chart showing another example of analytic signal transformation method used in the clock skew estimating method in the present embodiment.

Fig. 49 is a diagram showing a further example of structure in the analytic signal transformer used in the clock skew estimator in the present embodiment.

Fig. 50 is a flow chart showing a further example of analytic signal transformation method used in the clock skew estimating method in the present embodiment.

Fig. 51 is a diagram showing a further example of structure in the clock skew estimator in the present embodiment.

Fig. 52 is a flow chart showing a further example of clock skew estimation method in the present embodiment.

Fig. 53 is a diagram showing a further example of structure in the clock skew estimator in the present embodiment.

Fig. 54 is a flow chart showing a further example of clock skew estimation method in the present embodiment.

Fig. 55 is a diagram showing a further example of structure in the timing jitter estimator used in the clock skew estimator in the present embodiment.

Fig. 56 is a flow chart showing a further example of timing j itter estimating method used in the clock skew estimating method in the present embodiment.

Fig. 57 is a block diagram showing a functional

configuration of an example of a clock skew measurement apparatus according to the present embodiment.

Fig. 58 is a flow-chart showing an example of a clock skew measurement method according to the present embodiment.

Fig. 59 is a block diagram showing a functional configuration of a specific example of a deterministic clock skew estimator 3102 shown in Fig. 57.

Fig. 60 is a flow-chart showing a processing example of a deterministic clock skew estimating step of the step 3202 shown in Fig. 58.

Fig. 61 is a block diagram showing a functional configuration of another example of the clock skew measurement apparatus according to the present embodiment.

Fig. 62 is a flow-chart showing another example of the clock skew measurement method according to the present embodiment.

Fig. 63 is a block diagram showing an example of a functional configuration of a timing jitter estimator used in the clock skew measurement apparatus according to the present embodiment.

Fig. 64 is a flow-chart showing an example of a timing <BR> <BR> <BR> <BR> <BR> j itter estimation method used in the clock skew measurement method according to the present embodiment.

Fig. 65 is a block diagram showing another example of a functional configuration of an analytic signal transformer used in the clock skew measurement apparatus according to the present embodiment.

Fig. 66 is a block diagram showing further another example

of a functional configuration of an analytic signal transformer used in the clock skew measurement apparatus according to the present embodiment.

Fig. 67 is a flow-chart showing further another example of the analytic signal transformation method used in the clock skew measurement method according to the present embodiment.

Fig. 68 is a block diagram showing a portion of another example of the apparatus according to the present embodiment.

Fig. 69 is a flow-chart showing a portion of another example of the method according to the present embodiment. and Fig. 70 is a block diagram showing another example of a functional configuration of the deterministic clock skew estimator 3102.

Best Mode for Carrying Out the Invention The invention will now be described based on the preferred embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention. In the following, MPU clock signals are used as signals to be tested for the purpose of explanation of the invention.

Clock Skew Measuring Method First, the clock skew will be defined. As shown in Fig.

2A, where, for example, the clock source of the clock distribution network is used as a reference point, the clock skew is defined

as a difference between delay times # cdj and #cdk before clock signals CLKj and CLKk arrive at registers Rj and Rk.

Fig. 2B shows the timings of the clock skews. Here, T is a fundamental clock period of the clock signals under test.

The rising edge times of the clock signal CLKg, CLKj, and CLKk are denoted by tcdg, tcdj, and tk cd respectively. Also, when the ideal clock edge times (the jitter-free clock edge times) of each clock signal CLKg, CLKj, and CLKk are denoted by (nT) g, (nT) j, and (nT) k, the delay times #cdj and #cdk Will be respectively expressed as follows:

The following equations express the respective time differences between the ideal clock edge times of CLKj, CLKk and the ideal clock edge time CLKg, and correspond to the deterministic components (deterministic clock skew values) of the clock skew determined by signal paths.

In addition, ##g [n] (Tg/2#) (=tcdg(nT)-(nT)g), # #j [n] (Tj/2 z) (=tod (nT)-(nT) j), and ##k [n] (Tk/2#) (=tcdk(nT)-(nT)k) express the timing jitter sequences (unit in second) of the clock signals CLKg, CLKj, and CLKk respectively. When equations (2) and (3) are substituted into equation (1), the clock skew TiIkskew in CLKj and CLKk will be estimated as follows: The second member in the equation (6) as noted below corresponds to the random variation (random component) of the clock skew based on the timing jitters in each clock signal.

In other words, this clock skew estimation method can determine the random distribution of a clock skew by combining the amount of distance between the clock edges of each clock signal and the ideal clock edge, namely, the timing jitters of each clock signal. Here, the fundamental periods of the generally distributed clock signals CLKj and CLKk are identical to one another (Tj=Tk). Fig. 3 shows the relationship between the timing jitter and clock skew.

The following equation expresses the difference between the rising edge times of the ideal clocks of the clock CLKj and CLKk, and are the deterministic components of the clock skew determined by the signal paths of the clock distribution network: The deterministic clock skew value ci, k Skewi for example, can be determined by the instantaneous phases of two signals CLKj, CLKk under test and the difference between their linear phase components in the instantaneous phases. The fundamental cosine wave components of the signals CLKj and CLKk are as follows :

Here, the instantaneous phases of xj (t) andxk (t) are respectively expressed by the sum of the instantaneous linear phase component 2 71 t/TL having the fundamental period TL (L=j, k), initial phase angle g Lo (L =j, k}, and instantaneous phase noise component A L (t) (L=j, k).

The estimation method for the instantaneous phase in the clock signals, however, will be explained later. When A 0 (t) =0 is used in equations (10) and (11), the instantaneous linear phase in the jitter-free clock signals are obtained as follows:

Here, the ideal rising edge times t= (nT) j, and t= (nT) k of the <BR> <BR> signalsCLKjandCLKkarethetimes wheretheinstantaneouslinear phase becomes (2n#-#/2), and have the following relationship from equations (12) and (13): Therefore, per equation (7), the following deterministic clock skew value is obtained: In general, the fundamental periods of the distributed clock

signals CLK and CLKk are the same with one another (Tj=Tk). In other words, the deterministic clock skew value between the two signals under test can be determined as a difference between the initial phase angles in the instantaneous linear phase of those two signals under test.

Here, the initial phase angle Oo of the signals under test can be obtained by conducting a linear line fitting for the instantaneous phase waveform data (k) based on the minimum square method and choosing the formula below in such a way that #0 becomes the minimum: Here, the initial phase angle to be determined is expressed as follows : The estimation of parameters based on the linear line fitting is described, for example, on page 362 of J. S. Bendat and A.

G. Piersol"Random Data: Analysis and Measurement procedure", 2d edition, published by John Wiley & Sons, Inc. in 1986.

Further, the initial phase angle zozo of signal x (t) under test can be obtained by conducting a cosine wave fitting for the clock waveform data x (k) or fundamental sine wave component based on the minimum square method in the following equation in such a way that 6 becomes the minimum through the maximum likelihood estimation method:

Here, the initial phase angle to be determined is expressed as follows:

The estimation of the parameter based on the maximum likelihood estimation is described, for example, on pages 167-172 of S.

M. Kay"Fundamentals of StatisticalSignal Processing : Estimation Theory", Published by Prentice-Hall, Inc. in 1993.

In the foregoing, it is assumed that the clock edges corresponding to the two signals under test are separated no more than one period from one another. When the corresponding clock edges are separated more than one period, the deterministic clock skew value is determined by the difference between the initial phase angles and by the sum of the offset times of those clock edges. 7-J. k/j 'Io rp Skew \ 0 0/2 offset 0 [sec] (21)

The clock signal distributed from the clock signal source has a close relationship with the clock signal source. As a result, the phase noise in the distributed clock signals (timing jitter sequences) generally show a similar trend with the phase noise in the clock signal source (timing jitter sequences). Due to this, the timing jitter sequences of the plural clock signals distributed from the same clock signal source both show similar characteristics to one another (see Figs. 5Aand5B). Therefore, the offset amount noffset in the clock edges corresponding to the two signals under test canbe determinedbythe correlationbetween the timing jitter sequences through estimation by finding an offset position where the correlation value is the largest. The offset amount noffset in the above clock edges can also be determined based on the offset position where the correlation value of the instantaneous phase noise becomes the largest.

In addition, the deterministic clock skew can be found by determining the zero-crossing timings of each signal under test and calculating the average value of the time difference between the corresponding zero-crossings.

This clock skew estimation method of the present invention first determines the timing jitters A ßi [n] andA k [n] of the two signals xj (t), Xk (t) under test as shown in Fig. 4. The determined timingjitterwaveforms A ßi [n] and A ß k [n] are shown in Figs. 5A and 5B respectively. Next, the deterministic skew value #j,kSkew between the two signals xj (t), Xk (t) under test is determined. Then, the timing difference of the clock edges are determined by calculating the difference between the timing jitter j [n] and A ok [n] so that the random components of the clock skew between signals xj (t), Xk (t) under test can be determined. By calculating the sum of the random components and deterministic components in the clock skew, the clock skew Tj,kSkew[n] between the signals under test can be determined. The determined clock skew Ti'kSkew [n] is shown in Fig. 6. Next, the RMS value and the peak-to-peak value in the clock skew will be measured from the clock skew sequence TgkewM-The RMS value TilkskewlRMs of the clock skew is the standard deviation for clock skew Tj,kSkew[n], and is determined by the following equation: Here, N is a number of samples of the measured clock skew data.

Also, the peak-to-peak value Tj,kSkew,pp of the clock skew is a difference between the maximum and minimum value of Tilkskew [n] and is determined by the following equation:

Fig. 7 shows the histogram of the clock skew measured by this clock skew measurement method.

This clock skew estimation method can also measure the clock skews between the clock signals with different frequencies.

Here, the clock distribution network shown in Fig. 8 is considered.

The clock source PLLg multiplies the system clock CLKG provided from an external source by M times and distributes the clocks CLKj and CLKk to the network. Fig. 9 (a) shows the system clock CLKG, and Fig. 9 (c) shows the multiplied clock CLKj. The i\ 0 [1] [rad] of the system clock CLKG indicates the time fluctuation between that edge and the ideal clock edge. Therefore, as shown in Fig. 9 (b), assuming that the ideal clock edge is multiplied by M times, A i [#n/M#] and ##j [n] become 1: 1 when A 0 [1] is copied by M-1 times. Here, the #x# indicates a maximum integer where it does not exceed x. By calculating the clock skew between CLKjandCLKGWithequation (6), equation (24) is formed as follows : The deterministic clock skew value sGJskew between the clocks CLKj and CLKG is expressed as the time difference between the ideal clock edge (nMT) j of the clock CLKj and the ideal clock edge (nMT) G of the system clock CLKG, and can be determined from the initial phase angle of each clock signal as follows:

Here, since the clock CLK is a clock which multiplied the system clock CLKG by M times, the fundamental period TG of the system clock CLKG is equivalent to M times of the fundamental period Tj of CLKj (TG=MTj).

In addition, by using an apparatus capable of measuring two channels at the same time to first sample CLK and CLKg then sample CLKk and CLKg, this clock skew measurement method can measure the clock skew between CLK and CLKk.

First, the clocks CLK and CLKg are sampled at the same time to determine the skew ofthose CLK ; and CLKg byusingequation (6): Next, CLKk and CLKg are sampled at the same time to determine the skew of those CLKk and CLKg in a similar manner:

Lastly, by determining the difference between the clock skew sequences calculated above, the clock skew between CLKj and CLKk can be obtained:

This clock skew measurement method can not only estimate the clock skews between the distributed MPU clock signals mentioned above, but it can also be applied to estimate the clock skews of other signals.

Generation Probability Estimating Method for Peak-to-Peak'Value of Clock Skew Next, the probability estimating method for peak-to-peak clock skews in the present invention will be explained.

Fig. 10 shows the power spectra determined by using the <BR> Fast Fourier Transformon the clockwaveformof the microprocessor.

The upper diagram shows the quiet mode in the microprocessor,

namely the power spectra in an inactive state of the microprocessor, and the lower diagram shows the noise mode in the microprocessor, namely the power spectra in an active state of the microprocessor.

In the quiet mode, only the PLL (phase-locked loop) circuit operates to output the clock signals, and is in the condition where the clocks are not affectedby surrounding circuit operation.

In the noise mode, all of the L2 (level 2) memories, system bus, core bus, and branch prediction units in the microprocessor operate, and is in the condition where the clock is heavily affected by the surrounding circuit operations. In either conditions, the line spectrum in the clocks is observed at 400MHz Where the random instantaneous phase noise is seen in a nearby frequencybandwithrespecttothecenterfrequency400MHz. This indicates the existence of narrow-band random data. In addition, the probability density function of the timing jitters in the above clock signals is in a Gaussian distribution as shown in Fig. 11. Therefore, the timing jitter sequences in the clock signals is a Gaussian-based random process.

As mentioned above, the clock skew TjkSkew between the 2 clock signals is expressed as follows, and their random component TjtkRS is expressed as the difference between the timing jitter sequences as follows:

Therefore, when the probability density function of the timing jitters A i [n] and A 0 k [n] in each clock signal shows an average value 0 and a dispersion # in the Gaussian distribution, the probability density function of TitkRs is expressed as the convolution,

where it becomes a Gaussian distribution by central limit theorem :

In other words, the random component TikRs in the clock skew is also a Gaussian-based random process.

In the narrow-band random process {Z[n]}, when a certain

instantaneous value Z [n] is subject to Gaussian distribution, the peak value collection, namely the maximum value collection of Z [n] {max (Z [n])}, becomesclosertoRayleighdistributionwhen the degrees of freedom n (number of sample) is made larger. This principle is described, for example, on page 542 of J. S. Bendat and A. G. Piersol"Random Data: Analysis and Measurement Procedure", 2nd Edition, published by John Wiley & Sons, Inc. in 1986, or on pages 90-92 of D. E. Newland"An Introduction to Random Vibrations, Spectral & Wavelet Analysis", published by Longman Scientific & Technical in 1993.

As explained above, by the existence of the random components Tiers of the clock skew and that random components TjkRsbeing subject to the Gaussian distribution, the peak value collection {Zp} = {max (TjkRs [n])} of the random components of the clock skew becomes subject to the Rayleigh distribution.

The Rayleigh destitution is described on pages 30-31 of S. M.

Kay"Fundamentals of Statistical Signal Processing: Detection Theory", published by Prentice-Hall, Inc. in 1998.

The probability density function Pr (Zp) of the Rayleigh distribution is known to be expressed by the following equation:

Here, az is the RMS value of clock skew Ti kRS, and a 2 is the dispersion. The Rayleigh probability density function is, as shown in Fig. 12, Pr (Zp) # 0 when Zp > 0.

Further, when the peak value Zp is subject to the Rayleigh distribution, the probability of Zp becomes larger than a certain value #pk is known to be expressed by the following equation (right-tail probability):

Also, the standard deviation of #pk is expressed by the following equation:

The probability Pr(Zp > #pk) is shown in Fig. 13.

Therefore, by setting #pk as the worst case peak value of the random components in the clock skew and measuring the root mean square #z2 in the clock skew of the signal under test, the probability of the random components in the clock skew of the signal under test that exceeds the worst case peak value #pk can be estimated, where the reliability of that clock distribution network becomes higher as the probability becomes

lower.

Based on the consideration described above, the probability estimating method for peak-to-peak clock skews in the present invention determines the occurrence probability of the peak value in those clock skews between the Signals under test.

Further, by removing the low frequency. components from the instantaneous phase noise, the probability density function in the timing jitters can become closer to the Gaussian distribution, thereby improving the accuracy in the probability estimation.

Also, when the probability for peak value Zp of the timing jitter of the input signal that exceeds the peak value #pk is given by the equation (35), the probability for the peak-to-peak value Jpp of the jitter that exceeds #pp as shown below can be obtained from the product of the probability for positive peak value Zp+ to exceed +#pp/2, and the probability for negative peak value Zp- that exceeds -#pp/2:

Based on the foregoing observation, the probability estimation method for peak-to-peak clock skews of the present invention determines the occurrence probability of the peak-to-peak value in the clock skews between the signals under test.

In Fig. 14, the samples and peak-to-peak values are plotted for the clock skews between the two signals under test, which have been distributed within the microprocessor. The upper diagram shows the test results in the quiet mode in the microprocessor, and the lower diagram shows the test results in the noise mode. The theoretical curve in the diagrams are calculated from the inverse probability Pr(Zpp>#pp) expressed by the equation (38). The test data complies very well with the theoretical curves of the Rayleigh distribution (especially in the noise mode).

Timing Jitter Estimation Method Next, the timing jitter estimation method incorporated in the present invention is described hereafter.

A jitter-free clock signal is a square wave with a fundamental frequency fo. These signals can be separated into harmonics frequencies including fo, 3fo, 5fo and so forth based on the Fourier analysis. Since the jitter corresponds to the fluctuation of the fundamental frequency of the signal under test, only the signal components closest to the fundamental frequency will be considered in the jitter analysis.

The fundamental sinusoidal wave component in the clock signal (signal under test) with jitter is expressed as follows, where A represent an amplitude of the clock signal and To represents the fundamental period of the clock signal: Here, g (t) represents an instantaneous phase of the signal under test, and is expressed as a sum of the linear phase component 2xt/To having the fundamental period To, an initial phase angle ¢0 (can be zero in the calculation), and the instantaneous phase noise component A ß (t).

When the instantaneous phase noise component A ß (t) is zero, an interval between the rising zero-crossing points of the signal under test is merely the constant period To The non-zero instantaneous phase noise component A 0 (t) causes to fluctuate

the zero-crossing points of the signal under test. In other words, A (nTo) in the zero-crossing point nTo indicates the time fluctuation of the zero-crossing points, and is called a timing jitter. Therefore, by estimating the instantaneous phase 0 (t) of the signal under test and finding the difference between that instantaneous phase and linear phase in the zero-crossing points (which corresponds to the phase waveform of the ideal jitter-free clock signal), namely the instantaneous phase noise A 0 (t), the timing jitters in the signals under test can be determined.

First, the timing jitter estimation method of the present invention converts the signal x (t) under test shown in Fig. 15 into an analytic signal Z (t) of a complex number. The converted analytic signal Z (t) is shown in Fig. 16. In Fig. 16, the continuous line indicates the real part of the analytic signal and the broken line indicates the imaginary part of the analytic signal. Next, an instantaneous phase A 0 (t) of the signal x (t) under test will be estimated from the analytic signal Z (t). The estimated instantaneous phase waveform 0 (t) is shown in Fig.

17. Then, by conducting a linear line fitting for the instantaneous phase waveform data based on the minimum square method, determining the linear phase 1inear (t) corresponding to <BR> <BR> <BR> <BR> the instantaneous phase waveform in the ideal j itter-free signal, and calculating the difference between the instantaneous phase 0 (t) and that linear phase linear (t), the instantaneous phase noise A (t) in the signal under test is determined. The

instantaneous phase noise waveform A 0 (t) determined in this manner is shown in Fig. 18. Further, the instantaneous phase noise waveform A 0 (t) is sampled at a timing closest to each zero-crossing point (analogous zero-crossing point) in the real part x (t) of the analytic signal z (t), and the instantaneous phase noise in the zero-crossing timing nTo, namely the timing litter A ß [n] (=##[nT0], is thereby estimated. The estimated timing jitter waveform A A [n] is shown in Fig. 19.

With the use of a waveform clipper, the timing jitter estimation method of the present invention can estimate the timing jitter with high accuracy by removing the AM (amplitude modulation) components from the signals under test and retaining only the PM (phase modulation) components corresponding to the jitter.

Also, by using means for removing low frequency components, the timing jitter estimation method of the present invention can remove the low frequency components from the instantaneous phase noise signals.

Instantaneous Phase Estimation Method Using Analytic Signals The analytic signal z (t) of the real signal x (t) is defined by a complex signal in the following equation: z (t) s x (t) + j x (t) (40)

Here, j is an imaginary unit, and an imaginary part #(t) of the complex signal z (t) is a Hilbert-transformation of the real part x (t).

Meanwhile, the Hilbert transformed time waveform x (t) is defined by the following equation: Here, #(t) is the convolution of the function x(t) and (1/# f). In other words, the Hilbert transformation is equivalent to the x(t) that has passed through a band-pass filter. However, the spectra component in the output #(t) at this time will not change in the amplitude, but the phase shifts by tut/2.

The analytic signal and Hilbert transformation are described, for example, in A. Papoulis"Probability Random Variables and Stochastic Processes", 2nd Edition, published by McGraw-Hill Book Company, 1984.

The instantaneous phase waveform ¢ (t) of the real signal x (t) is determined by using the following equation from the analytic signal z (t):

Next, the algorithm for estimating the instantaneous phase with use of the Hilbert transformation is explained below. First, by applying the Hilbert transformation to the signal under test shown in Fig. 20 and determining a signal corresponding to the imaginary part of the complex signal,

the signal x (t) under test is transformed into an analytic signal in the equation (45): The transformed analytic signal is shown in Fig. 21. Here, a band-pass filter process is applied to the obtained analytic signal. This is for handling only the signal components closest to the fundamental frequency of the signal under test in the <BR> <BR> j itter analysis because the j itter corresponds to the fluctuation of the fundamental frequency of the signal under test. Next, the phase function (t) is estimated by using equation (42) from the determined analytic signal z (t):

Here, # (t) is expressed by using the principal value of a phase range, between- and + ? c, and carries discontinuous points near the conversion point from +x to-z. The estimated phase function 0 (t) is shown in Fig. 22. Lastly, by unwrapping the discontinuous phase function 0 (t) (namely, appropriately adding the integer multiple of 2x to the principal value (t)), the discontinuity can be removed to obtain the continuous instantaneous phase # (t).

The phase unwrapping method is described in Donald G. Childers, David P. Skinner, and Robert C. Kemerait"The Cepstrum : A Guide to Processing, volume 65, published by Proceedings of IEEE, 1977. The unwrapped continuous instantaneous phase function 0 (t) is shown in Fig. 23.

Transformation to Analytic Signal Using Fast Fourier Transformation The transformation from the real signal to the analytic

signal can be fulfilled by a digital signal process using Fast Fourier Transformation (FFT).

First, the FFT is applied to the digitized signal x (t) under test as shown in Fig. 24 to obtain both-side power spectra (with positive and negative frequency) X (f) of the signal under test. The obtained both-side power spectra X (f) is shown in Fig. 25. Then, all data is emptied except for the data closest to the fundamental frequency from the positive frequency components of the spectra X (f), and doubles the positive frequency components. Such processes in the frequency domain corresponds to the band-limit process of the signal under test in the time domain to obtain the analytic signal. The obtained signal Z (f) in the frequency domain is shown in Fig. 26. Lastly, by applying an inverse FFT to the obtained signal Z (f), the band-limited analytic signal z (t) can be obtained. The band-limited analytic signal z (t) is shown in Fig. 27.

TheanalyticsignaltransformationusingFFTisdescribed, for example, in J. S. Bendat and A. G. Piersol"Random Data: Analysis and Measurement Procedure", 2nd Edition, published by John Wiley & Sons, Inc. in 1986.

Alternatively, when the instantaneous phase estimation is the object, the process of doubling the positive frequency component can be omitted.

Detection Method for the Analogous Zero-Crossing Points Next, the detection method for the analogous zero-crossing points will be explained. First, a signal value Vso% at the 50% level of the analytic signal of the input signal to be tested is calculated as a zero-crossing level, where the maximum value for the real part x (t) of the analytic signal is at a 100% level thereof and the minimum value is at a 0% level thereof. Then, the difference between each adjacent sample value and the 50% level V5o%, namely, (x (j-l)-V5o%) and (x (j)-V50%) is calculated to further determine their product (x (j-l)-V5o%) X (x (j)-V50%).

When x (t) is crossing the 50% level, namely the zero-crossing level, thesymbolofthesesamplevalues (x (i-1)-Vso%) s (x (i)-vso%) Change from negative to positive or vice versa, therefore, when the above product is negative, it means that x (t) crosses the zero-crossing level, where time j-1 or j with a smaller absolute value from sample values (x (j-1)-V50%), (x (j)-V5o%) at that point <BR> is determined as the analogous zero-crossing point. The waveform of the real part x (t) of the analytic signal is shown in Fig.

28. The circle marks in Fig. 28 show the points closest to the detected rising zero-crossing point (analogous zero-crossing point).

Waveform clipping Waveform clipping means is able to remove the AM components from the input signal to retain only the PM components in the input signal corresponding to the jitters. The waveform clipping for the analog or digital input signal is conducted by (1)

multiplying the signal value by a constant number, (2) replacing the signal value larger than the predetermined threshold value 1 with threshold value 1, and (3) replacing the signal value smaller than the predetermined threshold value 2 with threshold value 2. Here, threshold value 1 is assumed to be larger than threshold value 2. The clock signal with the AM component is shown in Fig. 29. From the fluctuation of the time waveform envelope in this drawing, the existence of the AM components is obvious. The clock signal clipped by the clipping means is shown in Fig. 30. Since the time waveform shows a constant envelope, the removal of the AM components can be confirmed.

Examples of the first embodiment of the present invention are described below.

Fig. 31 shows an example of structure in the probability estimating apparatus for peak-to-peak clock skews used in the embodiment of the present invention. The probability estimating apparatus for peak-to-peak clock skews 100 is comprised of a clock skew estimator 101 for estimating the clock skew sequences between a plurality of clock signals under test, and a probability estimator 102 for determining and outputting the occurrence probability of the peak-to-peak value in the clock skews between the signals under test based on the clock skew sequences. Further, the probability estimator 102 is comprised of an RMS (root mean square) detector 103 for determining the RMS value of the supplied jitter waveforms, a memory 104 for storing predetermined

peak-to-peak values, and a probability calculator 105 for calculating the probability of the peak-to-peak jitters which exceeds the above predetermined value based on the peak-to-peak value and the RMS value. The clock skew estimator and its detailed configuration will be explained later.

Next, with use of the probability estimating apparatus for peak-to-peak clock skews 100 in the present embodiment, the operation to estimate the probability of the peak-to-peak clock skews between the plurality of signals under test that exceeds the predetermined value will be explained. Fig. 32 shows the operational procedure of the probability estimating method for peak-to-peak clock skews in the present embodiment. First, in step 201, the predetermined peak-to-peak value in the memory 104 is initialized. Next, in step 202, the clock skew estimator 101 estimates the clock skew sequences among the plurality of clock signals under test and supplies the estimated clock skew sequences to the probability estimator 102. Then, in step 203, the RMS detector 103 calculates the mean square value in the clock skew sequences supplied from the clock skew estimator 101 to determine the RMS value. Lastly, in step 204, the probability calculator 105 calculates the probability for the peak-to-peak value in the clock skews between the signals under test which exceeds the above predetermined value with use of the peak-to-peak value stored in the memory 104 and the RMS value, and the process ends. In the above step 204, the probability calculator 105 determines the probability of the peak-to-peak value in the clock

skews which exceeds the above predetermined value by using the equation (38), where the RMS value obtained from the above step 203 is # z and the peak-to-peak value stored in the memory 104 is #pp.

Alternatively, the set value for determining the probability of the peak-to-peak value in the clock skews which exceeds the predetermined value can be 2K times (K is constant) the RMS value of the clock skews. In this situation, instead of the memory 104, by providing a constant number multiplier for multiplying the RMS value a z obtained by the RMS detector 103 by 2K times, the obtained 2K # z can be input to the probability calculator 105 as #pp.

The probability estimating apparatus for peak-to-peak clock skews shown in Fig. 31 can also be structured as an apparatus for determining the probability of the peak value in the clock skews that exceeds the predetermined value. In this situation, the memory 104 stores the predetermined peak value, and the probability calculator 105 determines the probability of the peak value in the clock skews which exceeds the predetermined value by using the equation (36).

Similarly, in the probability estimating method for peak-to-peak clock skews shown in Fig. 32, by replacing the step 204 of calculating the occurrence probability of the peak-to-peak value in the clock skews between the signals under test to a

step of calculating the occurrence probability of the peak value in the clock skews, the peak value in the clock skews can be used in the procedure for determining the occurrence probability for the peak value in the clock skews that exceeds the predetermined value.

Further, when determining the probability for the peak value in the clock skews exceeding the predetermined value, this predetermined value can be K times (K is constant) the RMS value in the clock skews. Under this condition, instead of the memory 104, by providing a constant number multiplier for multiplying the RMS value u z obtained by the RMS detector 103 by K times, the obtained K # z can be input to the probability calculator means 105 as the peak value #pk.

Also, the probability estimating apparatus for peak-to-peak clock skews shown in Fig. 31 can be structured as an apparatus for determining the occurrence probability of the peak-to-peak value in the clock skews by changing the configuration of the probability estimator. Fig. 33 shows such another example of structure in the probability estimating apparatus for peak-to-peak clock skews used in the present embodiment. This probability estimating apparatus 300 for peak-to-peak clock skews is similar to the probability estimating apparatus for peak-to-peak clock skews shown in Fig. 31 except for the probability estimator 102 being replaced by a probability estimating apparatus 102a, where it is comprised of anRMS detector

103 for determining the RMS value of the supplied clock skew sequences, a peak-to-peak detector 301 for determining the peak-to-peak value based on the supplied clock skew sequences, and a probability calculator 105 for calculating the probability of the clock skews between the signals under test which exceeds the above peak-to-peak value based on the peak-to-peak value and the RMS value (for simplicity of explanation, descriptions for the duplicated parts are omitted).

Next, with the use of the probability estimating apparatus for peak-to-peak clock skews 300 in the present embodiment, the operation for estimating the probability of the clock skews between the signals under test that exceeds the peak-to-peak value will be explained. Fig. 34 shows such an operational procedure of the probability estimating method for peak-to-peak clock skews in the present embodiment. This probability estimating method for peak-to-peak clock skews is similar to the probability estimating method for peak-to-peak clock skews shown in Fig. 32 except for the removal of the step 201 for initializing the predetermined peak-to-peak value in the memory, and the addition of a step 401 in which, after the RMS value in the clock skew sequences between the signals under test is determined, the above noted peak-to-peak detector 301 calculates the difference between the maximum and minimum values in the clock skew sequences to determine the peak-to-peak value (for simplicity of explanation, descriptions for the duplicated parts are omitted). Here, in step 204, the probability calculator

105 determines the probability for the clock skews exceeding the peak-to-peak value by using the equation (38), where the RMS value obtained from the step 203 is # z and the peak-to-peak value also obtained from the above step 203 is #pp. Further, the step 203 for determining the RMS value in the above clock skew sequences and the step 401 for determining the peak-to-peak value are independent from one another, and can conduct the procedure in parallel even if the orders are changed.

Also, the probability estimating apparatus for peak-to-peak clock skews shown in Fig. 33 can be structured as an apparatus for determining the occurrence probability of the peak value in the clock skews. In this situation, the probability calculator 105 determines the probability for the peak value in the clock skews that exceeds the above predetermined value by using the equation (36), and the peak-to-peak detector 301 determines the maximum or minimum value in the clock skews.

Similarly, in the probability estimating method for peak-to-peak clock skews shown in Fig. 34, by replacing the step 204 of calculating the occurrence probability of the peak-to-peak value in the clock skews between the signals under test with a step of calculating the occurrence probability of the peak value in the clock skews, and replacing the step 401 for determining the peak-to-peak value in the clock skews with a step for calculating the maximum or minimum value in the clock skew sequences to determine the peak value, the procedure can

determine the occurrence probability of the peak value in those clock Skews.

Fig. 35 shows an example of structure in the clock skew estimator used in the embodiment of the present invention. This clock skew estimator 500 is comprised of timing j itter estimators 501a and 501b for estimating the timing jitter sequences in the clock signals under test, a deterministic clock skew estimator 502 for estimating the timing errors between the ideal clock edges of the clock signals under test to determine the deterministic components of the clock skews, and a clock skew calculator 503 for receiving the above timing jitter sequences to calculate their timing differences and outputting the clock skew sequences. In addition to the timing jitter sequences, the timing jitter estimators 501a and 501b also estimate the initial phase angles of the signals under test, and output them to the deterministic clock skew estimator 502. The detailed <BR> structure of the timing j itter estimator will be explained later.

Next, with the use of the clock skew estimator 500 in the present embodiment, the operation for conducting the clock skew estimation between the signals under test will be explained. Fig. 36 shows the procedure for the clock skew estimating method in the present embodiment. First, in step 601, the timing jitter estimators 501a and 501b estimate the initial phase angles of the signals under test and the timing jitter sequences. Next, in step 602, the deterministic clock skew estimator 502 calculates

the difference between the initial phase angles of those signals under test received from the timing jitter estimators 501a and 501b to estimate the deterministic components of the clock skews between the signals under test. Lastly, in step 603, the clock skew calculator 503 estimates the clock skew sequences between the signals under test based on the timing jitter sequences obtained from the timing jitter estimators 501a and 501b and the deterministic components of the clock skews obtained from the deterministic clock skew estimator 502, and the process ends.

In the above step 602, in which the deterministic components of those clock skews between the signals under test are estimated, the deterministic clock skew estimator 502 finds the deterministic components in the clock skews between the signals under test by using the equation (16). Also, in the above step 602, the deterministic clock skew estimator 502 can determine the absolute value of the equation (16) when necessary. Further, in the above step 603, where the clock skew sequences between the signals under test are estimated, the clock skew calculator 503 determines the clock skew sequences between the signals under test by using the equation (6). Moreover, the step 601, in which the initial phase angles of the signals under test and timing jitter sequences are estimated, can be replaced with a procedure shown in Fig. 44. In addition, the step 602, in which the deterministic components of the clock skews between the signals under test are estimated, can be replaced with a procedure shown in Fig. 38.

The clock skew estimator shown in Fig. 35 can be structured as an apparatus for estimating only the random components of the clock skews. In this situation, the deterministic clock skew estimator 502 for determining the deterministic components of the clock skews can be abbreviated. Similarly, the clock skew estimating method shown in Fig. 36 can estimate only the random components of the clock skews. In this arrangement, the step 602 of estimating the deterministic components of the clock skews from the initial phase angles of the signals under test can be omitted.

The above deterministic clock skew estimator 502 can be implemented by the configuration shown in Fig. 37. Fig. 37 shows an example of structure in the deterministic clock skew estimator used in the embodiment of the present invention. This deterministic clock skew estimator 700 is comprised of an offset estimator 701 for receiving the initial phase angles and the timing jitter sequences of the signals under test for estimating the offsets between the clock edges corresponding to the signals under test based on the timing jitter sequences, and a deterministic clock skew calculator 702 for calculating the deterministic components of the clock skews between the signals under test based on the above noted initial phase angles and the offsets of the clock edges estimated by the offset estimator 701.

Next, with the use of the deterministic clock skew

estimator 700 in the present embodiment, the operation for estimating the deterministic components of the clock skews between the signals under test will be explained. Fig. 38 shows the procedure for the deterministic clock skew estimating method in the present embodiment. First, in step 801, the offset estimator 701 determines the offset position where the correlation coefficient between the timing jitter sequences becomes the largest based on the timing jitter sequences of the signals under test, thereby estimating the offset noffset between the corresponding clock edges. Then, in step 802, the deterministic clock skew calculator 702 calculates the deterministic components of the clock skews between the signals under test based on the initial phase angles and the offsets in the clock edges estimated by the offset estimator 701, and the process ends. In the step 802, where the deterministic components of the clock skews between the signals under test are calculated, the deterministic clock skew calculator 702 obtains the deterministic components of those clock skews between the signals under test by using the equation (21).

Fig. 39 shows another structural example of the clock skew estimator used in the embodiment of the present invention. This clock skew estimator 900 is comprised of timing jitter estimators 501a, 501b, 501c, and 501d for estimating the timing jitter sequences # #j[n], # #g [n], A ¢ k [n], and A 0 9 [n] in the clock signals xj (t), xg (t) Xk (t), and xg (t) under test respectively, deterministic clock skew estimators 502a and 502b for estimating

the timing errors between the ideal clock edges of the clock signals xj (t), xg (t) under test as well as clock signals xk (t), xg (t) under test to estimate the deterministic components T gtiskewand tg'Skew of the clock skews, clock skew calculators 503a and 503b for receiving the above timing jitter sequences and calculating their timing differences therebetween to output the clock skew sequences Tgiskew [n] and Tg,k Skew [n], and another clock skew calculator 901 for receiving the above clock skew sequences from the clock skew calculators 503a and 503b to determine the difference between the clock skew sequences and estimate the clock skew sequence TskewEn]. For simplicity of explanation, description for the duplicated parts is omitted.

Next, with the use of the clock skew estimator 900 in the present embodiment, the operation for conducting the clock skew estimation among the signals under test will be explained. Fig.

40 shows the procedure of the clock skew estimation method in the present embodiment. First, in step 1001, timing jitter estimators 501a and 501b estimate the initial phase angles and and #0g of the signals xj (t), xg (t) under test and timing jitter sequences A fi [n] and A g [n]. Then, in step 1002, the deterministic clock skew estimator 502a calculates the difference between the initial phase angles (io and zozo of the signals under test obtained from the timing jitter estimators 501a and 501b to estimate the deterministic component #g,j Skew of the clock skews between the signals under test. Then, in step 1003, the clock skew calculator 503a estimates the clock

skew sequence T'skewEn] between the signals under test based on the timing jitter sequences A ßi [n] and A ßg [n] obtained from the above timing jitter estimators 501a and 501b and based on the deterministic component # g,jSkew of the clock skews obtained from the deterministic clock skew estimator 502a. Next, in step 1004, the timing jitter estimators 501c and 501d estimate the initial phase angles ##0k and ##0g of the signals Xk (t), xg (t) under test and the timing jitter sequences A k [n] and A g [n].

Next, in step 1005, the deterministic clock skew estimator 502b calculates the difference between the initial phase angles ko and go of the signals under test obtained from the timing jitter estimators 501c and 501d to estimate the deterministic component #g,k Skew of the clock skews between the signals under test. Then, in step 1006, the clock skew calculator 503b estimates the clock skew sequence Tg'kSkew [n] between the signals under test based on the timing jitter sequences # #k [n] and A g [n] obtained from the above timing jitter estimators 501c and 501d and based on the deterministic component #g,j Skew of the clock skews obtained from the deterministic clock skew estimator 502b.

Lastly, in step 1007, the clock skew calculator 901 estimates theclockskewsequenceTitkskew [n] betweenthesignalsxj (t), xk (t) under test based on the clock skew sequences Tg,j Skew[n] and Tg'kskew [n] obtained from the above clock skew calculators 503a and 503b, and the process ends. In the above step 1007, in which the clock skew sequences between the signals xj (t), xk (t) under test are estimated, the clock skew calculator 901 determines the clock skew sequences between the signals under test by using

the equation (28). In order to simplify the explanation, descriptions for other duplicated parts are omitted.

The clock skew estimator shown in Fig. 39 can be structured as an apparatus for estimating only the random components of the clock skew. Under such a construction, the deterministic clock skew estimators 502a and 502b for determining the deterministic components of the clock skews can be eliminated.

Similarly, the clock skew estimating method shown in Fig. 40 can estimate only the random components of the clock skew. Under such a procedure, the steps 1002 and 1005 for estimating the deterministic components of the clock skews from the initial phase angles of the signals under test can be eliminated.

Fig. 41 shows another structural example of the clock skew estimator used in the embodiment of the present invention. This clock skew estimator 1100 is similar to the clock skew estimator shown in Fig. 35 except for the inclusion of a frequency multiplier 1101 for receiving the timing jitter sequences estimated by the timing jitter estimator 501b to copy the timing jitter sequences by, for example, M-1 times, and to determine the timing jitter sequences when the signals under test are multiplied by M times (in order to simplify the explanation, descriptions for the duplicated parts are omitted).

Next, with the use of the clock skew estimator 1100 in the present embodiment, the operation for conducting the clock

skew estimation in the signals under test will be explained. Fig. 42 shows another procedure of the clock skew estimation method in the present embodiment. This clock skew estimation method is similar to the clock skew estimation method shown in Fig. 36 except for having step 1201 in which, after determining the timing jitter sequences, the frequency multiplier 1101 copies the timing jitter sequences estimated by the timing jitter estimator 510b by, for example, M-1 times, to determine the timing jitter sequences when the signals under test are multiplied by M times (in order to simplify the explanation, descriptions for duplicated parts are omitted). Under this situation, in the above step 602 for estimating the deterministic components of the clock skews between the signals under test, the deterministic clock skew estimator 502 obtains the deterministic components of the clock skews between the signals under tested by using the equation (25). Also, in the above noted step 603 in which the clock skew sequences between the signals under test are estimated, the clock skew calculator 503 determines the clock skew sequences between the signals under test by using the equation (24).

The clock skew estimator shown in Fig. 41 can be structured as an apparatus for estimating only the random components of the clock skews. In such a situation, the deterministic clock skew estimator 502, which determines the deterministic components of the clock skews, can be eliminated. Similarly, the clock skew estimating method shown in Fig. 42 can also estimate

only the random components of the clock skews. At this time, the step 602 in which the deterministic components of the clock skews can be estimated from the initial phase angles of the signals under test, can be omitted.

Further, the above frequency multiplier can be incorporated into the clock skew estimator shown Fig. 39. In such a construction, the frequency multiplier is inserted directly at the output of the timing jitter estimators 501b and 501d. Similarly, the step for multiplying the frequency can be added to the clock skew estimating method shown in Fig. 40.

At this time, the step to multiply the frequency is inserted after the steps 1001 and 1004 in which the timing jitters are estimated.

Fig. 43 shows a structural example of the timing jitter estimator used in the clock skew estimator of the present embodiment. The timing jitter estimator 1300 is comprised of an analytic signal transformer 1301 for transforming the signals under test into band-limited complex analytic signals, an instantaneous phase estimator 1302 for determining the instantaneous phase of the analytic signals transformed by the analytic signal transformer 1301, a linear trend remover 1303 for removing the linear phase from the instantaneous phase estimated by the instantaneous phase estimator 1302 to obtain the instantaneous phase noise, and a zero-crossing resampler 1304 for receiving the instantaneous phase noise estimated by

the linear trend remover 1303 to resample only the instantaneous phase noise data closest to the real zero-crossing timings based on the above analytic signals and to output the timing jitter sequences. The analytic signal transformer 1301 can use the structures shown in Figs. 45,47, and 49. Also, the analytic signal transformer 1301 can be structured to freely change the pass band of the signals. Further, the linear trend remover 1303 determines the initial phase angles of the signals under test as well as the instantaneous phase noise, and outputs them to the deterministic clock skew estimator.

Next, with the use of the timing jitter estimator 1300 in the present embodiment, the operation for estimating the initial phase angles as well as the timing jitter sequences in the signals under test will be explained. Fig. 44 shows the procedure of the timing jitter estimation method in the present embodiment. First, in step 1401, the analytic signal transformer 1301 transforms the signals under test into analytic signals, where the predetermined frequency components are selectively passed there through. Next, in step 1402, the instantaneous phase estimator 1302 estimates the instantaneous phase of the signals under test by using the analytic signals obtained from the analytic signal transformer 1301. Then, in step 1403, the linear trend remover 1303 estimates the linear phase corresponding to an ideal clock signal based on the instantaneous phase estimated by the instantaneous phase estimator 1302, and determines the initial phase angles of the signals under test.

Then, in step 1404, the linear trend remover 1303 removes the linear phase from the instantaneous phase to estimate the instantaneous phase noise. Lastly, in step 1405, the zero-crossing resampler 1304 resamples only the instantaneous phase noise closest to the real zero-crossing timings in the above analytic signals based on the above instantaneous phase noise estimated by the linear trend remover 1303 to estimate the timing jitter sequences, and the process ends. The step 1401 for transforming the signals under test into the analytic signals can be conducted in the procedures shown in Figs. 46, 48, and 50.

Fig. 45 shows a structural example of the analytic signal transformer used in the timing jitter estimator 1300 of the present embodiment. The analytic signal transformer 1500 is comprised of a band-pass filter 1501 for extracting only the components closest to the fundamental frequency of the signals under test to band-limit the signals under test, and a Hilbert transformer 1502 for Hilbert-transforming the output signals from the band-pass filter 1501 to generate Hilbert transformed pairs.

The band-pass filter 1501 can be an analog filter or a digital filter, or can be created by using a digital signal filter such as a FFT. Further, the band-pass filter 1501 can be structured to freely change the pass band of the signals.

Next, with the use of the analytic signal transformer 1500 in the present embodiment, the operation for transforming the

signals under test into band-limited analytic signals will be explained. Fig. 46 shows the procedure for the signal transformation method of the present embodiment. First, in step 1601, the band-pass filter 1501 removes only the components closest to the fundamental frequency from the signals under test to band-limit those signals under test. Then, in step 1602, the Hilbert transformer 1502 applies the Hilbert transformation to the band-limited signals under test, and generates Hilbert transformed pairs in the input signals corresponding to the analytic signals of imaginary part. Lastly, in step 1603, the analytic signal transformer 1500 outputs the output signals from the band-pass filter 1501 as a real part of the analytic signals and the output signals from the Hilbert transformer 1502 as an imaginary part of the analytic signals, then the process ends.

Fig. 47 shows another structural example of the analytic signal transformer used in the timing jitter estimator 1300 of the present embodiment. The analytic signal transformer 1700 is comprised of a time domain to frequency domain transformer 1701 for transforming the signals under test into both-side spectra signals of a frequency domain, a bandwidth limiter 1702 for removing only the components closest to the positive fundamental frequency from the both-side spectra signals in the frequency domain, and a frequency domain to time domain transformer 1703 for transforming the outputs of the above bandwidth limiter 1702 back into the time domain signals. The time domain to frequency domain transformer 1701 and the frequency

domain to time domain transformer 1703 can be implemented by a FFT and an inverse FFT, respectively. Also, the bandwidth limiter 1702 can be structured to freely change the pass band of the signals.

Next, with the use of the analytic signal transformer 1700 in the present embodiment, the operation for transforming the signals under test into band-limited analytic signals will be explained. Fig. 48 shows another procedure of the signal transformation method in the present embodiment. First, in step 1801, the time domain to frequency domain transformer 1701 applies the FFT to the signals under test to transform the time domain signals into the both-side spectra signals in the frequency domain.

Then, in step 1802, the bandwidth limiter 1702 replaces the negative frequency components with zero for the transformed both-side spectra signals of the frequency domain. Then, in step 1803, the bandwidth limiter 1702 retains only the components closest to the fundamental frequency of the signals under test in the one-side spectra signals, where the negative frequency components are replaced with zero, to band-limit the signals in the frequency domain. Lastly, in step 1804, the frequency domain to time domain transformer 1703 applies an inverse FFT to the band-limited one-side spectra signals to transform the frequency domain signals into analytic signals in the time domain, and then the process ends. The order of the above steps 1802 and 1803 can be switched to one another, i. e., after the step of retaining only the components closest to the fundamental

Frequency of the signals under test to replace the remaining frequency components by zero and band-limit those signals of a frequency domain, the step for replacing the negative frequency components in the both-side spectra signals with zero can be performed.

Fig. 49 shows a further example of structure in the analytic signal transformer used in the timing jitter estimator 1300 of the present embodiment. The analytic signal transformer 1900 is comprised of a buffer memory 1901 for storing the signals under test, a signal selector) 1902 for sequentially extracting the signals from the buffer memory 1901 while overlapping the part of the extracted signals with the ones previously extracted, a window function multiplier 1903 for multiplying a window function to each extracted part of the signal, a time domain to frequency domain transformer 1904 for transforming each part of the signal multiplied by the window function into both-side spectra signals in the frequency domain, a bandwidth limiter 1905 for removing only the components closest to the positive fundamental frequency of the signals under test from the both-side spectra signals transformed into the frequency domain, a frequency domain to time domain transformer 1906 for transforming the outputs of the bandwidth limiter 1905 back into the time domain signals, and an inverse window function multiplier 1907 for multiplying the above inverse window function to the signals transformed into the time domain to obtain the band-limited analytic signals. The time domain to frequency domain

transformer 1904 and the frequency domain to time domain transformer 1906 can be implemented by using the FFT and inverse FFT, respectively. Further, the bandwidth limiter 1905 can be structured to freely change the pass band of the signals.

Next, with the use of the analytic signal transformer 1900 in the present embodiment, the operation for transforming the signals under test into band-limited analytic signals will be explained. Fig. 50 shows a further procedure of the signal transformation method of the present embodiment. First, in step 2001, the signals under test are stored in the buffer memory 1901. Then, in step 2002, the signal selector 1902 extracts part of the signals stored in the buffer memory 1901. Then, in step 2003, the window function multiplier 1903 multiplies the window function to the extracted parts of the signal. Next, in step 2004, the time domain to frequency domain transformer 1904 applies the FFT process to the signal parts multiplied by the window function to transform the time domain signals into the both-side spectra signals in the frequency domain. Then, in step 2005, the bandwidth limiter 1905 replaces the negative frequency components with zero for the transformed both-side spectra signals in the frequency domain. Next, in step 2006, the bandwidth limiter 1905 retains only the components closest to the fundamental frequency of the signals under test in the one-side spectra signals, where the negative frequency components are replaced with zero, to replace the remaining frequency components with zero and band-limit the frequency

domain signals. Then, in step 2007, the frequency domain to time domain transformer 1906 applies the inverse FFT to the band-limited one-side spectra signals of the frequency domain to transform the frequency domain signals into the time domain signals. Then, in step 2008, the inverse window function multiplier 1907 multiplies the inverse window function produced in the step 2003 to the inverse transformed time domain signals to determine the band-limited analytic signals. Lastly, instep <BR> 2009, inspectionsareperformedtoseeifthereisanyunprocessed data existing in the buffer memory, where if it does exist, the signal selector 1902 in step 2010 repeats the steps 2003-2009 after sequentially taking out signals from the buffer memory while overlapping the part of those signals with the ones previously extracted, and if it does not exist, the process will end. The order of the above steps 2005 and 2006 can be switched to one another, i. e., after the step of retaining only the components closest to the fundamental frequency of the signals under test by replacing the remaining frequency components with zero and band-limit those frequency domain signals, the step for replacing the negative frequency components with the both-side spectra signals with zero can be performed.

Fig. 51 shows a further structural example of the clock skew estimator used in the embodiment of the present invention.

This clock skew estimator 2100 is similar to the clock skew estimator shown in Fig. 35 except for the inclusion of AD converters 2101a and 2101b for digitizing the analog signals

under test to be converted into digital signals (in order to simplify the explanation, descriptions for duplicated parts are omitted). For the above AD converters, a high speed AD transformer, digitizer, or digital sampling oscilloscope is preferably used.

Next, with the use of the clock skew estimator 2100 in the present embodiment, the operation of the clock skew measurement for the signals under test will be explained. Fig.

52 shows such a procedure of the clock skew estimation method in the present embodiment. This clock skew estimating method is similar to the clock skew estimating method shown in Fig.

36 except for the inclusion of step 2201 in which, prior to the start of the procedure, the AD converters 2101a and 2101b sample (digitize) the analog signals under test, which are subject to the clock skew measurement, and convert them into the digital signals (in order to simplify the explanation, descriptions for the duplicated parts are omitted).

The above AD converters can be incorporated in the clock skew estimator 1100'with the frequency multiplier show in Fig.

41. In this situation, the procedure of the clock Skew estimation method shown in Fig. 42 additionally includes a step where, prior to the start of the procedure, the AD converters sample (digitize) the analog signals under test, which are subject to the clock skew measurement, and convert them into the digital signals.

Further, the above AD transformers can be incorporated in the clock skew estimator 900 shown in Fig. 39. Similarly, the step for sampling (digitizing) the signals under test to transform them into the digital signals can be incorporated into the clock skew estimating method shown in Fig. 40.

Fig. 53 shows a further structural example of the clock skew estimator used in the embodiment of the present invention.

This clock skew estimator 2300 is similar to the clock skew estimator shown in Fig. 35 except for the inclusion of waveform clippers (wave form clipping means) 2301a and 2301b for removing the AM components in the signals (for simplicity of explanation, descriptions for the duplicated parts are omitted).

Next, with the use of the clock skew estimator 2300 in the present embodiment, the operation for the clock skew measurement of the signals under test will be explained. Fig. 54 shows another procedure of the clock skew estimating method of the present embodiment. This clock skew estimating method is similar to the jitter measurement method shown in Fig. 36 except for the inclusion of step 2401, where the waveform clippers 2301a and 2301b remove the AM components from the signals under test prior to the procedure (in order to shorten the explanation, descriptions for the duplicated parts are omitted).

The above waveform clippers can be incorporated in the clock skew estimator 1100 with the frequency multiplier shown

in Fig. 41. In this arrangement, the procedure for the clock skew estimation method shown in Fig. 42 is provided with a step where the waveform clippers remove the AM components from the signals under test prior to the start of the procedure.

Also, the above waveform clippers can be incorporated into the clock skew estimator 900 shown in Fig. 39. Similarly, the step where the waveform clipper removes the AM components of the signals under test can be incorporated in the clock skew estimating method shown in Fig. 40.

Fig. 55 shows a further structural example of the timing j itter estimator used in the embodiment of the present invention.

This timing jitter estimator 2500 is similar to the timing j itter estimator shown in Fig. 43 except for the inclusion of the low frequency component remover 2501 which receives the instantaneous phase noise and removes the low frequency components from the above instantaneous phase noise and outputs them to the zero-crossing resampler (in order to simplify the explanation, descriptions for the duplicated parts are omitted).

Next, with the use of the timing jitter estimator 2500 in the present embodiment, the operation for estimating the initial phase angles of the signals under test and timing jitter sequences will be explained. Fig. 56 shows such a procedure for the timing j itter estimation method of the present embodiment.

This timing jitter estimating method is similar to the timing

j itter estimating method shown in Fig. 44 except for the inclusion of step 2601 in which, after estimating the instantaneous phase noise, the low frequency component remover 2501 removes the low frequency components from the instantaneous phase noise (for simplicity of explanation, descriptions for the duplicated parts are omitted).

According to the probability estimation apparatus for peak-to-peak clock skews as Well as the probability estimation method for peak-to-peak clock skews of the present embodiment, by assuming the linear clock skews to be Gaussian-based random processes and determining the Rayleigh probability density distribution function of the peak-to-peak value in the clock skews, the probability estimation for the peak-to-peak value in the clock skews that exceeds the predetermined value, for which no traditionally effective methods existed, canbe achieved, resulting in the dramatic improvement in the effectiveness of the product reliability analysis.

Furthermore, according to the probability estimation apparatus for peak-to-peak clock skews as well as the probability estimation method for peak-to-peak clock skews of the present embodiment, by measuring the peak-to-peak value in the clock skews and calculating the occurrence probability thereof, the occurrence probability of that peak-to-peak value can be checked whether it can satisfy the product specifications or not, thereby dramatically improving the effectiveness of the reliability

analysis of products which was not possible in the conventional technology.

In the following, examples of the second embodiment of the present invention are described.

Fig. 57 shows a functional configuration of an example of a clock skew measurement apparatus according to the present embodiment. This clock skew measurement apparatus 3100 <BR> comprises timing j itter estimators 3101a and 3101b for estimating timing jitter sequences A 4) j [n] and A ßk [n] of clock signals under measurement xj (t) and Xk (t), respectively, a deterministic clock skew estimator 3102 for estimating a timing error between ideal clock edges of the respective clock signals under measurement and forestimating adeterministiccomponent rSkewitk of clock skew, a clock skew estimator 3103 to which the timing jittersequences A fi [n] and A ok [n] are inputted for calculating a timing difference sequence between those timing jitter sequences A i [n] and A ok [n] to output a clock skew sequence TSkewj,k[n], and a clock skew detector 3104 for obtaining clock skew values between the clock signals under measurement from the clock skew sequence. In addition, the clock skew detector 3104 comprises a peak-to-peak detector 3105 for obtaining a difference between the maximum value and the minimum value of the clock skew sequence Tskew'k [n], an RMS detector 3106 for calculating an RMS value as a standard deviation of the clock skew sequence, and a histogram estimator 3107 for obtaining a histogram of the clock skew sequence. The timing jitter

estimators 3101a and 3101b estimate initial phase angles oi and ßok of the clock signals under measurement xj (t) and xk (t), respectively in addition to the timing jitter sequences A 0 i [n] and A ¢ k [n], and output the estimated initial phase angles to the deterministic clock skew estimator 3102. A specific configuration of the timing jitter estimators 3101a and 3101b will be described later.

Next, the operation in the case where a clock skew between the clock signals under measurement xj (t) and xk (t) is measured using the clock skewmeasurement apparatus 3100 of this embodiment will be described. Fig. 58 shows a processing procedure of an example of the clock skew measurement method according to the present embodiment. First, in step 3201, initial phase angles ßoi and okl and timing jitter sequences A fi [n] and A k [n] of the respective clock signals under measurement xj (t) and (t) are estimated by the timing jitter estimators 3101a and 3101b, respectively. Next, in step 3202, a difference between the initial phase angles #0j and #0k of the respective clock signals under measurement is calculated by the deterministic clock skew estimator 3102 to estimate a deterministic component # Skewj,k of clock skew between the clock signals under measurement. Next, in step 3203, a clock skew sequence TSkew''k [n] between the clock signals under measurement xj (t) and xk (t) is estimated by the clock skew estimator 3103 from the timing jitter sequences A ßi [n] and ##k [n], and the deterministic component # Skewj,k of clock skew. Finally, in step 3204, a clock skew value between

the clock signals under measurement xj (t) and xk (t) is obtained by the clock skew detector 3104 from the estimated clock skew sequence Skew, and the process ends.

In the step 3202 for estimating a deterministic component of clock skew between the clock signals under measurement, the deterministic clock skew estimator 3102 obtains a deterministic component of clock skew between the clock signals under measurement using the equation (16). In addition, in the step 3202, the deterministic clock skew estimator 3102 may obtain, if necessary, an absolute value of the equation (16). In addition, in the step 3203 for estimating a clock skew sequence between the clock signals under measurement, the clock skew estimator 3103 obtains a clock skew sequence TSkew'k [n] between the clock signals under measurement using the equation (6). In the step 3204 for obtaining a clock skew value between the clock signals under measurement, the peak-to-peak detector 3105 obtains a peak-to-peak value of clock skew using the equation (23), the RMS detector 3106 obtains an RMS value of clock skew using the equation (22), and the histogram estimator 3107 obtains a histogram from the clock skew sequence. Alternatively, an RMS value and/or the peak-to-peak value may be obtained from only the second term of the equation (6). In addition, the step 3201 for estimating initial phase angles and timing jitter sequences of the clock signals under measurement may be replaced by the processing procedure shown in Fig. 64. Furthermore, the step 3202 for estimating a deterministic component of clock skew

between the clock signals under measurement may be replaced by the processing procedure shown in Fig. 60.

The clock skew measurement apparatus shown in Fig. 57 can also be modified as an apparatus for estimating only random component of clock skew. In this case, the deterministic clock skew estimator 3102 for obtaining a deterministic component of clock skew is omitted. Similarly, the clock skew measurement method shown in Fig. 58 can also be modified as a method of estimating only random component of clock skew. In this case, the step 3202 for estimating a deterministic component of clock skew from initial phase angles of the clock signals under measurement is omitted.

The deterministic clock skew estimator 3102 shown in Fig.

57 estimates a deterministic component of. clock skew from a difference between initial phase angles #0j and #0k of the respective clock signals under measurement. However, the deterministic clock skew estimator can also be materialized by the configuration shown in Fig. 59. That is, this deterministic clock skew estimator 3102 to which initial phase angles #0j and ok and timing jitter sequences A q5J [n] and l\ k [n] of the respective clock signals under measurement xj (t) and xk (t) are inputted comprises an offset estimator 3301 for estimating an offset lloffset between corresponding clock edges of the respective clock signals under measurement from those timing jitter sequences A ¢ i [n] and l\ ¢ k [n], and a deterministic clock skew

calculator 3302 for calculating a deterministic component z Skewj,k of clock skew between the clock signals under measurement from the initial phase angles foi and ok and the offset noffset between the corresponding clock edges estimated by the offset estimator 3301.

The operation in the case where a deterministic component of clock skew between the clock signals under measurement is estimated using this deterministic clock skew estimator 3102 will be described. Fig. 60 shows the processing procedure.

First, in step 3401, from the inputted timing jitter sequences [n] and A ¢ k [n] of the clock signals under measurement, an offset position, at which correlation function between those timing jitter sequences shows the largest value, is obtained by the offset estimator 3301 to estimate an offset noffset between the corresponding clock edges. Next, in step 3402, a deterministic component rSkew3k of clock skew between the clock signals under measurement xj (t) and xk (t) is calculated by the deterministic clock skew calculator 3302 from the inputted initial phase angles oi and fok and the offset noffset between the corresponding clock edges, and then the process ends. In the step 3402 for calculating a deterministic component of clock skew between the clock signals under measurement, the deterministic clock skew calculator 3302 obtains a deterministic component of clock skew between the clock signals under measurement using the equation (21). As indicated by dashed lines in Fig. 59, instantaneous phase noises A Oj [t] and A 0

k [t] to be explained in Fig. 63 may be inputted to the offset <BR> <BR> <BR> <BR> <BR> estimator 3301 to obtain an offset position at which a correlative value between those ##j[t] and ##k [t] becomes the largest value for estimating an offset offset.

Fig. 61 shows a functional configuration of another example of the clock skew measurement apparatus according to the present embodiment. This clock, skew measurement apparatus 3500 comprises timing jitter estimators 3101a, 3101b, 3101c, and 3101d for respectively estimating timing jitter sequences A i [n], ##g[n], ##k [n], and A g [n] of respective clock signals under measurement xj (t), xg (t), Xk (t), and xg (t), deterministic clock skew estimators 3102a and 3102b for respectively estimating a timing error Etgti between ideal clock edges of the clock signals under measurement xj (t) and xg (t) and <BR> <BR> <BR> <BR> atimingerrorEtgibetween idealclockedgesofthe clocksignals under measurement xk (t) and xg (t) to respectively estimate deterministic components #Skewg,j and # Skewg,k using those timing errors Et5'i and Etgk, clock skew estimators 3103a and 3103b to which the timing j itter sequences ##j[n], ##g[n], and ##k [n], A 09 [n] are respectively inputted for calculating timing difference sequences between the two inputs at each clock skew estimator respectively to output clock skew sequences Skews [n] and TskewM respectively, a clock skew estimator 501 to which those clock skew sequences TSkewg,j [n] and TSkewg,k[n] are inputted for obtaining a difference between those clock skew sequences to estimate a clock skew sequence Tskew''k [n], and a clock skew

detector 3104 for obtaining a clock skew value between the clock signals under measurement from the clock skew sequence obtained by the clock skew estimator 3501. For simplicity, the explanation of portions duplicated with those in Fig. 57 is omitted.

Next, the operation in the case where a clock skew between the clock signals under measurement is measured using the clock skew measurement apparatus 3500 according to the present embodiment will be described. Fig. 62 shows a processing procedure of the clock skew measurement method according to the present embodiment. First, in step 3601, initial phase angles oi and 0 0, and timing jitter sequences ##j[n] and ##g [n] of the respective clock signals under measurement xj (t) and xg (t) are estimated by the timing jitter estimators 3101a and 3101b, respectively. Next, in step 3602, a difference between the initial phase angles ßoi and og of the clock signals under measurement calculated by the deterministic clock skew estimator 3102a to estimate a deterministic component rskewgiofclockskew between the clock signals under measurement. Next, in step 3603, a clock skew sequence Tskew' [n] between the clock signals under measurement is estimated by the clock skew estimator 3103a from the timing jitter sequences A 0 i [n] and A g [n], and the deterministic component rSkewgti of clock skew.

Next, in step 3604, initial phase angles okand Og, and timing jitter sequences ##k[n] and # #g[n] of the respective

clock signals under measurement xk (t) and xg (t) are estimated by the timing jitter estimators 3101c and 3101d, respectively.

Next, in step 3605, a difference between the initial phase angles ok and sog ouf the clock signal under measurement obtained in the step 3604 is calculated by the deterministic clock skew estimator 3102b to estimate a deterministic component Skew g, k of clock skew between the clock signals under measurement. Next, in step 3606, a clock skew sequence Tskew' [n] between the clock signals under measurement is estimated by the clock skew estimator 3103b from the timing jitter sequences ##k[n] and ##g [n] obtained in the step 3604 and the deterministic component z Skewg,k of clock skew obtained in the step 3605. Next, in step 3607, a clock skew sequence TSkewj,k[n] between the clock signals under measurement xj (t) and xk (t) is estimated by the clock skew estimator 3501 from the clock skew sequences Tgkew' [n] and Tskew [n] respectively obtained in the steps 3603 and 3606.

Finally, in step 3608, a clock skew value between the clock signals under measurement xj (t) and xk (t) is obtained by the clock skew detector 3104 from the clock skew sequence Tskewilk [n] estimated in the step 3607, and the process ends. In the step 3607 for estimating the clock skew sequence between the clock signals under measurement xj (t) and xk (t), the clock skew estimator 3501 obtains a clock skew sequence between the clock signals under measurement using the equation (28). The process sequence of the steps 3601-3603 and the steps 3604-3606 may be exchanged.

For simplicity, the explanation of portions duplicated with those in Fig. 58 is omitted.

The clock skew measurement apparatus shown in Fig. 61 may also be configured as an apparatus for estimating only random component of clock skew. In this case, the deterministic clock skew estimators 3102a and 3102b for obtaining the deterministic components of clock skew are omitted. Similarly, the clock skew measurement method shown in Fig. 62 may also be modified as a method of estimating only random component of clock skew. In this case, the steps 3602 and 3605 for estimating deterministic components of clock skew from the initial phase angles of the clock signals under measurement are omitted.

As indicated by dashed lines in Fig. 57, a timing jitter sequence estimated by one of the timing jitter estimators 3101a and 3101b, i. e., the timing jitter sequence A fk [n] estimated by the timing jitter estimator 3101b in the case of Fig. 57 may be copied (M-l) times by the frequency multiplier 3701 to obtain <BR> <BR> <BR> <BR> <BR> a timing j itter sequence that is to be obtained when the frequency of the clock signal under measurement xk (t) is multiplied by M, and to supply the obtained timing jitter sequence to the clock skew estimator 3103. By such a process, in the clock distribution system previously described with reference to Fig. 8, the clock signal xk (t) in Fig. 357 corresponds to the system clock signal CLKG in Fig. 8, and the clock signal xj (t) is a signal created by multiplying the frequency of the clock signal CLKG (Xk (t)) by M. In this case, aclockskew rskewGi [n] betweentheclocksignal CLKG (Xk (t)) and the clock signal xj (t) can be obtained by the

equation (24).

Regarding the processing procedure of the clock skew measurement method in this case, as shown in Fig. 58, after timing jitter sequences are obtained in the step 3201, the timing jitter sequence estimated by the timing jitter estimator 3101b may be assigned, for example (M-1) times as indicated by dashed lines, in step 3801 by the frequency multiplier to obtain a timing j itter sequence that is to be obtained when the frequency of the clock signal under measurement is multiplied by M, and then the process may move to the step 3202. At this time, in the step 3202 for estimating a deterministic component of clock skew between the clock signals under measurement, the deterministic clock skew estimator 3102 obtains a deterministic component of clock skew between the clock signals under measurement using the equation (25). In addition, in the step 3203 for estimating a clock skew sequence between the clock signals under measurement, the clock skew estimator 3103 obtains a clock skew sequence between the clock signals under measurement using the equation (24).

Also in the case of using the frequency multiplier 3701, when the clock skew measurement apparatus is constructed as an apparatus for estimating only random component of clock skew, the deterministic clock skew estimator 3102 for obtaining a deterministic component of clock skew may be omitted. In this case, in the clock skew measurement method, the step 3202 for estimating a deterministic component of clock skew from the

initial phase angles of the clock signals under measurement may be omitted.

In addition, the frequency multiplier 3701 may also be built in the clock skew measurement apparatus shown in Fig. 61.

In this case, the frequency multiplier is inserted in series in each output side of the timing jitter estimators 3101b and 3101d. Similarly, a step of multiplying. a frequency can also be added to the clock skew measurement method shown in Fig. 62.

In this case, the step of multiplying a frequency is inserted after each of the steps 3601 and 3604 for estimating timing jitters.

Fig. 63 shows an example of configuration of each of the timing jitter estimators 3101a, 3101b, 3101c, and 3101d. This timing jitter estimator 3900 is described in, for example, "Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method by T. J. Yamaguchi, M. Soma, M. Ishida, T. Watanabe, and T. Ohmi, Proceedings of 18th IEEE VLSI Test Symposium, pp. 395-402,2000. This timing jitter estimator 3900 comprises an analytic signal transformer 3901 for transforming a clock signal under measurement into a band-limited complex analytic signal, an instantaneous phase estimator 3902 for obtaining an instantaneous phase of the analytic signal transformed by the analytic signal transformer 3901, a linear phase remover 3903 for removing a linear instantaneous phase from the instantaneous phase estimated by the instantaneous phase

estimator 3902 to obtain an instantaneous phase noise, a zero-crossing detector 3904 to which a real part of the analytic signal is inputted from the analytic signal transformer 3901 for generating sampling pulses at timings (approximated zero-crossing points) close to zero-crossing timings of the real part of the analytic signal, a zero-crossing sampler 3905 to which the instantaneous phase noise estimated by the linear phase remover 3903 is inputted for sampling the instantaneous phase noise using the sampling pulses from the zero-crossing detector 3905. The analytic signal transformer 3901 may be constructed such that a pass bandwidth of a signal can arbitrarily be changed.

In addition, the linear phase remover 3903 obtains an initial phase angle of the clock signal under measurement simultaneously with the instantaneous phase noise, and outputs the obtained initial phase angle to the deterministic clock skew estimator.

A processing procedure in this timing jitter estimator 3900 will be explained with reference to Fig. 64. In step 4001,, an inputted clock signal under measurement is transformed by the analytic signal transformer 3901 into an analytic signal whose predetermined frequency components are selectively passed.

In step 4002, an instantaneous phase of the clock signal under measurement is estimated by the instantaneous phase estimator 3902 using the analytic signal. In step 4003, a linear instantaneous phase corresponding to an ideal clock signal is estimated by the linear phase remover 3903 from the instantaneous phase to obtain an initial phase angle of the clock signal under

measurement. In step 4004, the linear instantaneous phase is removed by the linear phase remover 3903 from the instantaneous phase to estimate an instantaneous phase noise A ( i (t). At the same time, in step 4005, timings (approximated zero-crossing points) closest to zero-crossing points of a real part of the analytic signal are detected by the zero-crossing detector 3904 from the real part of the analytic signal using the previously explained zero-crossing point detection method. Finally, in step 4006, only the instantaneous phase noise data at the approximated zero-crossing points from the instantaneous phase noise are sampled by the zero-crossing sampler 3904 to estimate a timing jitter sequence A 4) j [n], and the process ends.

In the analytic signal transformer 3901 used in the timing jitter estimator 3900, for example as shown in Fig. 63, only components around a fundamental frequency are extracted by a band-pass filter 1101 from the clock signal under measurement to band-limit the clock signal under measurement. In addition, the band-limited clock signal under measurement is inputted to a Hilbert transformer 4102 to Hilbert-transform this signal, and an output of the band-pass filter 4101 is outputted as a real part of the analytic signal. An output of the Hilbert transformer 4102 is outputted as an imaginary part of the analytic signal. The band-pass filter 4101 maybe either an analog filter or a digital filter, or may be implemented using a digital signal process such as FFT or the like. In addition, the band-pass filter 4101 may be constructed such that the pass bandwidth of

the signal can arbitrarily be changed.

Fig. 65 shows another configuration example of the analytic signal transformer 3901 used in the timing jitter estimator 3900. For example, FFT (Fast Fourier Transform) is applied to the clock signal under measurement by a time domain to frequency domain transformer 4301 to transform a signal in time domain into a both-sided spectrum signal (for example, Fig.

24) in frequency domain. Negative frequency components of the transformed both-sided spectrum signal in frequency domain are replaced by zero by the bandwidth limiter 4302 to obtain a single-sided spectrum signal. In addition, regarding, this single-sided spectrum signal, only components around the fundamental frequency of the clock signal under measurement are retained and the other frequency components are replaced by zeros to band-limit the signal in frequency domain. Inverse FFT is applied by a frequency domain to time domain transformer 4303 to the band-limited single-sided spectrum signal to transform the signal in frequency domain into an analytic signal in time domain.

Fig. 66 shows further another configuration example of the analytic signal transformer 3901 used in the timing jitter estimator3900. This analytic signal transformer 4500 comprises a buffer memory 4501 for storing therein a clock signal under measurement, a signal extractor 4502 (waveform data selector) for extracting the signal in the sequential order from the buffer

memory 4501 such that the signal being extracted is partially overlapped with the signal extracted just before, a window function multiplier 4503 for multiplying each extracted partial signal by a window function, a time domain to frequency domain transformer 4504 for transforming each partial signal multiplied by the window function into a both-sided spectrum signal in frequency domain, a bandwidth limiter 4505 for extracting only components around a positive fundamental frequency of the clock signal under measurement from the both-sided spectrum signal transformed in frequency domain, a frequency domain to time domain transformer 4506 for inverse-transforming an output of the bandwidth limiter 4505 into a signal in time domain, and an inverse window function multiplier 4507 for multiplying the transformed signal in time domain by an inverse number of the window function to obtain a band-limited analytic signal. The time domain to frequency domain transformer 4504 and the frequency domain to time domain transformer 4506 may be packaged using FFT and inverse FFT, respectively. In addition, the bandwidth limiter 4505 may be constructed such that the pass bandwidth of the signal can arbitrarily be changed.

The operation in the case of transforming the clock signal under measurement into a band-limited analytic signal using this analytic signal transformer 4500 will be described with reference to Fig. 67. First, in step 4601, the buffer memory 4501 stores therein the clock signal under measurement. Next, in step 4602, the signal extractor (waveform data selector) 4502 extracts a

portion of the stored signal from the buffer memory 4501. In step 4603, the window function multiplier 4503 multiplies the extracted sectioned signal by the window function. In step 4604, the time domain to frequency domain transformer 4504 applies FFT to the partial signal multiplied by the window function to transform the signal in time domain into a both-sided spectrum signal in frequency domain. In step 4605, the bandwidth limiter 4505 replaces negative frequency components of the transformed both-sided spectrum signal in frequency domain with zero.

Furthermore, in step 4606, the bandwidth limiter 4505 retains only components around the fundamental frequency of the clock signal under measurement in the single-sided spectrum signal produced by replacing negative frequency components with zero and replaces the other frequency components with zero to limit the bandwidth of the signal in frequency. domain. In step 4607, the frequency domain to time domain transformer 4506 applies inverse FFT to the band-limited single-sided spectrum signal in frequency domain to transform the signal in frequency domain into a signal in time domain. In step 4608, the inverse window function multiplier 4507 multiplies the inverse-transformed signal in time domain by an inverse number of the window function used in the multiplication in the step 4603 to obtain a band-limited analytic signal. Finally, in step 4609, a check is made to see if there is unprocessed data remaining in the buffer memory 4603. If there is unprocessed data remaining in the buffer memory, the signal extractor 4502 extracts, in step 4610, the signal in the sequential order from the buffer memory

4501 such that the signal being extracted is partially overlapped with the signal extracted just before, and thereafter steps 4603, 4604,4605,4606,4607,4608 and 4609 are repeated. If there is no unprocessed data, the process ends. The processing sequence of the step 4605 and the step 4606 may be exchanged.

That is, only components around the fundamental frequency of the signal under measurement are retained and the other frequency components are replaced with zeros first to limit the bandwidth of the signal in frequency domain, and thereafter negative frequency components of the both-sided spectrum signal may be replaced with zero.

In the linear phase remover 3903 in the timing jitter estimator 3900 shown. in Fig. 63, for example as illustrated in the figure, an inputted instantaneous phase is converted into a continuous instantaneous phase by a continuous phase converter 3091. Regarding the continuous instantaneous phase, a linear instantaneous phase corresponding to a jitter-free ideal signal is estimated by a linear phase estimator 3092 using, for example, a linear trend estimation method, i. e., by applying a linear line fitting by least squares method to the continuous instantaneous phase, to output an initial phase angle o (t) of the clock signal under measurement xj (t). In addition, the linear instantaneous phase is subtracted from the continuous instantaneous phase by a subtractor 3093 to output an instantaneous phase noise A f (t).

Further, Figs. 63,65, and 66 are shown in the international

publication WO00/46606 (published on August 10,2000) report.

As indicated by dashed lines in Fig. 57, analog clock signals under measurement xj (t) and Xk (t) may be digitized by AD converters 4701a and 4701b, respectively to convert the analog clock signals into digital signals, and the digital signals may be inputted to the respective timing jitter estimators 401a and 401b. In addition, as indicated by dashed lines in Fig. 57, waveform clippers 4901a and 4901b may be provided to supply those input signals xj (t) andxk (t) to the AD converters 4701a and 4701b or the timing j itter estimators 401a and 401b, respectively after removing AM components in the state that phase modulation components, that are jitter components of the respective input signals, are retained in the input signals. The waveform clippers 4901a and 4901b may be provided in the output sides of the AD converters 4701a and 4701b, respectively.

In addition, as indicated by dashed lines in Fig. 63, low frequency components of the instantaneous phase noise may be removed by a low frequency component remover 5101 from the instantaneous phase noise A 0 (t) outputted from the linear phase remover 3903, and the instantaneous phase noise from which low frequency components have been removed may be supplied to the zero-crossing sampler 3905.

In the above description, the instantaneous phase noise (t) is sampled at approximated zero-crossing points to obtain

a timing jitter sequence [n] However, since the linear phase remover 3903 has a configuration as shown in Fig. 63, for example as indicated by dashed lines in Fig. 68, the sampling at approximated zero-crossing points may be inserted in series between the instantaneous phase estimator 3902 and the continuous phase converter 3091. Alternatively, the sampling at approximated zero-crossing points may be inserted in series between the continuous phase converter 91 and the linear phase estimator 3092/subtractor 3093. In such a configuration, a timing jitter sequence A j [n] can also be obtained from the subtractor 3093.

In addition, since the estimation of an instantaneous phase noise A 0 (t) from an instantaneous phase is performed by the configuration shown by the linear phase remover 3903 in Fig.

63, the processing procedure is, as shown in Fig. 69, that after an instantaneous phase is obtained in the step 4002 in Fig. 64, in step 4003a, the instantaneous phase is converted into a continuous instantaneous phase by the continuous phase converter 3091, and in step 4003b, a linear instantaneous phase of the continuous instantaneous phase is estimated by the linear phase estimator 3092 from the continuous instantaneous phase. After that, in step 4004, the linear instantaneous phase is removed by the subtractor 3093 from the continuous instantaneous phase to obtain an instantaneous phase noise A A (t).

Therefore, similarly to the configuration shown in Fig.

68, as indicated by dashed lines in Fig. 69, the approximated zero-crossing sampling may be applied to the instantaneous phase in step 5001 after the step 4002 to obtain a sample sequence of the instantaneous phase. And then the process may move to the step 4003a to transform the sample sequence into a continuous instantaneous phase.

Alternatively, in step 5002, the continuous phase obtained in the Step 4003a maybe sampled at the approximated zero-crossing points to obtain a sample sequence of the continuous instantaneous phase, and then the process may move to step 4003b to estimate an instantaneous linear phase from the sample sequence of the continuous instantaneous phase. In either case, in step 4004, there is obtained a timing jitter sequence A 0 i [n] by sampling the instantaneous phase noise at the approximated zero-crossing points.

Regarding the deterministic clock skew estimator 3102 in Fig. 58, for example, as shown in Fig. 70, the clock signals under measurementxj (t) andxk (t) may be inputted to zero-crossing timing detectors 3081 and 3082, respectively. Then zero-crossing timing sequences tizerolc (n) and tkzerOC (n) of those respective signals maybe inputted to a subtractor 3083 to obtain a time difference sequence between corresponding zero-crossing time points of the zero-crossing timing sequences tizeroc (n) and tkzero, (n). Then a mean value of those time differences may be calculated by a mean value calculator 3084 to obtain the mean

value as a deterministic clock skew value r' kskew.

The apparatus shown in Fig. 57 and Fig. 61 can be functioned by executing programs in a computer.

According to the clock skew measurement apparatus and the clock skew measurement method of the present embodiment, a random spread (random components) of clock skew can be measured, and therefore an efficiency of clock skew test can greatly be improved.

Moreover, if necessary, the apparatus can be constructed such that one of the clock skew components that is deterministically determined by clock distribution network paths are also simultaneously measured.

In addition, according to the clock skew measurement apparatus and the clock skew measurement method of the present embodiment, a clock skew between clock signals each having a different frequency from one another can be obtained. By this, a clock signal having relatively low frequency can be used as a reference clock signal in a clock skew test, and therefore an efficiency and a practical usability of a clock skew test can greatly be improved.

In addition, according to the clock skew measurement apparatus and the clock skew measurement method of the present embodiment, a clock skew between clock signals under measurement can be estimated by simultaneously sampling in the sequential

order clock waveforms under measurement utilizing an apparatus that can simultaneously measure two channels. By this, the number of required simultaneous samplings can be decreased from NC2 (=N (N-1)/2) to (N-1) two-channel simultaneous measurements, and therefore a measurement time of clock skew can greatly be decreased.

In addition, according to the clock skew measurement apparatus and the clock skew measurement method of the present embodiment, only the minimum number of pins are required when clock signals to be distributed within, for example, a semiconductor chip are taken out to the outside of the chip.

Therefore, the test expense of VLSI test can be reduced.

Although the present invention has been described by way of exemplary embodiments, it should be understood that many changes and substitutions may be made by those skilled in the art without departing from the spirit and the scope of the present invention which is defined only by the appended claims.

Industrial Applicability As described above, according to the apparatus and method of the present invention, the estimating and measuring time of clock skews can be shortened.