PERFORMING SPREAD-SPECTRUM CLOCK CONTROL

FIELD

One or more embodiments described herein relate to processing signals.

BACKGROUND

Clock circuits are used to synchronize or control the performance of various functions in electronic systems. These systems include but are not limited to mobile devices that perform wireless communications over a variety of channels. In a typical wireless device, display clocks, peripheral component clocks, memory clocks, and central processing unit (CPU) clocks can generate interference that diminishes the efficiency of platform wireless connections.

The main source of interference comes from harmonics of these clocks. These harmonics can overlap the frequency range of one or more wireless (radio) channels. This overlap may significantly reduce the data rate and/or operating range of the channel, thereby diminishing communication quality or limiting device capability.

Many such clocks use a technique called spread spectrum clocking (SSC) in order to reduce the energy levels of clock harmonics and comply with regulatory limits on electromagnetic emissions. However, this technique often increases interference with wireless receivers in the same system by spreading the harmonic energy into radio channels.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows an apparatus for generating spread- spectrum clock signals.

Figure 2 shows control information for generating spread- spectrum clock signals in different modes of operation.

Figure 3 shows the progression of states in one operational mode example.

Figure 4 shows clock signals frequencies for the states in the mode of Figure 3.

Figure 5 shows one embodiment of a method for controlling spread- spectrum clocking.

Figure 6 shows another embodiment of a method for controlling spread- spectrum clocking.

Figure 7 shows an example of the noise that may exist at various harmonics of a clock signal.

Figure 8 shows an example of a locking-mode diagram for spread- spectrum clocking.

Figure 9 shows the formation of a notch in the clocking spectrum for a channel produced by the locking-mode diagram of Figure 8. DETAILED DESCRIPTION

Figure 1 shows one embodiment of an apparatus for controlling the generation of spread- spectrum clock (SSC) signals in an electronic system. The electronic system may include, for example, any one of a number of mobile terminals such as a smart phone, wireless phone, personal digital assistant, pad terminal, pod- type terminal, navigation system, laptop or notebook computer, as well as others. The system may also be stationary or transportable such as but not limited to a desktop computer or other type of embedded processing apparatus.

The spread- spectrum clock signals may be generated to allow clocks to remain viable for use while at the same time reducing interference in the radio channel by at least a predetermined amount. The SSC clocking signals are generated by controlling one or more parameters of a phase-locked loop (PLL) included in the apparatus.

In accordance with the embodiment of Figure 1, the apparatus includes a phase-locked loop (PLL) circuit having a phase detector 1, a charge pump 2, a loop filter 3, an oscillator 4, and two divider circuits. The first divider circuit 5 divides the spread clock signal output from the VCO by a predetermined value n. The divided clock signal is sent along a feedback path to one of two inputs of the phase detector. The second divider circuit 6 divided a reference clock signal by a predetermined value m, which may or may not be the same a value n. The divided reference clock signal is input into the other input of the phase detector.

The phase detector compares the phase and/or frequency of the divided clock signal and divided reference signal and generates a difference signal for input into the charge pump. The difference signal may be an up signal or a down signal, or another type of signal indicative of the difference between the divided clock and reference signals.

The charge pump may source current to or sink current from the low-pass filter based on the difference signal from the phase detector. For example, if the divided clock signal is less than the divided reference signal, the charge pump may source current to the low-pass filter. Conversely, if the divided clock signal is greater than the divided reference signal, the charge pump may sink current from the low-pass filter.

The loop filter may be, for example, a low-pass filter made from a capacitor coupled in parallel with a resistor. When the low-pass filter receives source current from the charge pump, the voltage of the capacitor is charged. When current is sourced from the capacitor of the low-pass filter, capacitor voltage decreases. The charging or discharging of the capacitor generates a control signal for controlling the VCO. Also, the capacitor and resistor of the low-pass filter form a low-pass filter which may remove spurious components from the VCO control signal. In other embodiments, a band-pass, high-pass, or other type of filter may be used. The oscillator may be, for example, a voltage-controlled oscillator which outputs a clock signal based on the control signal output from the low-pass filter. Depending on whether the output of the phase detector was an up or down signal, the VCO increases or decreases the frequency of the clock signal. The comparison performed by the phase detector continues until the two input signals are equal in frequency, thereby producing a stable clock signal output set to a desired channel/frequency. In other embodiments, an oscillator different from a VCO may be used.

The clock signal output from the VCO may correspond to or serve as a basis for generating a spread- spectrum clock signal to synchronize or control functions of the host system. According to one embodiment, the clock signal frequency may be expressed as: Fout = (n/m) · Fref.

In order to implement spread spectrum clocking based on the clock signal output from the

PLL, digital control logic 7 adjusts one or more parameters of the PLL based on, for example, a required mode of operation at a time during the course of operation of the host system. In accordance with one embodiment, the parameters to be adjusted for each mode may be determined based on control information stored in a spread profile storage 8, which may be located within or coupled to control logic 7. The profile storage may be a memory, a set of registers, a logic machine, or any other implementation.

Figure 2 shows an example of the control information stored in profile storage for controlling one or more parameters of the PLL. The control information may include a plurality of sets of parameters, each for controlling operation of the PLL (and thus generation of spread- spectrum clocking) for a respective one of a plurality of modes of operation of the host system. In Figure 2, the sets of parameters are conceptually shown as different profiles, where profile 0 defines a set of PLL parameters for different states in the initial operational mode of the system, profile 1 defines a set of PLL parameters for different states in the next operational mode, and so on.

The number of profiles may be equal to or different from the modes, taking into account that different parameters settings may be required for the PLL within any given mode of operation.

Additionally, or alternatively, the profiles may be used to control the PLL clock for different platforms in the host device. For example, when the host system is a mobile terminal, the PLL may be used to generate different spread- spectrum clocking for different platforms . This may prove to be especially useful for certain system- on-chip (SOC) applications.

Also, the parameters to be set or otherwise adjusted by the profiles may be the same or different from state-to-state, from mode-to-mode, and/or from platform-to-platform. For illustrative purposes, one or more of the divider values and/or one or more of the charge pump settings may be set or otherwise adjusted from state-to- state and/or from mode-to-mode. Referring again to Figure 2, profile 0 defines the parameters for the PLL for the initial mode of operation having k states sO, si, ... sk. In accordance with one embodiment, each state may set three parameters, namely the clock cycles required to transition to the next state along one direction of the spread, the clock cycles required to transition to the next state along the opposite direction of the 5 spread, and a set of PLL parameters. These are shown as ci, ci' , and plli, for the ith state, si. The PLL parameters, plli may be, but are not limited to the n value of divider 5, and the m value of divider 6, and setting(s) corresponding to the operation of the charge pump. The same mechanism can be implemented in another fashion for a digital PLL.

The remaining states s 1 to sk in the first mode of operation have settings for these parameters o which may all be different or some of these parameters may be the same, depending on the specific state, for the same spread profile. The remaining profiles may have the same or different numbers of parameters for other operational modes of the host system, to be used to control the PLL for a different spread profile. The digital control logic 7 generates a set of PLL control parameters Pi, based on the input from the profile storage, ci, ci', and plli. The control parameters set Pi is sent to 5 the PLL. These PLL control parameters, Pi may be, but not limited to setting(s) corresponding to the divider value(s), the charge pump current, or the loop filter capacitance. For other types of PLLs such as a digital PLL, different PLL parameters, Pi may be generated by the digital control logic. The control logic may implemented by a digital state machine or other type of control.

Figure 3 shows an example of a state diagram for one operational mode of the host system, o where parameter k = 3 for one of the profiles shown in Figure 2. Given this parameter, the state diagram will have four states (sO to s3) with parameters stored in a corresponding profile in profile storage. The digital control logic is responsible for shifting from one state to the next state. The four states are sequentially executed over a time period and the sequence is iterated. Figure 4 shows the clock signal frequency over this time period.

5 Referring to Figures 3 and 4, in the sO state, the control logic 7 may set the PLL parameters to values P0 for an initial state sO. These parameters cause the output clock signal of the PLL to be set to a frequency fO.

When the host system transitions from sO to state si, the divider and charge pump parameters are set to cause the PLL clock signal to be set to a frequency f 1. The frequency transition from fO to 0 fl may be substantially linear according to one example. However, in other embodiments, this transition may follow a predetermined curvature or may otherwise be non-linear. The state machine will perform the transition from state s 1 to s2 after c 1 clock cycles, or from state s 1 to sO or c 1 ' clock cycles depending on the direction of the spread. When the host system transitions from s 1 to state s2, the divider and charge pump parameters are set to cause the PLL clock signal to be set to a frequency f2. The transition from state si to s2 takes place relatively quickly. This, in turn, causes the output change in frequency output of the PLL to be proportionally fast, thereby allowing spread- spectrum clocking to have a faster response time 5 compared with many other techniques for controlling spread- spectrum clocking. This may have the effect of improving performance and/or reducing interference in a manner to be described in greater detail.

When the host system transitions from s 1 to state s3, the divider and charge pump parameters are set to cause the PLL clock signal to be set to a frequency f3. The transition from state s2 to s3, o therefore, may take place more slowly compared with the transition from state s 1 to s2, and hence the transition between f2 and f3 may be slower than that between f 1 and f2.

In this example, subsequent state transitions from s3 to sO produce frequency-to-frequency changes at least substantially in a mirror image of the frequency changes that took place from state sO to s3. Of course, in other embodiments, different state transmissions may be performed for different5 state and/or frequency transitions, and/or different profiles may be used for different operational modes, of the host system. A specific explanation of how the charge pump parameter is controlled to adjust the clock signal output of the PLL will now be given.

Figure 5 shows one embodiment of a method for controlling the generation of a spread- spectrum clocking signal. This method may be performed by the circuit of Figure 2 based on the o profiles and parameters in Figures 3 and 4, or may be performed by another circuit and/or another set of profiles or parameters. In this embodiment, the slew rate of the VCO (which produces the clock signal) is controlled by using profiles that change the charge pump setting to achieve an increase in the open-loop VCO slew rate. Controlling the charge pump as a way of controlling the rate of change of spread- spectrum clocking may, in some applications, produce a faster response time, thereby 5 leading to improved performance.

An initial operation includes identifying a current mode of operation of a host system. (Block 210). The operational mode, of course, depends on the system. For example, if the system is a mobile terminal such as a smart phone, the operational mode may be performing a voice call, transmitting a text message, or accessing the internet. In any one of these modes, different states of 0 operation are required in order to support different operations of the phone, e.g., transmitter-receiver use, call connection processing, various paging functions, etc.

Once the operational mode has been identified, a controller or processor of the system may select from a storage area a profile corresponding to the operational mode. (Block 220). This controller or processor may, for example, correspond to digital logic 7 and the storage area may correspond to profile storage 8. As illustratively shown in Figure 2, the profile storage may store a plurality of profiles, each assigned to control operation of a spread- spectrum clock for a corresponding operational mode.

Also, as shown in Figure 2, each profile may include values for one or more parameters for controlling the PLL. In accordance with the present embodiment, the profile corresponding to the current operational mode makes the control logic to create different charge pump settings for at least two of a plurality of states within that mode. For example, in the illustrative case where k=3 and the selected profile is profile 1 in Figure 2, four different values of charge pump settings P0 to P3 may be included for four corresponding states of operation sO to s3 in this mode. Also, as controlled by by this profile, the charge pump settings change over a time period that includes corresponding clock cycles indicated by parameters c and c' in the profile.

Once the profile has been selected, the controller or processor (e.g., control logic 7) may adjust the charge pump settings at times corresponding to the designated clock cycles in the profile and at the different states corresponding to these clock cycles. (Block 230). In the case where k=0, only one charge pump setting may be applied for one state that corresponds to one frequency. In other cases where k > 1, various charge pump settings may be applied as previously explained.

By controlling the charge pump to, in turn, control changes in spread- spectrum clocking, a faster and more efficient adjustments in clock signal frequency may be affected. This is evident from the Figure 4, where in this illustrative non-limiting case the change between PLL output frequencies fl and f2 takes place quickly (between si and s2) according to a steep-sloped (e.g., fast slew rate) transitional line. This is in contrast with other approaches for controlling spread- spectrum clocking which control PLL output frequency according to a much more gradual sloped transition, which, in turn, allows for a greater amount of channel interference. The quicker response time of the present embodiment may eliminate much of this interference, allowing for much-improved channel signal quality.

The charge pump setting may control the charge pump of the PLL by changing the pump current. In this case, the PLL parameters Pi may provide digital control of a current-steering digital- to-analog converter (DAC) which affects the amplitude of charging or discharging current fed to the loop filter every reference clock cycle.

Concurrently with the operation of Block 230 or before or after this block, additional adjustments may optionally be made. The additional adjustments may involve adjusting one or more other PLL settings with respective ones of the charge pump settings at each state of the current operational mode. (Block 240). The one or more other PLL settings may be values of one or both of dividers 5 and 6 for the VCO clock signal and reference signal, respectively. Under some circumstances, this optional block may provide for even greater control over the slew rate of the

VCO output frequency, and thus the spread- spectrum clocking that is to be performed. Like the charge pump settings, the divider values may be controlled by control logic 7, based on the profiles stored in profile storage 8.

After the current operational mode is completed, control may continue based on the stored profiles of subsequent operational modes to be detected. (Block 250). This may involve controlling charge pump settings as explained, with or without the adjustment of other PLL parameters at various states within the subsequent modes. If only one PLL is included in the host system, the control logic may control the PLL settings based on other profiles stored in profile storage for each of a plurality of different system platforms in or for functions to be performed by the system.

Figure 6 shows another embodiment of a method for controlling the generation of a spread- spectrum clocking signal. This method is similar to the method of Figure 5, except that instead of controlling the charge pump settings the loop-filter capacitance is changed in a predetermined manner. In this embodiment, the loop-filter capacitor settings are changed based on values in the profiles stored for respective operational modes and states. Thus, in Figure 6, Blocks 310, 320, 340 and 350 may be performed in a manner similar to Blocks 210, 220, 240, and 250, but Block 330 is different in that it involves adjusting the PLL loop-filter capacitance.

For example, the loop filter capacitance can be implemented by a minimum valued capacitor having a set of binary- weighted capacitors in parallel, each with an individually controlled switch. When all switches are open, only the minimum valued capacitor is part of the loop filter. This setting could be used for faster VCO frequency changes. When all switches are closed, the loop filter capacitance is maximized which may correspond to PLL operation with conventional spread frequency rates of change.

Like the method of Figure 5, controlling the loop-filter capacitance from state-to- state and/or from mode-to-mode may serve to increase the slew rate of the VCO compared with other approaches, thereby leading to improved signal quality and/or reduced interference.

Another embodiment corresponds to a method for controlling the generation of a spread- spectrum clocking signal, where both the charge pump setting and loop-filter capacitance are changed in one or more states of operational modes of the host system. In addition, one or more of the divider values and/or other PLL parameters may be changed with the charge pump and loop-filter capacitance settings as a way of further controlling (e.g., increasing or even decreasing, based on the given application) the slew rate of the VCO output frequency.

The parameter (or parameters) adjusted for generating the spread- spectrum clocking signal may be predetermined under various operating conditions for storage in the profiles previously discussed. The parameters may be selected in the profile to reduce a portion of a spectrum corresponding to one or more predetermined channels in a communication band or protocol.

In accordance with one embodiment, the portion of the spectrum to be reduced corresponds to a predetermined portion of a spectrum of the channel that includes noise, and more specifically one or more harmonics of a clocking signal where noise may be resident. For example, at least one parameter to be adjusted may be or affect a slew rate of a voltage-controlled oscillator, e.g., the slew rate may be increased by an amount which reduces noise at one or more harmonics in the spread- spectrum clock signal coincident with one or more frequencies in a range of frequencies allocated to the communications channel.

While this reduction may remove a portion of the clock spectrum itself, a sufficient portion of the unreduced spectrum may remain to allow compliance with electromagnetic emissions regulations, while still providing reduced noise level through adjustment of the slew rate. In other embodiments, a parameter different from slew rate may be adjusted to achieve noise reduction within the frequency range allocated to the channel.

Figure 7 shows an example of the noise that may exist at various harmonics of a clock signal in a heavily used portion of wireless spectrum. As shown, this noise may be attributed to various factors including but not limited to one or more of peripheral clocks, CPU clocks, pixel clocks, and memory clocks. The noise at these harmonics tends to degrade radio performance. To reduce this noise, a portion of the signal spectrum may be reduced (while other portions may be substantially unaffected) to generate a spectrum having less interference from a clock with essentially the same functionality.

Figure 8 shows a locking-mode diagram of how one or more parameters of the phase-locked loop may be controlled by the control logic in accordance with one or more of the aforementioned embodiments, to increase the slew rate of the VCO. In this diagram, the clock cycles are plotted against frequency. Based on adjustments made by the control logic, the PLL locks extremely fast on a proper spread- spectrum clocking signal as evidenced by the substantially vertical slopes in the circled portions of the diagram.

The accelerated rate at which locking occurs causes a notch X to form in the range of frequencies allocated to a particular channel as shown in Figure 9. The arrow in this diagram shows the extent of the spectral energy reduction, which results in a corresponding reduction of clock harmonic noise in this portion of the radio frequency range.

In this example, the extent of the reduction represents the vertical length of the arrow. However, in other embodiments, the adjustments made by the control logic may produce an elimination or near-elimination of the interference energy within the notch. For example, the loop- filter and/or charge pump settings may be controlled, with or without divider- value adjustments, to clear portions of the clock spectrum for radio transmission use in a corresponding channel, while simultaneously reducing noise.

In accordance with another embodiment, a computer-readable medium may store a program including code for implementing any of the aforementioned method embodiments described herein. The computer-readable medium may be a non-transitory medium such as any one of a variety of storage devices or mediums, e.g., internal memory, external storage device, etc. Alternatively, the code of the program may be embedded in a stream or downloadable signal transmitted, for example, over a network.

The program may include first code to determine a mode of an electronic system, second code to receive information from a storage area, and third code to adjust at least one parameter of a phase- locked loop based on the information received from the storage area. One parameter may be at least one of a charge pump setting or a loop-filter capacitance of the phase-locked loop to control spread- spectrum clocking in an electronic system.

In addition, the third code may adjust at least one parameter to cause a slew rate of a voltage- controlled oscillator to increase, the voltage-controlled oscillator to output a signal corresponding to a spread- spectrum clock signal. The slew rate may be increased by an amount which suppresses or eliminates at least one harmonic in the spread- spectrum clock signal at one or more frequencies in a range of frequencies corresponding to a predetermined communications channel.

In accordance with one or more of the aforementioned embodiments, the control logic used to adjust the settings of the PLL may receive a status signal indicating a current operational mode of the host system, the current state within a given mode, and/or the current and the next frequency associated with the states of the mode. Based on this status signal, the control logic may determine what profiles to access for purposes of adjusting the PLL settings.

Alternatively, a profile controller may be provided to cause profile settings to be output from profile storage 8 based on the status signal, so that the control logic may apply these settings to respective portions of the PLL for controlling spread- spectrum clocking. Also, in accordance with one more embodiments, the control logic adjusting the settings of the PLL may be implemented in software, hardware, or both.

One or more embodiments described herein may achieve improved performance compared with other approaches. For example, these embodiments may be implemented without the use of a phase interpolator coupled to the output of the PLL. These interpolators may prove useful in some contexts. However, they have been found to consume power and add to the cost and complexity of the host system. These embodiments may also be implemented with the use of a digital PLL. Also, one or more embodiments described herein may allow for improved customization of the spread- spectrum clock to various applications, e.g., platforms, operational modes, the states in each mode, etc.

Any reference in this specification to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. The features of one embodiment may be combined with the features of one or more other embodiments to form new embodiments.

Furthermore, for ease of understanding, certain functional blocks may have been delineated as separate blocks; however, these separately delineated blocks should not necessarily be construed as being in the order in which they are discussed or otherwise presented herein. For example, some blocks may be able to be performed in an alternative ordering, simultaneously, etc.

Although the present invention has been described herein with reference to a number of illustrative embodiments, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.