Background Embodiments of the present invention relate to an apparatus and method for demodulating a signal.

Synchronous Demodulation (SD) is a signal recovery method which is particularly used when an input envelope signal is modulated by a pure sine wave or a square wave. SD is less efficient for pulsed periodic signals with a low duty factor

Pulsed excitation is used typically in radiometric applications to study the pulse response of systems, but also to observe physical phenomena where continuous or sinusoidal excitation sources are not available. In the latter case, the priority is to measure one or more parameters linked to the time-averaged energy in the signal, rather than recovering its temporal shape.

Instruments that are based on the Synchronous Demodulation (SD) principle are capable of measuring the magnitude and phase of a selected frequency component of the input signal. SD has maximum sensitivity when the input signal is purely sinusoidal or has a duty cycle of 0.5 because the employed modulation-demodulation scheme assumes strictly harmonic functions. In the frequency domain, periodic signals with duty cycle substantially deviating from 0.5 will experience reduction of their magnitude detected at the fundamental frequency because of spreading their energy over higher harmonics. In the time domain, for duty cycle less than 0.5 the signal energy will be smeared over the whole half-period, while for duty cycles larger than 0.5 some signal energy will be lost. In either case of deviation, the pulsed character of the signal becomes essential and the extraction of a single frequency component (usually the fundamental) will no longer be efficient

It is an object of embodiments of the invention to at least mitigate one or more problems of the prior art. Summary of the Invention

According to aspects of the present invention there is provided methods and apparatus as forth in the appended claims.

Brief Description of the Drawings

Embodiments of the invention will now be described by way of example only, with reference to the accompanying figures, in which:

Figure 1 shows an apparatus according to an embodiment of the invention;

Figure 2 shows an illustration of time and Fourier domain signals according to an embodiment of the invention;

Figure 3 shows a method according to an embodiment of the invention;

Figure 4 illustrates a determination of a duty cycle according to an embodiment of the invention;

Figure 5 illustrates a method according to an embodiment of the invention;

Figure 6 illustrates exemplary gate window characteristics according to an embodiment of the invention;

Figure 7 further illustrates exemplary gate window characteristics according to an embodiment of the invention; and

Figures 8 and 9 illustrate a performance of an embodiment of the invention.

Detailed Description of Embodiments of the Invention Figure 1 illustrates a demodulation apparatus 100 according to an embodiment of the invention. The apparatus 100 comprises gating signal generation unit 110, a digital gating unit 120 and a synchronous demodulation unit 130. The apparatus 100 is arranged to receive an input signal 101 s[k], which may be a pulsed input signal 101.

The gating signal generation unit 110 comprises a gate characteristic estimation module 111 and a gating signal generation module 112. The input signal is provided to the gate characteristic estimation module 111 for estimate a length M of a gate signal gfkj as will be explained. The estimated length M is provided by the gate characteristic estimation module 111 to the gating signal generation module 112 which is arranged to generate the gate signal gfkj which is output 115 from the gating signal generation unit 110 to the digital gating unit 120.

The gate characteristic estimation module 111 is arranged to estimate the length M so as to maximise a magnitude of a fundamental frequency in a signal sa[k] output 121 by the digital gating unitl20. In some embodiments the gate characteristic estimation module 111 also determines a delay value D.

The gate signal g[k] is provided to the digital gating unit 120 to control when samples from the input signal 101 s[k] also provided to the digital gating unit 120 are output from the digital gating unit 120. When the gate signal g[k] transitions to a first predetermined value, which in one embodiment is high, the digital gating unit 120 opens allowing segments of the input signal s[k] to form the output signal 121

When the gate signal makes an opposing transition to a second predetermined value, such as to low, the segments are stopped. The length of the gate opening (high period in one embodiment) is controlled by M. A temporal position of the transition to the first predetermined value is given by a value D relative to an applied trigger. The applied trigger may be a first sample of the signal.

The gate characteristic estimation module 111 is arranged to determine a value of M which maximizes a magnitude of a fundamental frequency in sa[k This may be achieved by computing a discrete time Fourier series (DTFS) of the pulse input train s[k]. The general expression of discrete Fourier series representation of a function J[k] is:

h=0

N ₀ -l

∑ f[k]e

k=0 where k and h enumerate respectively the samples and harmonics of f[k]; 3 _h and No denote, respectively, the magnitude of h-th constituent harmonic and the period (in units of k) of/[&].

Therefore the DTFS of the pulsed input train s[k] is given

where A is the pulse amplitude and X is the pulse width (in units of k). The second term gives the magnitude sum of the harmonics that are contained within the input signal. The h=l term in the above equation represents the magnitude 3i of the fundamental harmonic of s[k]:

_{( ) =} J_ sin( o)

u ° ' N ₀ sin(^ / W ₀ )

The function 3ι(Νο) in the equation above has a maximum at No = M = 2X, which corresponds to a duty cycle δ = 0.5. Therefore the gate estimation unit determines a value of M which has a duty cycle of 0.5. Whilst M may be calculated in a straightforward manner for a signal composed of rectangular pulses as M=2X, it is expected that often the pulse shape will be irregular. For example the pulse shape may correspond to an output of a detector such as a radiation detector. The pulse shape may also depend upon characteristics of an emitter and/or a receiver.

When the pulse shape is complex but reproducible, the fundamental component of the signal 3 _G i may be estimated by comparing its value with M as parameter. The solid line in Fig. 4a represents a rectangular pulse pattern, repeating every 250 samples (i.e. No=250). In this example the width of the emitter pulse contains 25 discrete samples resulting in a duty cycle of 0.1. The dashed line plot illustrated in Fig. 4a shows the receiver's steady-state response as simulated in COMSOL Multiphysics for a pyroelectric detector (PED).

Figure 4b illustrates an embodiment in which Mis determined numerically by finding a maximum from a plurality of FFT calculations of 3 _G i for a gate size that varies from 1 to No. The gate size M may be varied in unit increments in one embodiment between a minimum and a maximum, wherein the minimum may be 1 and the maximum may be equal to No _. The unit increment may be 1 sample, or may be another predetermined number of samples. Thus a method according to an embodiment of the invention may comprise a step of determining a gate size M resulting in a maximum constituent harmonic. The harmonic may be a 1 ^st harmonic 3 _G1.

Noticeable in Fig. 4b is the difference between the two plots corresponding to the rectangular excitation pulse (bold) and the PED response (dashed). In the former case, concatenation with new samples of the same value (up to k=25) does not contribute to a harmonic function and 3QI is zero. The latter plot manifests a double peak - the first maximum is caused by the PED response peaking half way through the excitation pulse while the second corresponds to a harmonic contribution (k=45) resulting from the positive to negative swing. The position of the second maximum is determined by the value of k for which the area under the signal becomes zero, resembling 5G of 0.5.

In some embodiments the above procedure relating to the determination of M is repeated for a plurality of values of delay D. This is achieved by shifting and rotating the input signal s[k]. The input signal may be shifted and rotated one sample at a time, although other shift values may be used. Each value of 3 _G1 is estimated and saved in a 2D matrix as shown below. The row and column indices of the element containing the maximum value of 3 _G i, corresponds to the optimal value of D and M, respectively.

A method 500 according to an embodiment of the invention for determining M and D is shown in Figure 5. The method may be performed by the characteristic estimation module 111.

In step 510 a signal s[k] is received. It will be realised that step 510 is optional depending on the source of the signal. For example the signal may already be present in a memory of a computer performing a method according to an embodiment of the invention.

In step 520 variables are initialised. 3G[ ] is used to store a Fourier transformed version of the signal. 3GI,( r) is a two dimensional matrix storing 3 _G i for a plurality of values of M and D. In step 530 the signal s[k] is shifted by a value of variable r which stores a current shift value indicating a number of samples by which the signal is shifted.

In step 540 a fast Fourier transform (FFT) is performed on the gated signal sc[k], to calculate the value of the harmonics 3G The FFT window size is specified by the variable i taking values from 1 to N. The fundamental harmonic of the gated signal sc[k] is extracted from 3G and consequently placed in the 2D array 3GI,( _I , _R ) in a location defined by the instantaneous values of the variable i and r.

In step 550 it is determined whether the variable / is greater than or equal to N, wherein N is the signal period in units of k. If not the method moves to step 560 where i is incremented and the FFT repeated unit the gate window M is equal to the number of samples N, wherein the method moves to step 570.

In step 570 it is determined if the variable r is greater than or equal to N. If not, the method moves to step 580 where the gate width counter i is zeroed and the shift counter r is incremented by one.

In step 530 the signal s[k] is shifted by the new value of r. Steps 540-550 are then repeated for the shifted signal. Once in step 570 it is determined that r=N then the method moves to step 590.

In step 590 the method outputs the indexes of the element containing the maximum value in the matrix storing the values of the calculated harmonics. The row and column indexes of that element represent the optimal values of M and D respectively.

For example, in the case of a rectangular pulse waveform with period of 624 samples and pulse width of 50 samples the resulting matrix for the fundamental is graphically illustrated in a 3D graph in Fig. 6. For clarity purposes, 3[k] is plotted only for 0, 200, 400, and 624 trigger delays D (rainbow coloured plots) whereas the black-sphere plots indicates the maximum value of 3 _G1 for all the triggering delays. From the 3D plot, it can be observed that as the trigger delay D departs from the zero the value of 3[k] is be kept constant as long as the value of M is adjusted to withhold 5Q at 0.5. Consider the rectangular pulse input shown in Fig. 6. A pulse width of 50 samples implies that maximum value if 3[k] is achieved for M = 50 and D = 100. Reducing D to 50, the value of 5G still remains 0.5 and hence 3[k] at maximum. Similarly, a smaller gate window M of 20 or 50 samples yields the same results by adjusting D to the appropriate value.

For arbitrary, and most importantly, non-symmetric shaped pulses, the possibility of multiple combinations between M and D is minimized. Thus values of D and M are determined which provide a maximum magnitude of 3[&]. The indexes of the matrix are determined storing the maximum magnitude of 3[k] to determine D and Figure 3 illustrates a method 300 according to an embodiment of the invention which may be performed by the digital gating unit 120.

In step 305 it is determined whether a variable "start" is equal to true. The start variable is used to stop the method when set to false. True may be equal to a value of 1. If the start variable has a value of true then the method moves to step 310.

In step 310 variables used in the method are initialised. In one embodiment the following variables are utilised: i is used to store a value indicative of a current loop index and may be initialised to 0; p is used to store a current output sample number and may be initialised to 0; and a register or array used to store sample values REG may be initialised to store 0s at each sample index. The number of register or array elements in REG may be equal to the number of samples in one period of the input signal. For example if the input signal s[k] comprises 640 samples in each period (£=0-640) REG may comprise 640 elements.

In step 315 one or more input signals are received. The input signals comprise the input signal s[k] 121 and the gate signal g[k] 122. It will be realised that step 315 may be performed in another position of the method 300, or may be performed as a background operation.

In step 320 it is checked whether the loop index i is less than or equal to a number of samples in the input signal s[k] 121. The number of samples in the input signal may be denoted as L. In one embodiment the input signal may be sampled so that L=N ₀ . If i≤L then the method moves to step 325. Otherwise the method moves to step 360.

In step 325 it is determined whether the gate signal g[k] at the respective index position i corresponds to open or closed. For example, where open is indicated by a high value or T, the method moves to step 330 when the gate signal g[i] is equal to this value.

In step 330 a respective sample of the input signal is stored in a current register position. In embodiments where the current register position is denoted by the variable p REG[p] is used to store the current sample of the input signal s[i] as REG[p]=s[z] in step 330.

In step 335 one or more variables are updated. In one embodiment the index of the current sample in the input signal i is incremented (/ ^' =/ ^' + 1). In one embodiment the index of the current output sample p is also incremented (p=p+l). Following step 335 the method returns to step 320 wherein it is determined whether the new loop index i is less than L. In steps 340-355, if the gate signal g[k] at the respective index position i corresponded to closed in step 325 then the next sample of the input signal is selected without selecting a next element of the register REG. In step 340 the index p is decremented and in step 345 the newly selected register element REG[p] is updated to store its existing value. Then in step 355 both i and p are incremented such that after steps 340-355 i has effectively been incremented whilst p and REG[p] stores their values prior to step 340. The method then returns to step 320.

In step 320 if all samples of the current period of the input signal s[k] have been selected i.e. i=L then the method moves to step 360. In step 360 the content of the output register REG are output for processing by the synchronous demodulation unit 130. It will be appreciated that whilst the input signal s[k] comprises k samples in each period, such as £=640, the register REG may only store a portion of the input samples from each period. Samples of the input signal whilst the gate signal g[k] is closed are discarded or not stored in REG. Therefore REG may comprise fewer samples than s[k]. REG concatenates adjacent periods of the input signal whilst the gate signal is indicative of open. The signal samples stored in REG may be output as S _G [£]=REG[&] 121 as can be appreciated from Figure 2.

The synchronous demodulation unit 130 comprises a DC module 13 1 , a reference signal generation module 132 and a phase sensitive detector (PSD) module 133. The reference signal generation module 132 and the phase sensitive detector module 133 perform quadrature synchronous detection (QSD) on the signal s _G [k] 121 received from the digital gating unit 120. The QSD is based upon the length of the gate signal provided from the digital gating unit 120 as signal 122. The reference signal generation module 132 of the synchronous demodulation unit 130 is arranged to generate first and second quadrature reference signals. The quadrature reference signals may be denoted as i[k] and q[k] wherein which q[k] is π/2 phase-shifted from i[k]. The reference signals 132a, 132b are provided to the PSD module 133. A product of the reference signals with sc[k] determines real and imaginary components of the referenced harmonic, such as the 1 ^st harmonic. Referencing towards M ensures selective demodulation from a discrete carrier wave specified by the optimized gating period, as opposed to the pulse repetition rate.

The DC module 131 of the synchronous demodulation unit 130 is arranged to receive the signal output 121 by the digital gating unit 120. The DC module 131 is arranged to reduce or attenuate a DC component of the received signal such that a contribution of the DC component of sc[k] to the output signal is reduced. The DC module 131 may comprise a 1 ^st order Butterworth high pass filter (HPF) to filter the input signal and to produce a filter signal 131a which is provided to the PSD module 133. It will be realised, however, that other choices of filter may be used.

The PSD module 133 comprises one or more filters, for example, infinite impulse response (IIR) low-pass filters (LPF) which are arranged to extract the DC term of I[k] and imaginary Q[k] and subsequently compute the magnitude K[k] and phase φ of the demodulated complex vector according to:

where ΑΘ is the phase difference between the harmonic of interest and the reference signal. In one embodiment the PSD module 133 comprises at least one filter arranged to receive each of the I and Q reference signals 132a, 132b. In one embodiment two LPF filters are arranged in each of the I and Q reference signal paths in the PSD module 133. A time response of an embodiment of the invention is affected by the gate characteristic resulting to an observed time constant (OTC) as described by the equation below where x _Sd ,T ₀ , and T _s are the time constant of the LPFs of the PSD module 133, the pulse period, and the sampling time, respectively (in sec), whereas M specifies the gate width (in number of samples).

OTC = x for r _d > MT m

M T

The SNR performance of an embodiment of the present invention compared against a static mode gated integrator (SMGI) was recorded for detecting rectangular pulse trains (Case A), realistically shaped pulsed signals generated by SPS (Case B) and coloured noise (Case C) under various input conditions. The output signal-to-noise (SNR) values for each are plotted in Fig 8 and Fig 9, as bar charts where the black and grey bar series correspond to the performance of the present invention and SMGI respectively. The results of Case A are shown in Fig. 8a for white noise and Fig. 8b for 1/f noise. Similarly, Fig. 8c and Fig. 8d depict the performance of the two methods for Case B. Results for Case C are presented in Fig.9. The results are consistent for varying gate size, varying OTC, as well as type of pulse. The variations depending on the type of noise are presented and discussed below. The results in Fig. 8a and Fig. 8c imply that for white noise the SNR performance of SMGI is superior to that of an embodiment of the invention for the lower two gate sizes. In the example case shown in Fig. 8a.2. even though for a gate size of 136 samples the SNR output of an embodiment of the invention (49.5dB) is higher than SMGI (46.2dB), this is not sustained for a smaller number of samples. The SNR performance of SMGI increases to 52.5dB when the gate size is decreased to 62 samples. The reduction of the gate size caused the output signal of SMGI to increase from 18.054mV to 44.961mV and the output noise from 88.45μν to 106.74μν. In comparison, the output of an embodiment of the invention increases from 15.85mV to 15.94mV whereas the noise from 53.86μν to 82.48μν. In both methods, the output noise was observed to be higher since an effective bandwidth /¾/) of the internal LPFs feff was increased to maintain the same OTC. Even with lower output noise, the SNR of an embodiment of the invention is overall less than the SMGI under Gaussian white noise conditions. These are expected results, since the SMGI measures the peak amplitude of the pulse which is substantially higher than the magnitude of the fundamental harmonic of the gated signal s _G (k) used in an embodiment of the invention.

The SNR performance of an embodiment of the invention improves in the case of 1/f noise as shown in Fig. 8b and Fig. 8d. This is exemplified in charts (2) and (3) where the performance of the two methods becomes comparable already for the intermediate gate sizes. A significant improvement in an embodiment of the invention against SMGI is notable for higher bandwidths where the OTCs values are reduced to achieve higher detection rates. At slower rates, the SNR of SMGI improves due to a substantial decrease of the output noise while the output signal level is maintained at a voltage much higher than an embodiment of the invention. The results obtained in Case C are shown in Fig. 8 where the two methods were tested under various types of colored noise proportional to l/f^ by varying the exponent factor β. For consistency with previous simulations, the evaluation settings and pulse type are identical to Case B. The bar charts in Fig. 8a, Fig. 8b, and Fig. 8c represent the SNR performance of the two methods for β = 1.5, β = 2, and β = 2.5 respectively. As speculated, the performance of SMGI exacerbates as β increases while the SNR response of an embodiment of the invention remains unaffected. The increase of β results to a steeper slope of the PSD noise curve as shown in Fig. 9. Naturally, the low frequency components of 1/f ^β noise are dominating critically the baseband region causing the SMGI output noise to increase. On the other hand, an embodiment of the invention operates at 2kHz where the 1/f ^β noise is much less, hence the improved SNR.

It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same. Embodiments of the invention may be implemented by a computer which is a device for executing software instructions, such as a computation device. The device may comprise a processor for executing the software instructions and a memory for storing the software instructions.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.