BACKGROUND

[0001] The present disclosure relates to automatic gain control. More specifically, the present disclosure relates to automatic gain control to dynamically adjust the receiver gain depending on the operating scenario.

[0002] Baseband signals include, but are not limited to, video baseband signals, voice baseband signals, computer baseband signals, etc. Baseband signals include analog baseband signals and digital baseband signals. The conversion processes use modulation techniques to modulate higher frequency carrier signals with the baseband signals, to form modulated carrier signals.

SUMMARY

[0003] In one aspect, a receiver is provided. The receiver includes a front end for receiving a radio frequency (RF) signal, a low noise amplifier (LNA) for amplifying the RF signal, a mixer for converting the RF signal to an intermedia frequency (IF) signal, a baseband amplifier for amplifying the IF signal to generate a baseband signal, an analog-to-digital converter (ADC) for sampling the baseband signal, and a gain controller for adjusting a gain of the receiver. The gain controller includes a first gain state performed by a hardware implemented gain controller and a second gain state performed by a software implemented gain controller, and the second gain state is triggered after the first gain state.

[0004] In another aspect, a method for performing gain control in a receiver is provided. A radio frequency (RF) signal is processed by a conversion circuit to generate a baseband signal. The baseband signal is sampled by an analog-to-digital converter (ADC). A gain of the conversion circuit is adjusted with a gain controller based on the baseband signal sampled by the ADC. The gain controller includes a state machine having a plurality of gain states, and the plurality of gain states includes at least one hardware implemented gain state and at least one software implemented gain state.

[0005] In a further aspect, a method for adjusting a gain of a receiver is provided. A radio frequency (RF) signal is received. The RF signal is converted to an intermedia frequency (IF) signal. The IF signal is amplified to generate a baseband signal. The baseband signal is converted to a digital signal. The digital signal is measured. The gain of the receiver is adjusted based on a measurement of the digital signal by sequentially triggering a hardware implemented gain state and a software implemented gain state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0007] FIG. 1 illustrates an exemplary wireless network, according to some implementations of the present disclosure.

[0008] FIG. 2 illustrates an exemplary receiver with automatic gain control, according to some implementations of the present disclosure.

[0009] FIG. 3 illustrates an exemplary state transition diagram for performing a gain control in a receiver, according to some implementations of the present disclosure.

[0010] FIG. 4 illustrates an exemplary state transition table for performing a gain control in a receiver, according to some implementations of the present disclosure.

[0011] FIGs. 5-6 illustrate an exemplary timing diagram for performing a gain control in a receiver, according to some implementations of the present disclosure.

[0012] FIG. 7 illustrates a flowchart of an exemplary method for performing a gain control in a receiver.

[0013] FIG. 8 illustrates a flowchart of another exemplary method for performing a gain control in a receiver

[0014] FIG. 9 illustrates an exemplary node in the wireless network, according to some implementations of the present disclosure.

[0015] The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0016] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0017] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0018] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0019] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as Long-Term Evolution (LTE) or new radio (NR). A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0020] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some implementations of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0021] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0022] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0023] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rackmounted servers by way of illustration and not by way of limitation.

[0024] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0025] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0026] Each element in FIG. 1 may be considered a node of wireless network 100. In some implementations, each node of wireless network 100 may include a receiving apparatus, e.g., a receiver, to receive a signal via a receiving antenna and quantize the signal. In some implementations, the receiver may include a gain control section that adjusts the gain in the receiver in accordance with the electric power of the quantized signal. In some implementations, the automatic gain control (AGC) may have little or no flexibility for dynamically adjusting the state depending on the operating scenario. Once the state machine is designed, the state machine may be fully hardwired or have very little flexibility to reprogram the state transitions. The present disclosure provides a receiver having the AGC state machine with some main states that are flexible to allow the state transition, and the transition time may be programmable, which is chosen from a software programmable table. In some implementations, since the state transition events are based on the programmable time, the state transition may be triggered at any desired time the UE wishes. Furthermore, the operating scenario-specific table may be differently programmable for different AGC operating scenarios.

[0027] FIG. 2 illustrates an exemplary receiver 200 with automatic gain control, according to some implementations of the present disclosure. In some implementations, receiver 200 may include a front end 202 for receiving a radio frequency (RF) signal, a low noise amplifier (LNA) 204 for amplifying the RF signal, a mixer 206 for converting the RF signal to an intermedia frequency (IF) signal, a baseband amplifier 208 for amplifying the IF signal to generate a baseband signal, an analog-to-digital converter (ADC) 210 for sampling the baseband signal, a demodulator 212, and an automatic gain controller (AGC) 214 for adjusting a gain of receiver 200.

[0028] In some implementations, front end 202 may be an antenna. The antenna receives a high-frequency signal (e.g., a millimeter wave) transmitted by an external communication partner of receiver 200. The high-frequency signal received by front end 202 is supplied to the high- frequency signal processing circuit, including LNA 204, mixer 206, and baseband amplifier 208. The high-frequency signal processing circuit amplifies the high-frequency signal received by front end 202 by using AGC 214. The high-frequency signal processing circuit converts the high- frequency signal received by front end 202 to a baseband signal by using a locally generated signal 216 in receiver 200. The baseband signal is supplied to ADC 210. LNA 204 amplifies the high- frequency signal received by front end 202 by using the gain of LNA 204 determined by AGC 214 and then supplies the high-frequency signal to a frequency-converting section, e.g., mixer 206. Mixer 206 down-converts the frequency of the high-frequency signal amplified by LNA 204 by using the locally generated signal in receiver 200 so as to convert the high-frequency signal to a baseband signal and then supplies the baseband signal to baseband amplifier 208. Baseband amplifier 208 amplifies the baseband signal supplied by mixer 206 by using gain for baseband amplifier 208 determined by AGC 214 and then supplies the baseband signal to ADC 210. ADC 210 converts the analog baseband signal amplified by baseband amplifier 208 to a digital baseband signal by quantizing the analog baseband signal and then supplies the digital baseband signal to demodulator 212.

[0029] In some implementations, AGC 214 may include a first gain state performed by a hardware implemented gain controller and a second gain state performed by a software implemented gain controller, and the second gain state is triggered after the first gain state. In other words, AGC 214 may include at least one hardware AGC state and at least one software AGC state. The hardware AGC state may allow the hardware triggered fast gain state transition with a symbol, e.g., about 30 to 70 microseconds, and the software AGC state may allow the gain state transition at the symbol boundary. Hence, AGC 214 may allow flexible mix and match of the hardware AGC and the software AGC to handle various scenarios.

[0030] FIG. 3 illustrates an exemplary state transition diagram 300 for performing a gain control in receiver 200, according to some implementations of the present disclosure. FIG. 4 illustrates an exemplary state transition table 400 for performing a gain control in receiver 200, according to some implementations of the present disclosure. FIGs. 5-6 illustrate an exemplary timing diagram 500 for performing a gain control in receiver 200, according to some implementations of the present disclosure. FIG. 7 illustrates a flowchart of an exemplary method 700 for performing a gain control in receiver 200. For the purpose of better describing the present disclosure, the state transition diagram for performing the gain control in receiver 200 in FIG. 3, the state transition table for performing a gain control in receiver 200, the timing diagram for performing a gain control in receiver 200 in FIGs 5-6, and method 700 for performing a gain control in receiver 200 in FIG. 7 will be discussed together. It is understood that the operations shown in method 700 are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIGs. 3-7.

[0031] In some implementations, AGC 214 is utilized in the communication of receiver 200 to adjust the RF signal received by front end 202 and make the received signal power observed at the output of ADC 210 in a desirable range to process without being affected by the quantization noise of ADC 210 or the signal saturation at the output of ADC 210. The measure points after ADC 210 may be used to measure the output power and the saturation of ADC 210 to detect the desired signal power accurately. In a cellular environment, since the signal power or the output of band interference may be dynamically changed even within a short time period, the AGC in receiver 200 can act swiftly to adjust the receiver gain and have the output signal level of ADC 210 in a desirable range, according to some implementations of the present disclosure.

[0032] In some implementations, the state machine of AGC 214 is designed with several main states 1, 2 . . ., n, which may be flexible and suitable for different state transitions, as shown in state transition diagram 300 in FIG. 3. In addition, the transition time between the main states of the state machine may be programable and may be chosen from a software programable table, as shown in state transition table 400 in FIG. 4. Since the state transitions are based on the programmable time, the state transitions may be triggered at any time that the user equipment wishes. For example, an operating scenario-specific table, including the information of transition time and the next state, may be programmable for different operating scenarios of AGC 214.

[0033] As shown in FIG. 3, the state machine of AGC 214 may include states 1, 2 ..., k, . . ., n, and each state may have a corresponding triggering time/event. In some implementations, the state machine of AGC 214 may further include an initial state before all state transitions or after all state transitions. In some implementations, after each state transition or between state transitions, the state machine of AGC 214 may further include a returning state. In some implementations, the state transitions may be triggered by a predefined event/trigger time (switching time), as shown in FIG. 4.

[0034] As shown in FIG. 3, in some implementations, after every state transition, the state may return to the returning state before performing the next state, and each state transition is triggered by either programmable trigger time or programmable event. In some implementations, the next state is independently programmable and may be irrespective of the current or previous state. Hence, the state machine of AGC 214 may have greater flexibility.

[0035] As shown in FIG. 4, in some implementations, the state transitions may be executed from event 0 to even N. In some implementations, each event may be triggered by a positive edge clock at a specified switching time, e.g., To, Ti, T2, . . ., Tk, . . ., TN. The switching time is software programmable as required by the specific operation scenario. In some implementations, at each event, the next state to be proceed is also software programmable. In some implementations, AGC 214 may go through the state transitions one by one, e.g., from the returning state or the initial state to state 1, . . . , state k, . . . , and to the initial state, at the defined specific trigger time, and eventually may enter the returning state or the initial state which can be programmed as the last entry of state transition table 400.

[0036] As shown in operation 702 of FIG. 7, the RF signal is processed by a conversion circuit to generate the baseband signal. In some implementations, the conversion circuit may include front end 202, LNA 204, mixer 206, and baseband amplifier 208. In some implementations, the RF signal is received by front end 202, e.g., the antenna, and then the RF signal may be amplified by LNA 204. Then, the RF signal is processed by the analog module to generate the baseband signal. In some implementations, the RF signal may be converted to the IF signal by mixer 206 and be amplified to generate the baseband signal by baseband amplifier 208. [0037] As shown in operation 704 of FIG. 7, the baseband signal is sampled by ADC 210. In some implementations, the measure points after ADC 210 may be used to measure the output power and the saturation of ADC 210 to detect the desired signal power accurately.

[0038] As shown in operation 706 of FIG. 7, the gain of the conversion circuit is adjusted with a gain controller, e.g., AGC 214, based on the baseband signal sampled by ADC 210. AGC 214 may include a state machine having a plurality of gain states, and the plurality of gain states comprises at least one hardware implemented gain state, and at least one software implemented gain state. FIGs. 5-6 disclose timing diagram 500 for the state transition in some implementations of AGC 214. In some implementations, timing diagram 500 may be the state transition of AGC 214 implemented for New Radio (NR) Synchronization Signal Block (SSB). It is understood that the trigger time illustrated in timing diagram 500 may be different from the trigger time illustrated in state transition table 400. [0039] As shown in FIG. 5, the state transition may be started from the initial state. At the switching time Ti, ADC 210 is turned on, and the state machine proceeds to the returning state. At the switching time T2, the state machine proceeds to a hardware AGC, and the output power of ADC 210 is measured at the same time. In some implementations, one hardware AGC may be implemented before the software AGC. In some implementations, more than one hardware AGCs may be implemented before the software AGC. In some implementations, the saturation of ADC 210 is also measured during the hardware AGC implementation period. In some implementations, between the different hardware AGC implementation periods, the state machine may proceed to the returning state.

[0040] The hardware AGC state may allow the hardware AGC to trigger fast gain state transition with a symbol, e.g., about 30 to 70 microseconds, and therefore the gain may settle fast. Then, after the hardware AGC implementation periods, the state machine proceeds to the returning state.

[0041] At the switching time T3, the state machine proceeds to a software AGC, as shown in FIG. 5. After the measurement of the symbol received signal strength indicator (RSSI) is completed, the state machine proceeds to the returning state. In some implementations, more than one software AGC may be implemented in the state machine. For example, as shown in FIGs. 5- 6, at the switching time T4, the state machine may proceed to another software AGC, and at the switching time T5, the state machine may proceed to a further software AGC. Then, at the switching time Te, the state machine may proceed back to the initial state.

[0042] In some implementations, the gain states in the state machine, including the hardware AGC and the software AGC, are sequentially switched based on a timetable, e.g., state transition table 400. The hardware AGC is proceeded before the software AGC to accelerate the state machine in receiver 200. In some implementations, state transition table 400 is programmed to define several switching times of the proceeding of different states. For example, a first switching time of triggering the hardware implemented gain state, e.g., the hardware AGC, and a second switching time of triggering the software implemented gain state, e.g., the software AGC. [0043] In some implementations, the plurality of gain states are sequentially switched based on predefined events defined in state transition table 400. For example, event 0, event 1, . . . , event k, . . . , event N, may be defined in state transition table 400, and these events may proceed sequentially. In some implementations, each event in state transition table 400 may proceed in different states. For example, event 0 and event 1 may be performed by the hardware AGC, and other events proceeded after event 1 may be performed by the software AGC, which is not limited here.

[0044] In some implementations, the plurality of gain states defined in state transition table 400 may include the initial state, and the initial state is triggered before the hardware implemented gain state, e.g., the hardware AGC, and the software implemented gain state, e.g., the software AGC. In some implementations, the plurality of gain states defined in state transition table 400 may include the returning state, and the returning state is triggered after performing each of the hardware implemented gain state and the software implemented gain state.

[0045] In some implementations, AGC 214 may control the gain of LNA 204 and baseband amplifier 208. In some implementations, during the operation of receiver 200, the gain state of LNA 204 and baseband amplifier 208 may be switched to the initial state, and the gain state of LNA 204 and baseband amplifier 208 may then be switched to the returning state at the first switching time Ti, as shown in FIG. 5. In some implementations, the first switching time Ti may align with a start of a first symbol of a synchronization signal block (SSB). Then, at the second switching time T2, the first hardware AGC may start to measure the output power of ADC 210, and after multiple measurements, the gain of LNA 204 and baseband amplifier 208 may be adjusted to a desired level.

[0046] At the third switching time T3, in some implementations, the analog gain of LNA 204 and baseband amplifier 208 may be fixed, and the state machine may be switched to the first software AGC to decode the successive symbols in the SSB. At the end of the SSB symbol, AGC 214 may message LNA 204 and baseband amplifier 208 to power down, and the state machine may be switched to the initial state.

[0047] In some implementations, the gain state of LNA 204 and baseband amplifier 208 may be switched to the returning state at a start of primary sync signal (PSS). In some implementations, the gain state of LNA 204 and baseband amplifier 208 may be switched to a second hardware AGC after the second switching time T2, and the second hardware AGC is different from the first hardware AGC. In some implementations, after the third switching time T3, the gain state of LNA 204 and baseband amplifier 208 may be switched to a second software AGC, at the fourth switching time T4, or may be further switched to a third software AGC, at the fifth switching time T5, as shown in FIGs. 5-6.

[0048] FIG. 8 illustrates a flowchart of a method 800 for performing a gain control in receiver 200. As shown in operation 802 of FIG. 8, the RF signal is received by receiver 200. In some implementations, the RF signal is received by front end 202 (e.g., the antenna) of receiver 200. As shown in operation 804 of FIG. 8, the RF signal is converted to the IF signal. As shown in operation 806 of FIG. 8, the IF signal is amplified to generate the baseband signal. The high- frequency signal received by front end 202 is supplied to the high-frequency signal processing circuit, including LNA 204, mixer 206, and baseband amplifier 208. The high-frequency signal processing circuit amplifies the high-frequency signal received by front end 202 by using AGC 214. The high-frequency signal processing circuit converts the high-frequency signal received by front end 202 to a baseband signal by using a locally generated signal in receiver 200.

[0049] As shown in operation 808 of FIG. 8, the baseband signal is supplied to ADC 210. LNA 204 amplifies the high-frequency signal received by front end 202 by using the gain of LNA 204 determined by AGC 214 and then supplies the high-frequency signal to a frequencyconverting section, e.g., mixer 206. Mixer 206 down-converts the frequency of the high-frequency signal amplified by LNA 204 by using the locally generated signal in receiver 200 so as to convert the high-frequency signal to a baseband signal and then supplies the baseband signal to baseband amplifier 208. Baseband amplifier 208 amplifies the baseband signal supplied by mixer 206 by using gain for baseband amplifier 208 determined by AGC 214 and then supplies the baseband signal to ADC 210. ADC 210 converts the analog baseband signal amplified by baseband amplifier 208 to a digital baseband signal by quantizing the analog baseband signal and then supplies the digital baseband signal to demodulator 212.

[0050] As shown in operation 810 of FIG. 8, the digital signal after ADC 210 is measured, and as shown in operation 812 of FIG. 8, the gain of receiver 200 is adjusted based on the measurement of the digital signal by sequentially triggering a hardware implemented gain state (the hardware AGC) and a software implemented gain state (the software AGC).

[0051] FIG. 9 illustrates a node 900 in the wireless network, according to some implementations of the present disclosure.

[0052] Each element in FIG. 1 may be considered node 900 of wireless network 100. Node 900 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 900 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 9, node 900 may include a processor 902, a memory 904, and a transceiver 906. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 900 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 900 may be implemented as a blade in a server system when node 900 is configured as core network element 106. Other implementations are also possible.

[0053] Transceiver 906 may include any suitable device for sending and/or receiving data, including receiver 200 described in FIG. 2. Node 900 may include one or more transceivers, although only one transceiver 906 is shown for simplicity of illustration. An antenna 908 is shown as a possible communication mechanism for node 900. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 900 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0054] As shown in FIG. 9, node 900 may include processor 902. Although only one processor is shown, it is understood that multiple processors can be included. Processor 902 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 902 may be a hardware device having one or more processing cores. Processor 902 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0055] As shown in FIG. 9, node 900 may also include memory 904. Although only one memory is shown, it is understood that multiple memories can be included. Memory 904 can broadly include both memory and storage. For example, memory 904 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 902. Broadly, memory 904 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0056] Processor 902, memory 904, and transceiver 906 may be implemented in various forms in node 900 for performing wireless communication functions. In some embodiments, processor 902, memory 904, and transceiver 906 of node 900 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 902 and memory 904 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 902 and memory 904 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 902 and transceiver 906 (and memory 904 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 908. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0057] In one aspect, a receiver is provided. The receiver includes a front end for receiving a radio frequency (RF) signal, a low noise amplifier (LNA) for amplifying the RF signal, a mixer for converting the RF signal to an intermedia frequency (IF) signal, a baseband amplifier for amplifying the IF signal to generate a baseband signal, an analog-to-digital converter (ADC) for sampling the baseband signal, and a gain controller for adjusting a gain of the receiver. The gain controller includes a first gain state performed by a hardware implemented gain controller and a second gain state performed by a software implemented gain controller, and the second gain state is triggered after the first gain state.

[0058] In some implementations, the gain controller includes a timetable to define a plurality of switching time to trigger the first gain state and the second gain state.

[0059] In some implementations, the gain controller includes a state machine having a plurality of gain states, and a transition between the plurality of gain states is sequentially performed accordingly to the plurality of switching time defined in the timetable.

[0060] In some implementations, the gain controller is switched from an initial state to a returning state at a first switching time. The first switching time aligns with a start of a first symbol of a synchronization signal block (SSB).

[0061] In some implementations, the gain controller measures an output power of the receiver at a second switching time and is switched from the returning state to the first gain state. [0062] In some implementations, the gain controller is switched from the first gain state to the returning state and is switched from the returning state to the second gain state at a third switching time.

[0063] In another aspect, a method for performing gain control in a receiver is provided. A radio frequency (RF) signal is processed by a conversion circuit to generate a baseband signal. The baseband signal is sampled by an analog-to-digital converter (ADC). A gain of the conversion circuit is adjusted with a gain controller based on the baseband signal sampled by the ADC. The gain controller includes a state machine having a plurality of gain states, and the plurality of gain states includes at least one hardware implemented gain state and at least one software implemented gain state.

[0064] In some implementations, the plurality of gain states are sequentially switched based on a timetable.

[0065] In some implementations, the timetable is programmed to define a first switching time of triggering the hardware implemented gain state and a second switching time of triggering the software implemented gain state.

[0066] In some implementations, the software implemented gain state is triggered after the hardware implemented gain state.

[0067] In some implementations, the plurality of gain states are sequentially switched based on predefined events.

[0068] In some implementations, a plurality triggering events are defined corresponding to each of the hardware implemented gain state and the software implemented gain state, and the plurality of gain states are switched when one of the predefined events is satisfied.

[0069] In some implementations, the plurality of gain states further includes an initial state, and the initial state is triggered before the hardware implemented gain state and the software implemented gain state. [0070] In some implementations, the plurality of gain states further includes a returning state, and the returning state is triggered after performing each of the hardware implemented gain state and the software implemented gain state.

[0071] In some implementations, the RF signal is amplified by a low noise amplifier (LNA), the RF signal is converted to an intermedia frequency (IF) signal, and the IF signal is amplified by a baseband amplifier to generate the baseband signal.

[0072] In some implementations, a gain state of the LNA and the baseband amplifier are switched to an initial state, and the gain state of the LNA and the baseband amplifier are switched to a returning state at a first switching time. The first switching time aligns with a start of a first symbol of a synchronization signal block (SSB).

[0073] In some implementations, a gain state of the LNA and the baseband amplifier are switched to an initial state, and the gain state of the LNA and the baseband amplifier are switched to a returning state at a start of primary sync signal (PSS).

[0074] In some implementations, the gain state of the LNA and the baseband amplifier are switched to a first hardware implemented gain state performed by the gain controller.

[0075] In some implementations, a gain state of the LNA and the baseband amplifier are switched to an initial state, the gain state of the LNA and the baseband amplifier are switched to a returning state at a first switching time, an output power of the ADC is measured at a second switching time, and the gain of the LNA and the baseband amplifier are adjusted according to a first hardware implemented gain state.

[0076] In some implementations, the gain state of the LNA and the baseband amplifier are switched to a second hardware implemented gain state performed by the gain controller. The second hardware implemented gain state is different from the first hardware implemented gain state.

[0077] In some implementations, the gain state of the LNA and the baseband amplifier are switched to the returning state, and the gain state of the LNA and the baseband amplifier are switched to a first software implemented gain state performed by the gain controller.

[0078] In some implementations, the gain state of the LNA and the baseband amplifier are switched to the returning state, and the gain state of the LNA and the baseband amplifier are switched to a second software implemented gain state performed by the gain controller.

[0079] In a further aspect, a method for adjusting a gain of a receiver is provided. A radio frequency (RF) signal is received. The RF signal is converted to an intermedia frequency (IF) signal. The IF signal is amplified to generate a baseband signal. The baseband signal is converted to a digital signal. The digital signal is measured. The gain of the receiver is adjusted based on a measurement of the digital signal by sequentially triggering a hardware implemented gain state and a software implemented gain state.

[0080] In some implementations, the gain of the receiver is settled by implementing the hardware implemented gain state in a symbol duration, and the gain of the receiver is adjusted by implementing the software implemented gain state at a symbol boundary.

[0081] In some implementations, a timetable is provided to define a plurality of switching time of triggering each of the hardware implemented gain state and the software implemented gain state.

[0082] In some implementations, a gain state of the receiver is switched to an initial state before triggering the hardware implemented gain state, and the gain state of the receiver is switched to a returning state at a first switching time, wherein the first switching time aligns with a start of a first symbol of a synchronization signal block (SSB).

[0083] In some implementations, the first switching time aligns a start of primary sync signal (PSS).

[0084] In some implementations, an output power of the receiver is measured at a second switching time.

[0085] In some implementations, the gain state of the receiver is switched to a first hardware implemented gain state based on the output power measured at the second switching time.

[0086] In some implementations, the gain state of the receiver is switched to a second hardware implemented gain state. The second hardware implemented gain state is different from the first hardware implemented gain state.

[0087] In some implementations, the gain state of the receiver is switched to the returning state, and the gain state of the receiver is switched to a first software implemented gain state at a third switching time.

[0088] In some implementations, the gain state of the receiver is switched to the returning state, and the gain state of the receiver is switched to a second software implemented gain state at a fourth switching time.

[0089] The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0090] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.