CLAIM FOR PRIORITY

[0001] This application is a continuation of and claims benefit of priority to U.S. Patent Application No. 63/269,607, filed on March 18, 2022, titled “APPARATUS AND METHODS FOR REDUCING WAFER BACKSIDE DAMAGE,” and which is incorporated by reference in its entirety.

BACKGROUND

[0002] Substrate processing tools are used to perform treatments such as deposition and etching of film on substrates like semiconductor wafers. For example, deposition may be performed to deposit a conductive film, a dielectric film, or other types of film using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), and/or other deposition processes. During deposition, wafer substrate is clamped down on a substrate support (e.g., a pedestal). The pedestal may hold the substrate by electrostatic clamping or by vacuum clamping facilitated by a chuck on the pedestal. In either mode, the wafer substrate is pressed against the chuck. In many processes, the wafer is thermally cycled to control deposition or etching chemistry on the exposed surface of the wafer substrate. Microscopic irregularities on the chuck surface may rub or scrape off small particles from the backside of the wafer substrate during thermal equilibration as the wafer expands or contracts. The particles may accumulate on the chuck, and transfer to subsequent wafer substrates during sequential processing of multiple wafers in the same tool. The contamination of wafer backsides by adventitious particle attachment may affect downstream processing. For example, backside particle contamination may affect quality of subsequent photolithography operations.

[0003] A common solution is to incorporate a plurality of contact-minimizing structures on the chuck surface, presenting a minimum contact area to a wafer clamped to the chuck, contact-minimizing structures may be in the form of small hemispherical domes or pillars for example, distributed on the chuck surface. The structures may minimize the contact surface area between the backside of the wafer substrate and the chuck. A wafer mounted on a chuck may rest on the contact-minimizing structures, which may also offset the wafer from the chuck surface. An advantage realized by the vertical offset between the wafer and chuck surface may be the reduction of debris formation, such as generation of large dust particles and microscopic particles of photoresist to be otherwise generated by contact with a flat surface. The number of point contact structures may be few. The total contact area of the structures may be restricted to a small fraction of the wafer area, for example, less than 1 1 While minimal contact area may be beneficial to mitigate particle generation, clamping forces may be magnified over the contact-minimizing structures, pressing the structures in the backside surface of the substrate. Often, the structures have a dome shape, presenting i single point of contact to the wafer backside. Clamping pressure may be very high at these contact points. For example, a resist coating or deposited metal or oxide or nitride film present on the wafer backside may be damaged by indentation or cracking metal or dielect films from the excess pressure due to the very small contact areas of the structures. A solution is needed for reducing damage caused by mesas while maintaining their benefits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The material described herein is illustrated by way of example and not by way limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions o some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified “ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, comer-rounding, and imperfei angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figt to indicate corresponding or analogous elements.

[0005] Fig. 1 illustrates a cross-sectional view of a wafer chuck assembly comprising mesas on a wafer chuck surface, according to at least one embodiment.

[0006] Fig. 2 illustrates a plan view of a first embodiment of a wafer chuck assembly comprising hexagonal mesas, according to at least one embodiment.

[0007] Fig. 3 illustrates a plan view of a wafer chuck assembly comprising a plurality round mesas, according to at least one embodiment.

[0008] Fig. 4 illustrates a plan view of a wafer chuck assembly comprising a plurality [0009] Fig. 5 illustrates a plan view of a wafer chuck assembly comprising a plurality wedge-shaped mesas in a symmetrical angular distribution, according to at least one embodiment.

[0010] Fig. 6 illustrates a plan view of a wafer chuck assembly comprising a plurality mesas in a logarithmically increasing radial distribution, according to at least one embodiment.

[0011] Fig. 7 illustrates a plan view of a wafer chuck assembly comprising a plurality mesas in a logarithmically decreasing radial distribution, according to at least one embodiment.

[0012] Fig. 8 illustrates a plan view of a wafer chuck assembly comprising a plurality mesas which have a logarithmic radial distribution and logarithmic progression of diamete according to at least one embodiment.

[0013] Fig. 9 illustrates a plan view of a wafer chuck assembly comprising a plurality mesas comprising tiled mesas, according to at least one embodiment.

[0014] Fig. 10 illustrates a cross-sectional view of a wafer process apparatus comprisi: a wafer chuck assembly comprising a plurality of mesas, according to at least one embodiment.

[0015] Fig. 11 illustrates a flow chart summarizing an exemplary method for using a wafer process apparatus, according to at least one embodiment.

DETAILED DESCRIPTION

[0016] At least one embodiment describes minimum contact area stand-off patterns fo reducing wafer backside damage. Here, numerous specific details are set forth, such as structural schemes, to provide a thorough understanding of at least one embodiment. It wil be apparent to one skilled in art that at least one embodiment may be practiced without the specific details. In other instances, well-known features, such as gas line tubing fittings, heating elements and snap switches, are described in lesser detail to not unnecessarily obscure an embodiment. Furthermore, it is to be understood that at least one embodiment shown in figures is illustrative representation and may be not necessarily drawn to scale.

[0017] In some instances, well-known methods and devices are shown in block diagra form, rather than in detail, to avoid obscuring present disclosure. Reference throughout thi disclosure. Thus, appearances of phrase “in an embodiment” or “at least one embodiment” “in one embodiment” or “some embodiments” in various places throughout this specificati are not necessarily referring to a same embodiment. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere particular features, structures, functions, or characteristics associab with two embodiments are not mutually exclusive.

[0018] Here, “coupled” and “connected,” along with their derivatives, may be used he to describe functional or structural relationships between components. These terms are not intended as synonyms for one another. Rather, in particular embodiments, “connected” mt be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. “Coupled” may be used to indicated that two or more elements a in either direct or indirect (with other intervening elements between them) physical, electri or in magnetic contact with one another, and/or that two or more elements co-operate or interact with one another (e.g., as in a cause an effect relationship).

[0019] Here, “over,” “under,” “between,” and “on” as used herein may generally refer a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. Unless these terms are modif with “direct” or “directly,” one or more intervening components or materials may be prese Similar distinctions are to be made in context of component assemblies. As used througho this description, and in claims, a list of items joined by “at least one of’ or “one or more ol can mean any combination of listed terms.

[0020] Here, “adjacent” here may generally refer to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

[0021] Unless otherwise specified in explicit context of their use, terms “substantially equal,” “about equal” and “approximately equal” may generally mean that there may be n< more than incidental variation between two things so described. Such variation may be typically no more than +/-10% of referred value.

[0022] To address at least limitations described herein, wafer chuck assembly embodiments comprising high-density mesa patterns are disclosed. Here, “mesa” may embodiment, mesa may have a substantially flat contact surface, affording a larger contact area than a point contact of a more conventional hemispherical structure. In at least one embodiment, while individual mesas may afford a very small contact area between wafer ; platen, when amassed in high-density patterns, collective contact area may be sufficient to reduce contact pressure due to clamping forces on individual mesas to below a critical levs above which damage backside layers may occur.

[0023] In at least one embodiment, threshold contact area may be at least 3% (e.g., between 3% and 90%) of total surface area of wafer chuck assembly to reduce clamping force load per individual mesa. Reduction of clamping force load per individual mesa may decrease wafer backside damage due to excessive load born by individual mesas. In at leas one embodiment, mesas comprise rounded or sloped leading edges between sidewalls and surfaces. In at least one embodiment, rounded leading top and/or side edges may reduce mesa-induced scratching and marring of backside wafer films or layers when wafers expai or contract during thermal cycling. Here, “rounded’ generally refers to top edges of mesas where a top contact surface and sidewalls intersect. In at least one embodiment, rounded edges may be characterized by a radius of curvature instead of a sharp angle. Here, “slope< in context of mesa top edges generally refers to edges that may have a transition extending an oblique angle between a substantially vertical sidewall and a substantially horizontal to surface.

[0024] Here, “wafer chuck” may generally refer to a structure comprising a plate or platen on which a wafer may be mounted and clamped. In at least one embodiment, clamp of wafer may be effectuated by vacuum clamping or by electrostatic clamping. Here, “vacuum clamping” may generally refer to a means of clamping a wafer substrate to a wal chuck by vacuum. Here, “electrostatic clamping” may generally refer to a means of clamp a wafer substrate to a wafer chuck by electrostatic force. In at least one embodiment, plate may comprise a surface having a substantially circular geometry. Here, “wafer chuck assembly” may generally refer to an assembly comprising a wafer chuck and may further include a column attached to wafer chuck, where column may house cables, wires, vacuui tubing, and gas lines that are fed to wafer chuck. Here, “wafer chuck surface” may general refer to a surface of a platen, part of wafer chuck on which a wafer substrate may be placei In at least one embodiment, wafer chuck surface may be substantially circular. Other suita q semiconductor wafer, such as a silicon wafer, generally has a disc shape. In at least one embodiment, diameter of a wafer may range between 3 cm and 50 cm.

[0025] In at least one embodiment, plurality of mesas may be distributed in a substantially uniform pattern over surface of a wafer chuck assembly. In at least one embodiment, number per unit area of mesas may be substantially constant over substantia] entire wafer chuck surface. In at least one embodiment, plurality of mesas has a non-unifo distribution pattern over wafer chuck surface. In at least one embodiment, number of mest per unit area may have a radially varying distribution over substantially entire wafer chucl surface. In at least one embodiment, plurality of mesas may have uniform contact surface area and/or shape. In at least one embodiment, mesas may have varying contact surface geometries (e.g., contact area size variations) over portions of wafer chuck surface. In at le one embodiment, for all mesa distribution patterns, combined area fraction of plurality of mesas may be at least 3% of wafer chuck surface area, hence, wafer surface area.

[0026] Fig. 1 illustrates a cross-sectional view of wafer chuck assembly 100, in accordance with at least one embodiment. In at least one embodiment, wafer chuck as semi 100 comprises a plurality of mesas 102 distributed on wafer chuck surface 104 of wafer chuck 106. In at least one embodiment, wafer chuck surface 104 may be substantially circular. Wafer chuck 106 may be seated on pedestal 108. In at least one embodiment, wal chuck assembly 100 may generally comprise wafer chuck 106 and pedestal 108. In at leasl one embodiment, mesas 102 may have a width wi. In at least one embodiment, width wi n range between 100 mils to 250 mils (e.g., approx. 2.50 mm to 6 mm). In at least one embodiment, mesas 102 may have a separation distance si between adjacent mesas 102. Ir some embodiments, sj may range between 100 mils to 1000 mils. In at least one embodim mesas 102 may have a z-height hi that may range between 10 mils (e.g., approx. 250 microns) to 100 mils (e.g., approx. 2.5 mm).

[0027] In at least one embodiment, mesas 102 may comprise top edges 110 and 112 between sidewalls 114 and 116 and contact surface 118. Here, “contact surface” may generally refer to an uppermost portion or top surface of mesas 102 (and of other mesa embodiments disclosed herein), which touches (e.g., contacts) an overlying substrate, suet semiconductor wafer. In at least one embodiment, contact surface may be interface with overlying substrate and mesa. In at least one embodiment, semiconductor wafer may have smooth or have a texture. In at least one embodiment, contact surfaces 118 of mesas 102 n have an area of contact with an overlying substrate, such as a semiconductor wafer. In at 1< one embodiment, for a plurality of mesas, total contact area with an overlying wafer substi may be calculated for example as contact area of an individual mesa multiplied by total number of mesas on a wafer chuck surface. In at least one embodiment, contact surface an of a plurality of mesas may be give as a percentage of surface area of a wafer chuck surfac [0028] In at least one embodiment, contact surfaces of disclosed mesas may be border by top edges. Here, “top edge” may generally refer to intersection of contact surface with mesa sidewall. In at least one embodiment, top edges are upper edges of mesa. In at least ( embodiment, top edges may be round or sloped to eliminate sharp edges that may con tri hr to damage of a wafer backside.

[0029] In at least one embodiment, top edges 110 and 112 may present an oblique or orthogonal angle to a radial direction of wafer chuck surface 104. In at least one embodim of wafer chuck assembly 100, backside 120 of wafer substrate 122 may be contacted to m( 102. In at least one embodiment, wafer chuck 106 may be heated to elevated temperatures thermal cycling of wafer substrate 122 during processing. In at least one embodiment, duri thermal cycling, wafer substrate 122 may expand and contract. In some embodiments, top edges 110 and 112 may be leading edges of mesas 102 relative to wafer backside 120. Her “leading edge” may generally refer to one or more top edges near contact surface of a mes In at least one embodiment, leading edge may be normal to or parallel to direction of them expansion or contraction of a wafer that may occur during thermal cycling. Because of rad symmetry of wafer, thermal expansion and contraction may generally occur along radial directions. In at least one embodiment, leading edge may be shaped by rounding, sloping < by other geometric design to avoid sharp edges, mitigating marring and scratching during thermal expansion and contraction of wafer.

[0030] In at least one embodiment, top edges 110 and 112 may be rounded or sloped t< mitigate scratching of layers or films on wafer backside 120. In at least one embodiment, t edges 110 and 112 may have at least one rounded edge having a suitable radius of curvatu n that permits sliding of mesas 102 over wafer backside 120. In at least one embodiment, edges 110 and 112 may extend around contact surface 118 of mesas 102.

[0031] In at least one embodiment, contact surface 118 may be substantially planar. In example. In at least one embodiment, a planar contact surface 118 may have a lower conta pressure on wafer backside 120 than a hemispherical or pointed surface.

[0032] Fig. 2 illustrates a plan view of wafer chuck assembly 200 comprising a plurali of hexagonal mesas 202 distributed on surface 204 of wafer chuck 205, in accordance witl least one embodiment. In at least one embodiment, wafer chuck 205 may have a diameter ranging between 100 mm to 300 mm, for example. In at least one embodiment, wafer chu< 205 may be seated on pedestal 108 as shown. In at least one embodiment, mesas 202 may arranged in a uniform pattern over wafer surface 204 as shown in figure. In at least one embodiment, mesas 202 are arranged in a hexagonal close-packed pattern, substantially filling circular wafer chuck surface 204.

[0033] Here, “close-packed” or “closed-packed distribution” may generally refer to geometrical arrangements to minimize spacing between substantially identical individual objects within an array of objects. In at least one embodiment, minimal spacing results in ; maximal packing density of array of identical objects within boundaries of a defined surfa or a volume. In at least one embodiment, “hexagonal close packed” may generally refer to two-dimensional packing geometry where an object in a plurality of objects may be surrounded by six other identical objects in such a way that six neighboring objects are centered at vertices of a symmetrical hexagon, with surrounded object at center of hexagoi In at least one embodiment, in a hexagonally close-packed array, a defined area may be maximally filled with identical objects. In at least one embodiment, objects may have circi or polygonal horizontal cross sections. In at least one embodiment, for maximal packing within a defined surface area or volume, circular objects (e.g., cylindrical pillars) may tou< at least at one point or have a closest spacing that may be 10% or less of diameter of circul objects. In at least one embodiment, sidewalls of polygonal objects may also touch or have closest spacing that may be 10% or less of width of object.

[0034] Here, dark lines between mesas 202 (e.g., shown as white hexagons) are spaces between adjacent mesas 202. In at least one embodiment, mesas 202 may fill between 709 and 90% of wafer chuck surface 204. In at least one embodiment, degree of surface fill mt depend on width W2 of mesas 202 and spacing S2 between sidewalls 206 of adjacent mesas 202, as shown in inset. In at least one embodiment, mesas 202 have a symmetrical hexago cross-section (e.g., mesas 202 having substantially equal polygonal cross sections and [0035] In at least one embodiment, other suitable polygonal symmetrical or non- symmetrical cross-sectional shapes (e.g., square, rectangular, parallelepiped or trapezoidal alone or in combination with other suitable polygonal shapes such as triangles, pentagons hexagons) may be employed. In at least one embodiment, hexagonal mesas 202 are equal! spaced by distance S2 from neighboring adjacent mesas 202 on all six sides. In at least one embodiment, mesas 202 are substantially symmetrical. For example, all six sidewalls 206 have length Li. In at least one embodiment, mesas 202 may be asymmetric. For example, < or more of sidewalls 206 may have a length that may be different from adjacent sidewalls same mesa 202 (not shown). In at least one embodiment, sidewalls 206 may be substantial non- vertical, having a slope.

[0036] In at least one embodiment, mesas 202 comprise contact surfaces 208. In some embodiments, contact surfaces 208 may be substantially planar as noted above for contact surface 118. In at least one embodiment, top edges 210 are rounded. In at least one embodiment, top edges 210 may have a radius of curvature n. In at least one embodiment, may be adjusted to optimize contact area of contact surfaces 208. In at least one embodimt vertices 212 are also rounded, for example, having a radius of curvature r?. In at least one embodiment, top edges 210 and vertices 212 may be rounded to mitigate damage to layers and/or films that may be on a wafer backside (e.g., backside 120).

[0037] In at least one embodiment, number of mesas 202 per unit area of wafer chuck surface 204 may be constant. In at least one embodiment, coverage of wafer chuck surface 204 by hexagonally close-packed mesas 202 may be approximately 70%. In at least one embodiment, area fraction of wafer chuck surface 204 that may be occupied by contact surfaces 208 may be controlled by adjusting space distance S2 and radius of curvature of rounded top edges 210. In at least one embodiment, increasing r2 may reduce contact area mesas 202. In at least one embodiment, while a close-packed pattern as that shown in Fig. may provide near maximal contact area, other less dense distribution patterns for mesas 2C may be employed to tailor contact area to a suitable value.

[0038] hi at least one embodiment, clamping loads may be generated by electrostatic clamping or vacuum clamping of a wafer substrate (e.g., wafer substrate 122) to wafer chr 205. In at least one embodiment, a particular area fraction of a wafer substrate (e.g., occup by contact surfaces 208 of mesas 202) may be optimized for reducing clamping load per be reduction of indentation or penetration of a soft photoresist layer on wafer backside ma be reduced or eliminated by providing a high contact area. In at least one embodiment, wh damage to backside films and layers may be reduced by increasing contact area, contact at may be optimized to mitigate generation of particles. In at least one embodiment, particles that may be created by friction between contact surfaces and wafer backside may be isolat between adjacent mesas 202. In at least one embodiment, mesas may have a height hi that may be optimized to separate contact surfaces 208 from wafer chuck surface 204. In at lea one embodiment, fe may range between 0.01 mm (10 microns) and 0.25 mm (250 micron; In at least one embodiment, particles may fall below contact surfaces 208, mitigating particulate contamination of backside surfaces.

[0039] In at least one embodiment, wafer chuck assembly 200 may be a vacuum wafei chuck assembly, comprising vacuum ports 214 on wafer chuck surface 204. Here, “vacuut port” may generally refer to a connection point in a vacuum line. In at least one embodime wafer chuck assembly 200 may include lift pin ports 216, from which lift pins (not shown may rise to lift a wafer substrate (e.g., wafer substrate 122, Fig. 1) from contact surfaces 2 In at least one embodiment, vacuum ports 214 may be arranged in a symmetrical pattern, such as hexagonal pattern shown in figure. In at least one embodiment, during operation o wafer chuck assembly 200, a wafer substrate (e.g., wafer substrate 122) may be placed on wafer chuck 205. In at least one embodiment, wafer substrate may be contacted to plurality mesas 202. In at least one embodiment, backside of substrate (e.g., wafer backside 120) m be offset from wafer chuck surface 204 by height hi of mesas 202. Vacuum clamping may created by suction of ambient gas through vacuum ports 214, creating a low pressure withi spaces in between mesas 202. In at least one embodiment, height hi of mesas 202, may be adjusted for optimal vertical offset of a wafer substrate for optimal vacuum clamping requiring adjustment of an open volume below substrate for a particular pressure different] between top and bottom sides of wafer substrate.

[0040] Fig. 3 illustrates a plan view of wafer chuck assembly 300, comprising a plural of mesas 302 distributed over surface 304 of wafer chuck 305, in accordance with at least embodiment. In at least one embodiment, wafer chuck 305 may have a diameter D> rangin between 100 mm to 300 mm, for example. In at least one embodiment, wafer chuck 305 rr be seated on pedestal 108, as shown. In at least one embodiment, mesas 302 may be be between 3% and 90%. In illustrated embodiment, mesas 302 are substantially identical (e.g., mesas 302 having substantially equal circular cross sections) cylindrical mesas or pillars having a circular horizontal cross-section having a diameter D2. In at least one embodiment, D2 may range between 100 and 300 mils (e.g., approx. 2.5 mm to 7.5 mm). I least one embodiment, other suitable round shapes (e.g., oval and/or elliptical) may be employed. In at least one embodiment, circular or round mesas may be combined with oth suitable round and/or polygonal shapes.

[0041] In at least one embodiment, mesas 302 may have a spacing S4 between neighboring mesas 302, as shown in inset. Spacing S4 may be adjusted to optimize contact surface area. In at least one embodiment, spacing S4 may range between 80 to 160 mils (e.j approx. 2 mm to 4 mm). In at least one embodiment, mesas 302 may have a z-height I13 between 0.01 mm and .25 mm.

[0042] In at least one embodiment, mesas 302 may comprise rounded top edges 310 between contact surface 308 and sidewall 306. In at least one embodiment, rounded top ed 310 may have a radius of curvature r4, as shown in inset. As noted above, radius of curvati r4 may be tailored for minimal impact on backside films or layers during thermal cycling c wafer substrate during processing. In at least one embodiment, simultaneously, radius of curvature may be adjusted for optimal area of contact surfaces 308.

[0043] In at least one embodiment, total contact area may be sum of contact surfaces 3 of all mesas 302. In at least one embodiment, wafer chuck surface 304 having a diameter 1 of approximately 300 mm (e.g., 11.2 in diameter, area 98.5 in ² ) may comprise, for exampl 2259 substantially identical mesas 302 having a center-to-center spacing S4 of approximate 230 mils (e.g., approx. 5.7 mm). In at least one embodiment, contact surface 308 (e.g., ha\ a diameter D2 of f 20 mils) of individual mesa 302 may have an area of 0.01 f in ² (e.g., approx. 7.1 mm ² ). In at least one embodiment, total area contacting a wafer substrate may approximately 25.5 in ² (e.g., approx. 164.5 cm ² ). In at least one embodiment, contact area fraction by mesas 302 may be approximately 26%, exceeding a threshold of 3%.

[0044] hi at least one embodiment, a pressure differential of 10 torr (e.g., 0,193 psi) between top side and backside of a wafer substrate clamped to wafer chuck assembly 300 may be developed over a wafer vacuum-clamped on wafer chuck assembly 300. In at least one embodiment, total atmospheric (e.g., clamping) load on wafer may be approximately ; 302 may be approximately 0.0084 pounds (e.g., approx. 3.8 grams, 0.76 psi). In at least on embodiment, a threshold pressure per mesa may be lower than 0.76 psi, for example.

[0045] Fig. 4 illustrates a plan view of wafer chuck assembly 400, in accordance with least one embodiment. In at least one embodiment, wafer chuck assembly 400 comprises a plurality of line mesas comprising a first subset comprising line mesas 402, a second subst comprising line mesas 404 and a third subset comprising line mesas 406. In at least one embodiment, collections of line mesas 402, 404, and 406 comprise subsets of plurality of mesas. In at least one embodiment, line mesas 402, 404, and 406 may be distributed in a polar geometry. Here, “polar geometry” may generally refer to an angular distribution (e.g in polar coordinates), where line mesas may be repeated at regular or irregular angles arou a circular surface. In at least one embodiment, line mesas 402-406 are shaped substantial!) lines having three different lengths. In at least one embodiment, mesas 402 have longest length, and mesas 406 have shortest length. In at least one embodiment, mesas 402, 404, a 406 are distributed symmetrically over surface 408 of wafer chuck 409. In at least one embodiment, while mesas 402, 404, and 406 are repeated in order at multiple angular intervals, they may be distributed in any suitable manner. In at least one embodiment, waf chuck 409 may be seated on pedestal 108, as shown. In at least one embodiment, wafer ch 409 may have a diameter Di ranging between 100 mm to 300 mm. In at least one embodiment, mesas 402, 404, and 406 are distributed in an angularly symmetrical (e.g., having substantially same angular separation in angular degrees) but radially non-uniform pattern, as shown. In at least one embodiment, density of mesas 402, 404 and 406 may increase toward periphery of wafer chuck surface 408 to support radially increasing clamp load, for example.

[0046] In at least one embodiment, mesas 402, 404, and 406 may be line-shaped structures, extending between radii Ri, R2. and R<- respectively. In at least one embodimen mesas 402 are longest of three mesa subsets, extending between radii Ri and Ri- In at least one embodiment, some mesas 402 are interrupted by vacuum ports 410. In at least one embodiment, mesas 404 have medium length, extending between radii Ri and R3. In at lea; one embodiment, mesas 406 are shortest of tree mesas, extending between radii Ri and R2 near periphery of wafer chuck surface 408.

[0047] In at least one embodiment, mesas 402, 404, and 406 may have substantially sa least one embodiment, mesas 404 are repeated every 30 degrees and are distributed betwec mesas 402. In at least one embodiment, mesas 406 repeat every 15 degrees between adj act mesas 402 and 404. In at least one embodiment, depending on width W4 and number of me desired, mesas (e.g., mesas 402, 404, and 406) may be placed at any suitable angular posit [0048] Fig. 5 illustrates a plan view of wafer chuck assembly 500, comprising a plural of wedge-shaped mesas 502 arranged in a symmetrical angular distribution around surface 504 of wafer chuck 505, in accordance with at least one embodiment. Plan view of Fig. 5 shows wafer chuck 505 seated on pedestal 108, according to at least one embodiment. In a least one embodiment, wafer chuck 505 may have a diameter Di ranging between 100 mm 300 mm. In at least one embodiment, mesas 502 are substantially wedge shaped, comprisii diverging sidewalls 506 fanning out towards periphery from a central region of surface 50' In at least one embodiment, mesas 502 may have a width that increases with increases with radial distance from center of surface 504. Here, “wedge shaped” may generally rel'ei a substantially triangular shape of an object. In at least one embodiment, a general definite of a wedge may be a triangular or trapezoidal shape that has non-parallel sidewalls subtending an angle between nonparallel sidewalls and a width that increases with distant from one end to another.

[0049] In at least one embodiment, mesas 502 are substantially identical. In some embodiments, sidewalls 506 and 507 of mesas 502 extend between radii R4 and R>. spanni a radial distance Rs-R4- In at least one embodiment, mesas 502 may be arranged in a symmetrical close-packed pattern as shown. In at least one embodiment, as shown in inset sidewalls 506 and 507 belonging to adjacent mesas 502a and 502b are also adjacent, separated by a distance gi. In at least one embodiment, mesas 502 may comprise contact surfaces 508 that may provide large contact area. In at least one embodiment, contact surli 508 may join sidewalls 506 and 507 by blunted top edges 509, which are shown as sloping transitions between sidewalls 506 and 507 and contact surfaces 508. In at least one embodiment, top edges 509 may be rounded edges, such as leading edges 210, shown in F 2.

[0050] In at least one embodiment, sidewalls 506 and 507 extend along radial vectors wafer chuck surface 504. In at least one embodiment, extension of sidewalls 506 and 507 along radial vectors may substantially eliminate or completely avoid scratching of a wafer of a wafer substrate clamped to wafer chuck assembly 500, radially extending top edges 51 of mesas 502 may be substantially parallel to direction of thermal expansion and contractu In at least one embodiment, by consequence, top edges 509 may not be prone to scratch a wafer backside during thermal expansion and contraction. In at least one embodiment, as mesas 502 may also undergo thermally-induced expansion and contraction during thermal cycling, coefficient of thermal expansion (CTE) of mesas 502 may be engineered to substantially match CTE of wafer so that relative motion between mesas 502 and a wafer may be minimized.

[0051] In at least one embodiment, wedge shape of mesas 502 may enable uniform rac as well as angular distribution of contact surface over wafer chuck surface 504. In at least embodiment, as clamping force over a wafer substrate (e.g., wafer substrate 122) may increase parabolically (e.g., as radius or diameter squared), fanning structure of mesas 502 may distribute clamping forces evenly over wafer surface as contact area also increases parabolically in radial direction.

[0052] Fig. 6 illustrates a plan view of wafer chuck assembly 600 comprising a plurali of mesas 602 distributed on surface 604 of wafer chuck 605, seated on pedestal 108 as shown, in accordance with at least one embodiment. In at least one embodiment, wafer chi 605 may have a diameter Di ranging between 100 mm to 300 mm. In at least one embodiment, mesas 602 are substantially identical. In at least one embodiment, mesas 602 may have circular horizonal cross-sections like mesas 302, described herein. In at least on< embodiment, mesas 602 have a logarithmic radial distribution. In at least one embodiment mesas 602 may be distributed along multiple concentric circles having a logarithmic radial spacing S4. In at least one embodiment, concentric circles may be grouped into several ann Here, “annulus” may generally refer to multiple circular portions of surface 604 extending between radii. Plural form of annulus is “annuli.” In at least one embodiment, logarithmic radial separation distance S4 may decrease substantially toward periphery of wafer chuck surface 604. In at least one embodiment, distribution of mesas 602 may be concentrated toward periphery of wafer chuck surface 604. In at least one embodiment, periphery of a wafer clamped to wafer chuck assembly 600 may have greatest contact area from concentrated distribution of outermost mesas 602. In at least one embodiment, inner regioi near center of wafer, having smallest clamping forces, also have proportionally smaller [0053] In at least one embodiment, angular distribution of mesa 602 may be substantie symmetric, as shown. In at least one embodiment, mesas 602 may repeat at angular increments of 15 degrees around wafer chuck surface 604, forming concentric circular distributions of mesas 602 along a logarithmic progress of radial distances. In at least one embodiment, at individual radii, mesas may have a uniform spacing ss in angular direction at least one embodiment, spacing ss may increase as radial distances increase toward periphery. In at least one embodiment, mesas 602 near periphery may repeat at smaller angular increments. In at least one embodiment, peripheral mesas 602 may repeat at angul increments of 7.5 degrees, as shown.

[0054] Fig. 7 illustrates a plan view of wafer chuck assembly 700 comprising a plurali of mesas 702 distributed over surface 704 of wafer chuck 705, in accordance with at least embodiment. In at least one embodiment, wafer chuck 705 may be seated on pedestal 108, shown. In at least one embodiment, wafer chuck 705 may have a diameter D- ranging between 100 mm to 300 mm. In at least one embodiment, mesas 702 are substantially identical, having a circular horizontal cross section of uniform diameter, as illustrated in F 2. In at least one embodiment, mesas 702 may have a polygonal horizonal cross section. [0055] In at least one embodiment, mesas 702 are radially distributed in an increasing logarithmic progression. In at least one embodiment, radial separation distance se may increase substantially logarithmically toward periphery of wafer chuck surface 704. In at I one embodiment, number of mesas 702 per unit area may be concentrated toward center o wafer chuck surface 704, diminishing toward periphery. In at least one embodiment, clamping forces may be stronger near center of clamped wafer. In at least one embodimen height clearance (e.g., z-height fo or fe) of mesas 702 is small (e.g., less than 10 mils), a radial pressure differential may exist while vacuum pumping is active. In at least one embodiment, pressure near center of wafer chuck surface 704 may be lower than at periph increasing clamping forces closer to center of a wafer substrate than at periphery.

[0056] In at least one embodiment, mesas 702 may have a uniform angular distributioi For example, mesas 702 may repeat at angular increments of 15 degrees uniformly around wafer chuck surface 704, as shown. In at least one embodiment, spacing ^/between anguk adjacent mesas 702 may be increase logarithmically toward periphery.

[0057] Fig. 8 illustrates a plan view of wafer chuck assembly 800 comprising a plurali between 100 mm to 300 mm. In at least one embodiment, mesas 802 are substantially cylindrical, having a circular horizontal cross section of diameter D<. In at least one embodiment, ? increases in a logarithmic progression toward periphery. Here, “logarithn progression” may generally refer to an increase in diameter of mesas that follow a logarithmic relationship with radial position of mesa. In at least one embodiment, a doubli of distance from center of chuck surface of position of a mesa corresponds to a 30% increi in diameter of mesa. In at least one embodiment, mesas 802 are concentrically arranged in uniform angular distribution having an angular increment of 15 degrees between concentri mesas 802.

[0058] In at least one embodiment, mesas 802 may be arranged along logarithmically spaced concentric circles having a logarithmic progression of center-to-center spacing ss. ] at least one embodiment, ss increases logarithmically toward periphery. In at least one embodiment, diameters D3 of concentric mesas 802 increase in a logarithmic progression toward periphery of wafer chuck surface 804, as shown. In at least one embodiment, all mesas 802 having same diameter D3 may be arranged on one concentric circle. At progressively increasing radial distances, mesas having same diameter D3 may be arranger along concentric circles. In at least one embodiment, while a logarithmic progression in be diameter D3 and radial spacing ss is implemented, other suitable non-linear and/or linear relationships may be equally employed.

[0059] In at least one embodiment, mesas 802 may have a uniform angular distributioi around wafer chuck surface 804. In at least one embodiment, mesas may repeat at angular increments of 15 degrees, resulting in a linear spacing S9 between adjacent mesas 802.

[0060] In at least one embodiment, clamping loads on mesas 802 from a wafer substra may increase parabolically (e.g., as wafer radius squared) toward periphery. In at least one embodiment, as diameter D3 of mesas 802 may be related to area of contact surfaces 806, ; logarithmic increase of contact area (e.g., an increasing logarithmic progression of diameu D3) may approximately track parabolic increase in load. In at least one embodiment, clamping loads may be evenly distributed among mesas 802. In at least one embodiment, diameters D3 may be optimized to tailor a particular clamping load profile.

[0061] Fig. 9 illustrates a plan view of wafer chuck assembly 900, in accordance with least one embodiment. In at least one embodiment, wafer chuck assembly 900 comprises E may be seated on pedestal 108, as shown. In at least one embodiment, wafer chuck 901 m; have a diameter Di ranging between 100 mm to 300 mm.

[0062] In at least one embodiment, mesas 902 - 911 may be tiled over wafer chuck surface 912. Contact surfaces of mesas 902-911 are shown, in accordance with at least one embodiment. In at least one embodiment, individual mesas are separated from neighboring mesas by a relatively narrow gap, defined below. In at least one embodiment, plurality of mesas may be divided into a first plurality of mesas, a second plurality of mesas, a third plurality of mesas, and a fourth plurality of mesas. In at least one embodiment, first plurali of mesas comprises a first subset comprising collections of mesas 902. In at least one embodiment, second plurality of mesas comprises a second subset comprising a collection mesas 904. In at least one embodiment, third plurality of mesas comprises a third subset comprising a collection of mesas 906. In at least one embodiment, fourth plurality of mesa comprises a fourth plurality comprising a collection of mesas 908, 910, and 911. In at leas one embodiment, first, second, third and fourth subsets comprising mesas 902 904, 906, 91 910, and 911 may be respectively distributed within concentric annuli on wafer chuck surf 912.

[0063] In at least one embodiment, individual mesas 902 may comprise sidewalls 914 and 915 that extend along a first radial direction and a second radial direction, respective!) In at least one embodiment, radial directions, defined by polar coordinates r and q, whereii is a radius and q is an angle, may repeat at substantially equal angular intervals qo for example, where qo may range between 15 and 60 degrees. In at least one embodiment, rad directions may generally be located at any angular position on wafer chuck surface 912. H “radial direction” may generally refer to a line or direction that extends along an imaginar radial line passing through center of wafer chuck surface 912. In at least one embodiment, radial direction may be a radial vector having coordinates r and q, for example, extending from center of wafer chuck surface to circumference.

[0064] In at least one embodiment, sidewalls 914 and 915 extend a first radial distance between center of wafer chuck surface and a first radius /? ,. In at least one embodiment, fij and second radial directions may have a first angular separation on wafer chuck surface, fe example, occurring every 60 degrees around wafer chuck surface 912, comprising six mes 902. separation, for example, repeated every 20 degrees around wafer chuck surface 912. In at least one embodiment, sidewalls 916 or 917 of every third mesa 904 may be aligned with sidewalls 914 and 915 of individual mesas 902. In at least one embodiment, sidewalls 916 and 917 may extend over a second radial distance between radii Re and R , where second radial distance is R7 - Re-

[0066] In at least one embodiment, individual mesas 906 may comprise sidewalls 918 and 919 that extend along a fifth radial direction and a sixth radial direction, respectively, at least one embodiment, fifth and sixth radial directions may have a third angular separati for example, repeated every 20 degrees around wafer chuck surface 912. In at least one embodiment, sidewalls 918 and 919 may align with sidewalls 916 and 917 of mesas 904. 1 at least one embodiment, sidewalls 918 and 919 may extend over a third radial distance extending between radii R7 and Re, where third radial distance is Re - Re.

[0067] In at least one embodiment, individual mesas 908 may comprise sidewall 920 t extends along a seventh radial direction and sidewall 921 that extends along a first non- diametric chord 927, indicated by dashed line labelled 927. In at least one embodiment, nc diametric chord 927 may extend at a first oblique angle relative to seventh radial direction Here, “non-diametric chord” may generally refer to a chord of circular wafer chuck surl'ac 912 that extends at oblique angles relative to any radial direction that passes through cente wafer chuck surface 912. In at least one embodiment, a non-diametric chord does not pass through center of wafer chuck surface 912. In at least one embodiment, sidewalls 920 and 921 may extend a fourth radial distance extending between radii Re and Re, where fourth radial distance is R9 - Rs- R9 may extend substantially from center of wafer chuck surface ¹ to circumference of wafer chuck surface 912.

[0068] In at least one embodiment, individual mesas 910 may comprise sidewall 922 1 extends along an eighth radial direction, and sidewall 923 that extends along a second non diametric chord 929, indicated by dashed line labeled 929. In at least one embodiment, noi diametric chord 929 may extend at a second oblique angle relative to eighth radial directio In at least one embodiment, second non-diametric chord 929 may be reflected across a mil plane into first non-diametric chord 927, where first oblique angle may be equal to second oblique angle with respect to mirror plane cutting through diameter of wafer chuck surface 912. In at least one embodiment, like sidewalls 920 and 921, sidewalls 922 and 923 may a [0069] In at least one embodiment, individual mesas 911 are triangular tiles sandwicht between mesas 908 and 910. In at least one embodiment, individual mesas 911 may compj sidewall 924 extending along first non-diametric chord 927, and may be adjacent and para to sidewall 921 of mesa 908. In at least one embodiment, mesas 911 may also comprise sidewall 925 extending along second non-diametric chord 929, and may be adjacent and parallel to sidewall 922 of mesa 910. In at least one embodiment, side alls 924 and 925 rr be seen to intersect at radius Rs, and diverge along non-diametric chords 927 and 929. In a least one embodiment, sidewalls 924 and 925 also extend between radii Rs and Rg.

[0070] In at least one embodiment, mesas 902-911 may comprise leading edges 926, 9 930, 932, 934 and 936, respectively, corresponding to mesas 902, 904, 906, 908, 910, and 911. In at least one embodiment, leading edges 926, 928, 930, 932, 934 and 936 may folio concentric circular arcs at increasing radial distances Rg, R?, Rs, and Rg, as shown.

[0071] In at least one embodiment, inset in Fig. 9 shows a cross-sectional view taken through adjacent mesas 906a and 906b, showing sidewalls 918 and 919 separated by spaci distance g2, in accordance with at least one embodiment. In at least one embodiment, mest 906a and 906b comprise blunted top edges 936 and 938 that are sloped. In other embodiments, top edges 936 and 938 may be rounded. In at least one embodiment, all of mesas 902-911 may comprise blunted top edges similar or identical to top edges 936 and S [0072] Fig. 10 illustrates a cross-sectional view of wafer processing apparatus 1000, ii accordance with at least one embodiment. In at least one embodiment, wafer processing apparatus 1000 comprises wafer chuck assembly 100 within wafer processing chamber 10 Here, “wafer processing chamber” may generally refer to a high vacuum chamber in whic] wafer substrate may be introduced for processing operations. In at least one embodiment, wafer processing chamber may comprise components such as a wafer chuck for holding wafer substrate. In at least one embodiment, wafer processing chamber 1002 may compris an antechamber (not shown) through which wafer substrate 122 may be introduced. In at 1 one embodiment, wafer processing chamber 1002 may comprise a lid that may be opened closed to introduce and remove wafer substrate 122. Here, “wafer processing apparatus” generally refers to a semiconductor processing tool comprising a vacuum chamber, in whl a wafer substrate may be placed for processing.

[0073] In at least one embodiment, wafer chuck 106 may be seated within pedestal 10! wafer chuck surface f 04. In at least one embodiment, wafer substrate 122 may be mounter on wafer chuck assembly 100 as shown. In at least one embodiment, wafer backside 120 n be contacted to mesas 102. In at least one embodiment, mesas comprise contact surfaces 1 that may contact at least 20% of area of wafer backside 120. In at least one embodiment, wafer chuck assembly 100 may comprise electrodes 1004 embedded within wafer chuck surface for electrostatic clamping (ESC) of wafer substrate 122 to mesas 102. Here, “electrodes” may generally refer to metallic structures that are electrically coupled to a voltage or power source. In at least one embodiment, “electrodes” may be contact electrod for sparking and maintaining a plasma or may be clamping electrodes for electrostatic clamping of a wafer on a wafer chuck. In at least one embodiment, wafer chuck assembly may alternatively comprise one or more vacuum ports 1006 for vacuum clamping of wafei substrate 122 to mesas 102. In at least one embodiment, mesas 102 may contact at least a threshold percentage (e.g., at least 3%) of wafer backside 120.

[0074] Fig. 11 illustrates flow chart 1100 summarizing an exemplary method for usinj wafer processing apparatus 1000, in accordance with at least one embodiment. In at least c embodiment, at operation 1102, a wafer substrate (e.g., wafer substrate 122) is mounted within a process chamber comprising a wafer chuck assembly (e.g., wafer chuck assembly 100 within wafer processing chamber 1002). In at least one embodiment, wafer may be mounted on a wafer chuck surface comprising a plurality of mesas (e.g., mesas 102 distributed on wafer chuck surface 104). In at least one embodiment, wafer has a structure layer or a film of a dielectric or photoresist on wafer backside, or side of wafer that may b< contacted by plurality of mesas. In at least one embodiment, plurality of mesas may contac least 3% (e.g., 3% - 90%) of wafer substrate. In at least one embodiment, plurality of mes may be distributed over wafer chuck surface to evenly distribute clamping forces. In at lea one embodiment, by such a distribution, pressure over individual mesas due to a clamped wafer may be reduced below a threshold level.

[0075] In at least one embodiment, at operation 1104, wafer substrate may be clamped electrostatically by an ESC chuck as described above, or by vacuum applied to ports in wa chuck surface. In at least one embodiment, clamping forces may be controlled by adjusting voltages of ESC electrodes or by adjusting a pressure differential between wafer chuck surface below wafer substrate and top surface of wafer substrate. [0077] Example 1 : A wafer chuck assembly, comprising: a wafer chuck comprising a surface having a substantially circular geometry, the surface having a center and a first are and a plurality of mesas distributed over the surface of the wafer chuck, wherein individua ones of the plurality of mesas extend a height above the surface of the wafer chuck, where the individual ones of the plurality of mesas comprise a contact surface, and wherein a sec area substantially equals a sum of an area of the contact surface of the individual ones of tl plurality of mesas is at least 3% of the first area.

[0078] Example 2: Wafer chuck assembly of Example 1 , wherein the individual ones < the plurality of mesas comprise at least one leading edge that is rounded or sloped.

[0079] Example 3 : Wafer chuck assembly of Example 1, wherein the second area is between 3% and 90% of the first area.

[0080] Example 4: Wafer chuck assembly of Example 1, wherein the height is betwee: 0.01 mm and 0.25 mm.

[0081] Example 5 : Wafer chuck assembly of Example 1, wherein the individual ones < the plurality of mesas comprise a substantially circular or polygonal cross section.

[0082] Example 6: Wafer chuck assembly of Example 5, wherein the individual ones < the plurality of mesas have a substantially equal diameter.

[0083] Example 7: Wafer chuck assembly of Example 5, wherein a diameter of the individual ones of the plurality of mesas increases with an increase in radial distance alorq the surface.

[0084] Example 8: Wafer chuck assembly of Example 8, wherein the individual ones < the plurality of mesas comprise a substantially polygonal plan view cross section, and wherein the individual ones of the plurality of mesas comprise substantially equal periphei dimensions.

[0085] Example 9: Wafer chuck assembly of Example 9, wherein the substantially polygonal plan view cross section is substantially hexagonal.

[0086] Example 10: The wafer chuck assembly of Example 10, wherein the individual ones of the plurality of mesas are arranged in a close-packed distribution over the surface, and wherein adjacent individual ones of the plurality of mesas have a substantially equal pitch between adjacent individual ones of the plurality of mesas.

[0087] Example 11 : Wafer chuck assembly of Example 10, wherein adjacent individu; [0088] Example 12: Wafer chuck assembly of Example 12, wherein a radial distri buti < of a number of individual ones of the plurality of mesas per unit area decreases from the center to a periphery of the surface.

[0089] Example 13: Wafer chuck assembly of Example 10, wherein adjacent individu; ones of the plurality of mesas have a pitch that decreases with an increase in radial distanc along the surface

[0090] Example 14: Wafer chuck assembly of Example 14, wherein a radial di stri buti < of a number of individual ones per unit area of surface increases from the center to a periphery of the surface.

[0091] Example 15: Wafer chuck assembly of Example 1, wherein the individual one, the plurality of mesas comprise a wedge, wherein the wedge comprises a first sidewall tha extends from a central region of the surface to a periphery of the surface and a second sidewall that extends from the central region to the periphery of the surface, and wherein t first sidewall of a first individual one of the plurality of mesas is adjacent to a second sidewall of a second individual one of the plurality of mesas.

[0092] Example 16: Wafer chuck assembly of Example 1, wherein first individual one of the plurality of mesas are first line mesas that are distributed in a first polar geometry oi the surface, wherein individual ones of the first line mesas extend a first radial distance ak first radial directions on the surface, and wherein the first radial distance extends from substantially a center of the surface to substantially a periphery of the surface.

[0093] Example 17 : Wafer chuck assembly of Example 1 , wherein first individual one of the plurality of mesas are first line mesas that are distributed in a first polar geometry oi the surface, wherein individual ones of the first line mesas extend a first radial distance ak first radial directions on the surface, and wherein the first radial distance extends from substantially a center of the surface to substantially a periphery of the surface.

[0094] Example 18: Wafer chuck assembly of Example 16, wherein second individual ones of the plurality of mesas are second line mesas that are distributed in a second polar geometry on the surface, wherein individual ones of the second line mesas extend a secoiic radial distance along second radial directions on the surface, and wherein the second radia distance extends between substantially the first radial distance and substantially the periph of the surface, and wherein the second radial distance is less than the first radial distance [0096] Example 20: Wafer chuck assembly of Example 19, wherein the individual one of the first line mesas are separated from one another by a first angle, wherein individual c of the second line mesas are separated from one another by a second angle, and wherein individual ones of the thrid line mesas are separated from one another by a thrid angle. [0097] Example 21 : Wafer chuck assembly of Example 20, wherein the first angle is substantially equal to the second angle, and wherein the second angle is substantially equa the third angle

[0098] Example 22: Wafer chuck assembly of Example 1 , wherein a first plurality of mesas comprises a first subset of the plurality of mesas, wherein individual ones of the fin plurality of mesas comprise a first sidewall and a second sidewall, wherein the first sidewt extends along a first radial direction on the surface, wherein the second sidewall extends along a second radial direction on the surface, and wherein the first sidewall and the secon sidewall extend between a center of the surface to a first radial distance.

[0099] Example 23: Wafer chuck assembly of Example 22, wherein a second plurality mesas comprises a second subset of the plurality of mesas, wherein individual ones of the second plurality of mesas comprise a third sidewall and a fourth sidewall, wherein the thin sidewall extends along a third radial direction on the surface, wherein the fourth sidewall extends along a fourth radial direction on the surface, and wherein the third sidewall and tl fourth sidewall extend between the first radial distance and a second radial distance.

[00100] Example 24: Wafer chuck assembly of Example 23, wherein a third plurality o mesas comprises a third subset of the plurality of mesas, wherein individual ones of the th: plurality of mesas comprise a fifth sidewall and a sixth sidewall, wherein the fifth sidewall extends along a fifth radial direction on the surface, wherein the sixth sidewall extends alo a sixth radial direction on the surface, and wherein the fifth sidewall and the sixth sidewall extend between the second radial distance and a third radial distance.

[00101] Example 25: Wafer chuck assembly of Example 24, wherein a fourth plurality mesas comprises a fourth subset of the plurality of mesas, wherein: a first individual ones the fourth subset of mesas comprising: a seventh sidewall that extends along a seventh rad direction; and an eighth sidewall that extends along a first non-diametric chord of the surface, wherein the first non-diametric chord extends at a first oblique angle relative to th seventh radial direction, and wherein the seventh and eighth sidewalls extend between the second non-diametric chord extends at a second oblique angle relative to the ninth radial direction, and wherein the ninth and tenth sidewalls extend between the third radial distant and the fourth radial distance; and a third individual ones of the fourth subset of mesas between the first individual ones and the second individual ones of mesas, wherein the thii individual ones of the fourth subset of mesas comprise: an eleventh sidewall, wherein the eleventh sidewall is adjacent and parallel to the eighth sidewall; and a twelfth sidewall, wherein the twelfth sidewall is adjacent and parallel to the tenth sidewall, wherein the eleventh sidewall and twelfth sidewall intersect at the third radius and extend to the fourth radius.

[00102] Example 26: A wafer processing apparatus, comprising: a wafer processing chamber comprising a wafer chuck assembly, the wafer chuck assembly comprising: a wa chuck comprising wafer chuck surface having a substantially circular geometry, the wafer chuck surface having a first area; and a plurality of mesas distributed over the wafer chuck surface, wherein individual ones of the plurality of mesas extend a height above the wafer chuck surface, and wherein the plurality of mesas comprises a second area that is at least about a threshold percentage of the first area.

[00103] Example 27 : Wafer processing apparatus of Example 26, wherein the wafer chi comprises one or more electrodes operable to electrostatically clamp a wafer substrate to ti wafer chuck.

[00104] Example 28: Wafer processing apparatus of Example 26, wherein the wafer chi comprises one or more vacuum ports operable to vacuum clamp a wafer substrate to the wafer chuck.

[00105] Example 29: A method for using a wafer processing apparatus, the method comprising: mounting a wafer substrate on a wafer chuck comprising a wafer chuck surfac comprising a substantially circular geometry, wherein the wafer chuck surface has a first a and a plurality of mesas distributed over the wafer chuck surface, wherein the plurality of mesas has a second area that is at least about a threshold percentage of the first area; and clamping the wafer substrate to the wafer chuck surface, wherein individual ones of the plurality of mesas contact at least the threshold percentage of a surface of the wafer such ti pressure over the individual ones of the mesas from the clamped wafer substrate is below ; threshold pressure. [00107] Example 31: Method of Example 29, wherein clamping the wafer substrate to t wafer chuck surface comprises electrostatically clamping the wafer substrate to the wafer chuck surface.

[00108] Example 32: Method of Example 29, wherein clamping the wafer substrate to t wafer chuck surface comprises vacuum clamping the wafer substrate to the wafer chuck surface.