APPARATUS, SYSTEM, AND METHOD OF COMPILING CODE FOR A PROCESSOR

CROSS REFERENCE

[0001] This Application claims the benefit of and priority from US Provisional Patent Application No. 63/415,309 entitled “APPARATUS, SYSTEM, AND METHOD OF VECTOR PROCESSING”, filed October 12, 2022, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

[0002] A compiler may be configured to compile source code into target code configured for execution by a processor.

[0003] There is a need to provide a technical solution to support efficient processing functionalities.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity of presentation. Furthermore, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. The figures are listed below.

[0005] Fig. 1 is a schematic block diagram illustration of a system, in accordance with some demonstrative aspects.

[0006] Fig. 2 is a schematic illustration of a compiler, in accordance with some demonstrative aspects.

[0007] Fig, 3 is a schematic illustration of a vector processor, in accordance with some demonstrative aspects.

[0008] Fig. 4 is a schematic flow-chart illustration of a method of compiling code for a processor, in accordance with some demonstrative aspects.

[0009] Fig. 5 is a schematic illustration of a product, in accordance with some demonstrative aspects.

DETAILED DESCRIPTION

[00010] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of some aspects. However, it will be understood by persons of ordinary skill in the art that some aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, units and/or circuits have not been described in detail so as not to obscure the discussion.

[00011] Some portions of the following detailed description are presented in terms of algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art.

[00012] An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities capture the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

[00013] Discussions herein utilizing terms such as, for example, “processing”, “computing”, “calculating”, “determining”, “establishing”, “analyzing”, “checking”, or the like, may refer to operation(s) and/or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and/or transform data represented as physical (e.g., electronic) quantities within the computer’s registers and/or memories into other data similarly represented as physical quantities within the computer’s registers and/or memories or other information storage medium that may store instructions to perform operations and/or processes.

[00014] The terms “plurality” and “a plurality”, as used herein, include, for example, “multiple” or “two or more”. For example, “a plurality of items” includes two or more items.

[00015] References to “one aspect”, “an aspect”, “demonstrative aspect”, “various aspects” etc., indicate that the aspect(s) so described may include a particular feature, structure, or characteristic, but not every aspect necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in one aspect” does not necessarily refer to the same aspect, although it may.

[00016] As used herein, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[00017] Some aspects, for example, may capture the form of an entirely hardware aspect, an entirely software aspect, or an aspect including both hardware and software elements. Some aspects may be implemented in software, which includes but is not limited to firmware, resident software, microcode, or the like.

[00018] Furthermore, some aspects may capture the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For example, a computer-usable or computer-readable medium may be or may include any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[00019] In some demonstrative aspects, the medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium.

[00020] In some demonstrative aspects, a data processing system suitable for storing and/or executing program code may include at least one processor coupled directly or indirectly to memory elements, for example, through a system bus. The memory elements may include, for example, local memory employed during actual execution of the program code, bulk storage, and cache memories which may provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

[00021] In some demonstrative aspects, input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) may be coupled to the system either directly or through intervening I/O controllers. In some demonstrative aspects, network adapters may be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices, for example, through intervening private or public networks. In some demonstrative aspects, modems, cable modems and Ethernet cards are demonstrative examples of types of network adapters. Other suitable components may be used.

[00022] Some aspects may be used in conjunction with various devices and systems, for example, a computing device, a computer, a mobile computer, a non-mobile computer, a server computer, or the like.

[00023] As used herein, the term "circuitry" may refer to, be part of, or include, an Application Specific Integrated Circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated or group), and/or memory (shared. Dedicated, or group), that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some aspects, some functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some aspects, circuitry may include logic, at least partially operable in hardware.

[00024] The term “logic” may refer, for example, to computing logic embedded in circuitry of a computing apparatus and/or computing logic stored in a memory of a computing apparatus. For example, the logic may be accessible by a processor of the computing apparatus to execute the computing logic to perform computing functions and/or operations. In one example, logic may be embedded in various types of memory and/or firmware, e.g., silicon blocks of various chips and/or processors. Logic may be included in, and/or implemented as part of, various circuitry, e.g., processor circuitry, control circuitry, and/or the like. In one example, logic may be embedded in volatile memory and/or non-volatile memory, including random access memory, read only memory, programmable memory, magnetic memory, flash memory, persistent memory, and the like. Logic may be executed by one or more processors using memory, e.g., registers, stuck, buffers, and/or the like, coupled to the one or more processors, e.g., as necessary to execute the logic.

[00025] Reference is now made to Fig. 1, which schematically illustrates a block diagram of a system 100, in accordance with some demonstrative aspects.

[00026] As shown in Fig. 1, in some demonstrative aspects system 100 may include a computing device 102.

[00027] In some demonstrative aspects, device 102 may be implemented using suitable hardware components and/or software components, for example, processors, controllers, memory units, storage units, input units, output units, communication units, operating systems, applications, or the like.

[00028] In some demonstrative aspects, device 102 may include, for example, a computer, a mobile computing device, a non-mobile computing device, a laptop computer, a notebook computer, a tablet computer, a handheld computer, a Personal Computer (PC), or the like.

[00029] In some demonstrative aspects, device 102 may include, for example, one or more of a processor 191, an input unit 192, an output unit 193, a memory unit 194, and/or a storage unit 195. Device 102 may optionally include other suitable hardware components and/or software components. In some demonstrative aspects, some or all of the components of one or more of device 102 may be enclosed in a common housing or packaging, and may be interconnected or operably associated using one or more wired or wireless links. In other aspects, components of one or more of device 102 may be distributed among multiple or separate devices.

[00030] In some demonstrative aspects, processor 191 may include, for example, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), one or more processor cores, a single-core processor, a dual-core processor, a multiple-core processor, a microprocessor, a host processor, a controller, a plurality of processors or controllers, a chip, a microchip, one or more circuits, circuitry, a logic unit, an Integrated Circuit (IC), an Application-Specific IC (ASIC), or any other suitable multipurpose or specific processor or controller. Processor 191 may execute instructions, for example, of an Operating System (OS) of device 102 and/or of one or more suitable applications.

[00031] In some demonstrative aspects, input unit 192 may include, for example, a keyboard, a keypad, a mouse, a touch-screen, a touch-pad, a track-ball, a stylus, a microphone, or other suitable pointing device or input device. Output unit 193 may include, for example, a monitor, a screen, a touch-screen, a flat panel display, a Light Emitting Diode (LED) display unit, a Liquid Crystal Display (LCD) display unit, a plasma display unit, one or more audio speakers or earphones, or other suitable output devices.

[00032] In some demonstrative aspects, memory unit 194 includes, for example, a Random Access Memory (RAM), a Read Only Memory (ROM), a Dynamic RAM (DRAM), a Synchronous DRAM (SD-RAM), a flash memory, a volatile memory, a non-volatile memory, a cache memory, a buffer, a short term memory unit, a long term memory unit, or other suitable memory units. Storage unit 195 may include, for example, a hard disk drive, a Solid State Drive (SSD), or other suitable removable or non-removable storage units. Memory unit 194 and/or storage unit 195, for example, may store data processed by device 102.

[00033] In some demonstrative aspects, device 102 may be configured to communicate with one or more other devices via at least one network 103, e.g., a wireless and/or wired network.

[00034] In some demonstrative aspects, network 103 may include a wired network, a local area network (LAN), a wireless network, a wireless LAN (WLAN) network, a radio network, a cellular network, a WiFi network, an IR network, a Bluetooth (BT) network, and the like.

[00035] In some demonstrative aspects, device 102 may be configured to perform and/or to execute one or more operations, modules, processes, procedures and/or the like, e.g., as described herein.

[00036] In some demonstrative aspects, device 102 may include a compiler 160, which may be configured to generate a target code 115, for example, based on a source code 112, e.g., as described below.

[00037] In some demonstrative aspects, compiler 160 may be configured to translate the source code 112 into the target code 115, e.g., as described below.

[00038] In some demonstrative aspects, compiler 160 may include, or may be implemented as, software, a software module, an application, a program, a subroutine, instructions, an instruction set, computing code, words, values, symbols, and/or the like.

[00039] In some demonstrative aspects, the source code 112 may include computer code written in a source language.

[00040] In some demonstrative aspects, the source language may include a programing language. For example, the source language may include a high-level programming language, for example, such as, C language, C++ language, and/or the like.

[00041] In some demonstrative aspects, the target code 115 may include computer code written in a target language.

[00042] In some demonstrative aspects, the target language may include a low-level language, for example, such as, assembly language, object code, machine code, or the like.

[00043] In some demonstrative aspects, the target code 115 may include one or more object files, e.g., which may create and/or form an executable program.

[00044] In some demonstrative aspects, the executable program may be configured to be executed on a target computer. For example, the target computer may include a specific computer hardware, a specific machine, and/or a specific operating system.

[00045] In some demonstrative aspects, the executable program may be configured to be executed on a processor 180, e.g., as described below.

[00046] In some demonstrative aspects, processor 180 may include a vector processor 180, e.g., as described below. In other aspects, processor 180 may include any other type of processor.

[00047] Some demonstrative aspects are described herein with respect to a compiler, e.g., compiler 160, configured to compile source code 112 into target code 115 configured to be executed by a vector processor 180, e.g., as described below. In other aspects, a compiler, e.g., compiler 160, configured to compile source code 112 into target code 115 configured to be executed by any other type of processor 180.

[00048] In some demonstrative aspects, processor 180 may be implemented as part of device 102.

[00049] In other aspects, processor 180 may be implemented as part of any other device, e.g., separate from device 102.

[00050] In some demonstrative aspects, vector processor 180 (also referred to as an “array processor”) may include a processor, which may be configured to process an entire vector in one instruction, e.g., as described below.

[00051] In other aspects, the executable program may be configured to be executed on any other additional or alternative type of processor.

[00052] In some demonstrative aspects, the vector processor 180 may be designed to support high-performance image and/or vector processing. For example, the vector processor 180 may be configured to processes 1/2/3/4D arrays of fixed point data and/or floating point arrays, e.g., very quickly and/or efficiently.

[00053] In some demonstrative aspects, the vector processor 180 may be configured to process arbitrary data, e.g., structures with pointers to structures. For example, the vector processor 180 may include a scalar processor to compute the non-vector data, for example, assuming the non-vector data is minimal.

[00054] In some demonstrative aspects, compiler 160 may be implemented as a local application to be executed by device 102. For example, memory unit 194 and/or storage unit 195 may store instructions resulting in compiler 160, and/or processor 191 may be configured to execute the instructions resulting in compiler 160 and/or to perform one or more calculations and/or processes of compiler 160, e.g., as described below.

[00055] In other aspects, compiler 160 may include a remote application to be executed by any suitable computing system, e.g., a server 170.

[00056] In some demonstrative aspects, server 170 may include at least a remote server, a web-based server, a cloud server, and/or any other server.

[00057] In some demonstrative aspects, the server 170 may include a suitable memory and/or storage unit 174 having stored thereon instructions resulting in compiler 160, and a suitable processor 171 to execute the instructions, e.g., as descried below.

[00058] In some demonstrative aspects, compiler 160 may include a combination of a remote application and a local application.

[00059] In one example, compiler 160 may be downloaded and/or received by the user of device 102 from another computing system, e.g., server 170, such that compiler 160 may be executed locally by users of device 102. For example, the instructions may be received and stored, e.g., temporarily, in a memory or any suitable short-term memory or buffer of device 102, e.g., prior to being executed by processor 191 of device 102.

[00060] In another example, compiler 160 may include a client-module to be executed locally by device 102, and a server module to be executed by server 170. For example, the client-module may include and/or may be implemented as a local application, a web application, a web site, a web client, e.g., a Hypertext Markup Language (HTML) web application, or the like.

[00061 ] For example, one or more first operations of compiler 160 may be performed locally, for example, by device 102, and/or one or more second operations of compiler 160 may be performed remotely, for example, by server 170.

[00062] In other aspects, compiler 160 may include, or may be implemented by, any other suitable computing arrangement and/or scheme.

[00063] In some demonstrative aspects, system 100 may include an interface 110, e.g., a user interface, to interface between a user of device 102 and one or more elements of system 100, e.g., compiler 160.

[00064] In some demonstrative aspects, interface 110 may be implemented using any suitable hardware components and/or software components, for example, processors, controllers, memory units, storage units, input units, output units, communication units, operating systems, and/or applications.

[00065] In some aspects, interface 110 may be implemented as part of any suitable module, system, device, or component of system 100.

[00066] In other aspects, interface 110 may be implemented as a separate element of system 100.

[00067] In some demonstrative aspects, interface 110 may be implemented as part of device 102. For example, interface 110 may be associated with and/or included as part of device 102.

[00068] In one example, interface 110 may be implemented, for example, as middleware, and/or as part of any suitable application of device 102. For example, interface 110 may be implemented as part of compiler 160 and/or as part of an OS of device 102.

[00069] In some demonstrative aspects, interface 110 may be implemented as part of server 170. For example, interface 110 may be associated with and/or included as part of server 170.

[00070] In one example, interface 110 may include, or may be part of a Web-based application, a web-site, a web-page, a plug-in, an ActiveX control, a rich content component, e.g., a Flash or Shockwave component, or the like.

[00071] In some demonstrative aspects, interface 110 may be associated with and/or may include, for example, a gateway (GW) 113 and/or an Application Programming Interface (API) 114, for example, to communicate information and/or communications between elements of system 100 and/or to one or more other, e.g., internal or external, parties, users, applications and/or systems.

[00072] In some aspects, interface 110 may include any suitable Graphic-User- Interface (GUI) 116 and/or any other suitable interface.

[00073] In some demonstrative aspects, interface 110 may be configured to receive the source code 112, for example, from a user of device 102, e.g., via GUI 116, and/or API 114.

[00074] In some demonstrative aspects, interface 110 may be configured to transfer the source code 112, for example, to compiler 160, for example, to generate the target code 115, e.g., as described below.

[00075] Reference is made to Fig. 2, which schematically illustrates a compiler 200, in accordance with some demonstrative aspects. For example, compiler 160 (Fig. 1) may be implement one or more elements of compiler 200, and/or may perform one or more operations and/or functionalities of compiler 200.

[00076] In some demonstrative aspects, as shown in Fig. 2, compiler 200 may be configured to generate a target code 233, for example, by compiling a source code 212 in a source language.

[00077] In some demonstrative aspects, as shown in Fig. 2, compiler 200 may include a front-end 210 configured to receive and analyze the source code 212 in the source language.

[00078] In some demonstrative aspects, front-end 210 may be configured to generate an intermediate code 213, for example, based on the source code 212.

[00079] In some demonstrative aspects, intermediate code 213 may include a lower level representation of the source code 212.

[00080] In some demonstrative aspects, front-end 210 may be configured to perform, for example, lexical analysis, syntax analysis, semantic analysis, and/or any other additional or alternative type of analysis, of the source code 212.

[00081] In some demonstrative aspects, front-end 210 may be configured to identify errors and/or problems with an outcome of the analysis of the source code 212. For example, front-end 210 may be configured to generate error information, e.g., including error and/or warning messages, for example, which may identify a location in the source code 212, for example, where an error or a problem is detected.

[00082] In some demonstrative aspects, as shown in Fig. 2, compiler 200 may include a middle-end 220 configured to receive and process the intermediate code 213, and to generate an adjusted, e.g., optimized, intermediate code 223.

[00083] In some demonstrative aspects, middle-end 220 may be configured to perform one or more adjustment, e.g., optimizations, to the intermediate code 213, for example, to generate the adjusted intermediate code 223.

[00084] In some demonstrative aspects, middle-end 220 may be configured to perform the one or more optimizations on the intermediate code 213, for example, independent of a type of the target computer to execute the target code 233.

[00085] In some demonstrative aspects, middle-end 220 may be implemented to support use of the optimized intermediate code 223, for example, for different machine types.

[00086] In some demonstrative aspects, middle-end 220 may be configured to optimize the intermediate representation of the intermediate code 223, for example, to improve performance and/or quality of the produced target code 233.

[00087] In some demonstrative aspects, the one or more optimizations of the intermediate code 213, may include, for example, inline expansion, dead-code elimination, constant propagation, loop transformation, parallelization, and/or the like.

[00088] In some demonstrative aspects, as shown in Fig. 2, compiler 200 may include a back-end 230 configured to receive and process the adjusted intermediate code 213, and to generate the target code 233 based on the adjusted intermediate code 213.

[00089] In some demonstrative aspects, back-end 230 may be configured to perform one or more operations and/or processes, which may be specific for the target computer to execute the target code 233. For example, back-end 230 may be configured to process the optimized intermediate code 213 by applying to the adjusted intermediate code 213 analysis, transformation, and/or optimization operations, which may be configured, for example, based on the target computer to execute the target code 233.

[00090] In some demonstrative aspects, the one or more analysis, transformation, and/or optimization operations applied to the adjusted intermediate code 213 may include, for example, resource and storage decisions, e.g., register allocation, instruction scheduling, and/or the like.

[00091] In some demonstrative aspects, the target code 233 may include targetdependent assembly code, which may be specific to the target computer and/or a target operating system of the target computer, which is to execute the target code 233.

[00092] In some demonstrative aspects, the target code 233 may include targetdependent assembly code for a processor, e.g., vector processor 180 (Fig. 1).

[00093] In some demonstrative aspects, compiler 200 may include a Vector Micro- Code Processor (VMP) Open Computing Language (OpenCL) compiler, e.g., as described below. In other aspects, compiler 200 may include, or may be implemented as part of, any other type of vector processor compiler.

[00094] In some demonstrative aspects, the VMP OpenCL compiler may include a Low Level Virtual Machine (LLVM) based (LLVM-based) compiler, which may be configured according to an LLVM-based compilation scheme, for example, to lower OpenCL C-code to VMP accelerator assembly code, e.g., suitable for execution by vector processor 180 (Fig. 1).

[00095] In some demonstrative aspects, compiler 200 may include one or more technologies, which may be required to compile code to a format suitable for a VMP architecture, e.g., in addition to open-sourced LLVM compiler passes.

[00096] In some demonstrative aspects, FE 210 may be configured to parse the OpenCL C-code and to translate it, e.g., through an Abstract Syntax Tree (AST), for example, into an LLVM Intermediate Representation (IR).

[00097] In some demonstrative aspects, compiler 200 may include a dedicated API, for example, to detect a correct pattern for compiler pattern matching, for example, suitable for the VMP. For example, the VMP may be configured as a Complex Instruction Set Computer (CISC) machine implementing a very complex Instruction Set Architecture (ISA), which may be hard to target from standard C code. Accordingly, compiler pattern matching may not be able to easily detect the correct pattern, and for this case the compiler may require a dedicated API.

[00098] In some demonstrative aspects, FE 210 may implement one or more vendor extension built-ins, which may target VMP-specific ISA, for example, in addition to standard OpenCL built-ins, which may be optimized to a VMP machine.

[00099] In some demonstrative aspects, FE 210 may be configured to implement OpenCL structures and/or work item functions.

[000100] In some demonstrative aspects, ME 220 may be configured to process LLVM IR code, which may be general and target-independent, for example, although it may include one or more hooks for specific target architectures.

[000101] In some demonstrative aspects, ME 220 may perform one or more custom passes, for example, to support the VMP architecture, e.g., as described below.

[000102] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of a Control Flow Graph (CFG) Linearization analysis, e.g., as described below.

[000103] In some demonstrative aspects, the CFG Linearization analysis may be configured to linearize the code, for example, by converting if-statements to select patterns, for example, in case VMP vector code does not support standard control flow.

[000104] In one example, ME 220 may receive a given code, e.g., as follows:

If (x > 0) {

A = A + 5; } else {

B = B * 2;

}

According to this example, ME 220 may be configured to apply the CFG Linearization analysis to the given code, e.g., as follows: tmpA = A + 5; tmpB = B * 2; mask = x > 0;

A = Select mask, tmpA, A

B = Select not mask, tmpB, B

Example (1)

[000105] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of an auto-vectorization analysis, e.g., as described below.

[000106] In some demonstrative aspects, the auto-vectorization analysis may be configured to vectorize, e.g., auto-vectorize, a given code, e.g., to utilize vector capabilities of the VMP.

[000107] In some demonstrative aspects, ME 220 may be configured to perform the auto-vectorization analysis, for example, to vectorize code in a scalar form. For example, some or all operations of the auto-vectorization analysis may not be performed, for example, in case the code is already provided in a vectorized form.

[000108] In some demonstrative aspects, for example, in some use cases and/or scenarios, a compiler may not always be able to auto-vectorize a code, for example, due to data dependencies between loop iterations.

[000109] In one example, ME 220 may receive a given code, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i++) { a[i]=b[i]+c[i]; }

According to this example, ME 220 may be configured to perform the CFG autovectorization analysis by applying a first conversion, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i+=32) { a[i.i+31 ]=b [i ...i+3 l]+c[i.. ,i+31];

}

Example (2a)

For example, ME 220 may be configured to perform the CFG auto-vectorization analysis by applying a second conversion, for example, following the first conversion, e.g., as follows: char32* a,b,c; for (int i=0; i < 64; i++) { a[i]=b[i]+c[i];

}

Example (2b)

[000110] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of a Scratch Pad Memory Loop Access Analysis (SPMLAA), e.g., as described below.

[000111] In some demonstrative aspects, the SPMLAA may define Processing Blocks (PB), e.g., that should be outlined and compiled for VMP later.

[000112] In some demonstrative aspects, the processing blocks may include accelerated loops, which may be executed by the vector unit of the VMP.

[000113] In some demonstrative aspects, a PB, e.g., each PB, may include memory references. For example, some or all memory accesses may refer to local memory banks. [000114] In some demonstrative aspects, the VMP may enable access to memory banks through AGUs, e.g., AGUs 320 as described below with reference to Fig. 3, and Scatter Gather units (SG).

[000115] In some demonstrative aspects, the AGUs may be pre-configured, e.g., before loop execution. For example, a loop trip count may be calculated, e.g., ahead of running a processing block.

[000116] In some demonstrative aspects, image references, e.g., some or all image references, may be created at this stage, and may be followed by calculation of strides and offsets, e.g., per dimension for each reference.

[000117] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of an AGU planner analysis, e.g., as described below.

[000118] In some demonstrative aspects, the AGU Planner analysis may include iterator assignment, which may cover image references, e.g., all image references, from the entire Processing Block.

[000119] In some demonstrative aspects, an iterator may cover a single reference or a group of references.

[000120] In some demonstrative aspects, one or more memory references may be coalesced and/or reuse a same access through shuffle instructions, and/or saving values read from previous iterations.

[000121] In some demonstrative aspects, other memory references, e.g., which have no linear access pattern, may be handled using a Scatter-Gather (SG) unit, which may have a performance penalty, e.g., as it may require maintaining indices and/or masks.

[000122] In some demonstrative aspects, a plan may be configured as an arrangement of iterators in a processing block. For example, a processing block may have multiple plans, e.g., theoretically.

[000123] In some demonstrative aspects, the AGU Planner analysis may be configured to build all possible plans for all PBs, and to select a combination, e.g., a best combination, e.g., from all valid combinations.

[000124] In some demonstrative aspects, a total number of iterators in a valid combination may be limited, e.g., not to exceed a number of available AGUs on a VMP. [000125] In some demonstrative aspects, one or more parameters, e.g., including stride, width and/or base, may be defined for an iterator, e.g., for each iterator for example, as part of the AGU Planner analysis. For example, min-max ranges for the iterators may be defined in a dimension, e.g., in each dimension, for example, as part of the AGU Planner analysis.

[000126] In some demonstrative aspects, the AGU Planner analysis may be configured to track and evaluate a memory reference, e.g., each memory reference, to an image, e.g., to understand its access pattern.

[000127] In one example, according to Examples 2a/2b, the image 'a' which is the base address, may be accessed with steps of 32 bytes for 64 iterations.

[000128] In some demonstrative aspects, the LLVM may include a scalar evaluation analysis (SCEV), which may compute an access pattern, e.g., to understand every image reference.

[000129] In some demonstrative aspects, ME 220 may utilize masking capabilities of the AGUs, for example, to avoid maintaining an induction variable, which may have a performance penalty.

[000130] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of a rewrite analysis, e.g., as described below.

[000131] In some demonstrative aspects, the rewrite analysis may be configured to transform the code of a processing block, for example, while setting iterators and/or modifying memory access instructions.

[000132] In some demonstrative aspects, setting of the iterators, e.g., of all iterators, may be implemented in IR in target- specific intrinsics. For example, the setting of the iterators may reside in a pre-header of an outermost loop.

[000133] In some demonstrative aspects, the rewrite analysis may include loop- perfectization analysis, e.g., as described below.

[000134] In some demonstrative aspects, the code may be compiled with a target that substantially all calculations should be executed inside the innermost loop.

[000135] For example, the loop-perfectization analysis may hoist instructions, e.g., to move into a loop an operation performed after a last iteration of the loop. [000136] For example, the loop-perfectization analysis may sink instructions, e.g., to move into a loop an operation performed before a first iteration of the loop.

[000137] For example, the loop-perfectization analysis may hoist instructions and/or sink instructions, for example, such that substantially all instructions are moved from outer loops to the innermost loops.

[000138] For example, the loop-perfectization analysis may be configured to provide a technical solution to support VMP iterators, e.g., to work on perfectly nested loops only.

[000139] For example, the loop-perfectization analysis may result in a situation where there are no instructions between the “for” statements that compose the loop, e.g., to support VMP iterators, which cannot emulate such cases.

[000140] In some demonstrative aspects, the loop-perfectization analysis may be configured to collapse a nested loop into a single collapsed loop.

[000141] In one example, ME 220 may receive a given code, e.g., as follows: for (int i = 0; i < N; i++) { int sum = 0; for (intj = 0; j < M; j++)

{ sum += a[j + stride * i] ;

} res[i] = sum;

}

According to this example, ME 220 may be configured to perform the loop- perfectization analysis to collapse the nested loop in the code to a single collapsed loop, e.g., as follows: for (int k = 0; k < N * M; k++) { sum = (k % M == 0 ? 0 : sum); sum += a[k % M + stride * ( k / M )] ; res[k/M] = sum;

}

Example (3)

[000142] In some demonstrative aspects, ME 220 may be configured to perform one or more operations of a Vector Loop Outlining analysis, e.g., as described below.

[000143] In some demonstrative aspects, the Vector Loop Outlining analysis may be configured to divide a code between a scalar subsystem and a vector subsystem, e.g., vector processing block 310 (Fig. 3) and scalar processor 330 (Fig. 3) as described below with reference to Fig. 3.

[000144] In some demonstrative aspects, the VMP accelerator may include the scalar and/or vector subsystems, e.g., as described below. For example, each of the subsystems may have different compute units/processors. Accordingly, a scalar code may be compiled on a scalar compiler, e.g., an SSC compiler, and/or an accelerated vector code may run on the VMP vector processor.

[000145] In some demonstrative aspects, the Vector Loop Outlining analysis may be configured to create a separate function for a loop body of the accelerated vector code. For example, these functions may be marked for the VMP and/or may continue to the VMP backend, for example, while the rest of the code may be compiled by the SSC compiler.

[000146] In some demonstrative aspects, one or more parts of a vector loop, e.g., configuration of the vector unit and/or initialization of vector registers, may be performed by a scalar unit. However, these parts may be performed in a later stage, for example, by performing backpatching into the scalar code, e.g., as the scalar code may still be in LLVM IR before processing by the SSC compiler.

[000147] In some demonstrative aspects, BE 230 may be configured to translate the LLVM IR into machine instructions. For example, the BE 230 may not be target agnostic and may be familiar with target- specific architecture and optimizations, e.g., compared to ME 220, which may be agnostic to a target- specific architecture. [000148] In some demonstrative aspects, BE 230 may be configured to perform one or more analyses, which may be specific to a target machine, e.g., a VMP machine, to which the code is lowered, e.g., although BE 230 may use common LLVM.

[000149] In some demonstrative aspects, BE 230 may be configured to perform one or more operations of an instruction lowering analysis, e.g., as described below.

[000150] In some demonstrative aspects, the instruction lowering analysis may be configured to translate LLVM IR into target-specific instructions Machine IR (MIR), for example, by translating the LLVM IR into a Directed Acyclic Graph (DAG).

[000151] In some demonstrative aspects, the DAG may go through a legalization process of instructions, for example, based on the data types and/or VMP instructions, which may be supported by a VMP HW.

[000152] In some demonstrative aspects, the instruction lowering analysis may be configured to perform a process of pattern-matching, e.g., after the legalization process of instructions, for example, to lower a node, e.g., each node, in the DAG, for example, into a VMP-specific machine instruction.

[000153] In some demonstrative aspects, the instruction lowering analysis may be configured to generate the MIR, for example, after the process of pattern-matching.

[000154] In some demonstrative aspects, the instruction lowering analysis may be configured to lower the instruction according to machine Application Binary Interface (AB I) and/or calling conventions.

[000155] In some demonstrative aspects, BE 230 may be configured to perform one or more operations of a unit balancing analysis, e.g., as described below.

[000156] In some demonstrative aspects, the unit balancing analysis may be configured to balance instructions between VMP compute units, e.g., data processing units 316 (Fig. 3) as described below with reference to Fig. 3.

[000157] In some demonstrative aspects, the unit balancing analysis may be familiar with some or all available arithmetic transformations, and/or may perform transformations according to an optimal algorithm.

[000158] In some demonstrative aspects, BE 230 may be configured to perform one or more operations of a modulo scheduler (pipeliner) analysis, e.g., as described below. [000159] In some demonstrative aspects, the pipeliner may be configured to schedule the instructions according to one or more constraints, e.g., data dependency, resource bottlenecks and/or any other constrains, for example, using Swing Modulo Scheduling (SMS) heuristics and/or any other additional and/or alternative heuristic.

[000160] In some demonstrative aspects, the pipeliner may be configured to schedule a set, e.g., an Initiation Interval (II), of Very Long Instruction Word (VLIW) instructions that the program will iterate on, e.g., during a steady state.

[000161] In some demonstrative aspects, a performance metric, which may be based on a number of cycles a typical loop may execute, may be measured, e.g., as follows:

(Size of Input data in bytes) * II / (Bytes consumed/produced every iteration)

[000162] In some demonstrative aspects, the pipeliner may try to minimize the II, e.g., as much as possible, for example, to improve performance.

[000163] In some demonstrative aspects, the pipeliner may be configured to calculate a minimum II, and to schedule accordingly. For example, if the pipeliner fails the scheduling, the pipeliner may try to increase the II and retry scheduling, e.g., until a predefined II threshold is violated.

[000164] In some demonstrative aspects, BE 230 may be configured to perform one or more operations of a register allocation analysis, e.g., as described below.

[000165] In some demonstrative aspects, the register allocation analysis may be configured to attempt to assign a register in an efficient, e.g., optimal, way.

[000166] In some demonstrative aspects, the register allocation analysis may assign values to bypass vector registers, general purpose vector registers, and/or scalar registers.

[000167] In some demonstrative aspects, the values may include private variables, constants, and/or values that are rotated across iterations.

[000168] In some demonstrative aspects, the register allocation analysis may implement an optimal heuristic that suites one or more VMP register file (regfile) constraints. For example, in some use cases, the register allocation analysis may not use a standard LLVM register allocation. [000169] In some demonstrative aspects, in some cases, the register allocation analysis may fail, which may mean that the loop cannot be compiled. Accordingly, the register allocation analysis may implement a retry mechanism, which may go back to the modulo scheduler and may attempt to reschedule the loop, e.g., with an increased initiation interval. For example, increasing the initiation interval may reduce register pressure, and/or may support compilation of the vector loop, e.g., in many cases.

[000170] In some demonstrative aspects, BE 230 may be configured to perform one or more operations of an SSC configuration analysis, e.g., as described below.

[000171] In some demonstrative aspects, the SSC configuration analysis may be configured to set a configuration to execute the kernel, e.g., the AGU configuration.

[000172] In some demonstrative aspects, the SSC configuration analysis may be performed at a late stage, for example, due to configurations calculated after legalization, the register allocation analysis, and/or the modulo scheduling analysis.

[000173] In some demonstrative aspects, the SSC configuration analysis may include a Zero Overhead Loop (ZOL) mechanism in the vector loop. For example, the ZOL mechanism may configure a loop trip count based on an access pattern of the memory references in the loop, for example, to avoid running instructions that check the loop exit condition every iteration.

[000174] In some demonstrative aspects, a VMP Compilation Flow may include one or more, e.g., a few, steps, which may be invoked during the compilation flow in a test library (testlib), e.g., a wrapper script for compilation, execution, and/or program testing. For example, these steps may be performed outside of the LLVM Compiler.

[000175] In some demonstrative aspects, a PCB Hardware Description Language (PHDL) simulator may be implemented to perform one or more roles of an assembler, encoder, and/or linker.

[000176] In some demonstrative aspects, compiler 200 may be configured to provide a technical solution to support robustness, which may enable compilation of a vast selection of loops, with HW limitations. For example, compiler 200 may be configured to support a technical solution, which may not create verification errors. [000177] In some demonstrative aspects, compiler 200 may be configured to provide a technical solution to support programmability, which may provide a user an ability to express code in multiple ways, which may compile correctly to the VMP architecture.

[000178] In some demonstrative aspects, compiler 200 may be configured to provide a technical solution to support an improved user-experience, which may allow the user capability to debug and/or profile code. For example, the improved user-experience may provide informative error messages, report tools, and/or a profiler.

[000179] In some demonstrative aspects, compiler 200 may be configured to provide a technical solution to support improved performance, for example, to optimize a VMP assembly code and/or iterator accesses, which may lead to a faster execution. For example, improved performance may be achieved through high utilization of the compute units and usage of its complex CISC.

[000180] Reference is made to Fig. 3, which schematically illustrates a vector processor 300, in accordance with some demonstrative aspects. For example, vector processor 180 (Fig. 1) may be implement one or more elements of vector processor 300, and/or may perform one or more operations and/or functionalities of vector processor 300.

[000181] In some demonstrative aspects, vector processor 300 may include a Vector Microcode Processor (VMP).

[000182] In some demonstrative aspects, vector processor 300 may include a Wide Vector machine, for example, supporting Very Long Instruction Word (VLIW) architectures, and/or Single Instruction/Multiple Data (SIMD) architectures.

[000183] In some demonstrative aspects, vector processor 300 may be configured to provide a technical solution to support high performance for short integral types, which may be common, for example, in computer- vision and/or deep-learning algorithms.

[000184] In other aspects, vector processor 300 may include any other type of vector processor, and/or may be configured to support any other additional or alternative functionalities.

[000185] In some demonstrative aspects, as shown in Fig. 3, vector processor 300 may include a vector processing block (vector processor) 310, a scalar processor 330, and a Direct Memory Access (DMA) 340, e.g., as described below. [000186] In some demonstrative aspects, as shown in Fig. 3, vector processing block 310 may be configured to process, e.g., efficiently process, image data and/or vector data. For example, the vector processing block 310 may be configured to use vector computation units, for example, to speed up computations.

[000187] In some demonstrative aspects, scalar processor 330 may be configured to perform scalar computations. For example, the scalar processor 330 may be used as a "glue logic" for programs including vector computations. For example, some, e.g., even most, of the computation of the programs may be performed by the vector processing block 310. However, several tasks, for example, some essential tasks, e.g., scalar computations, may be performed by the scalar processor 330.

[000188] In some demonstrative aspects, the DMA 340 may be configured to interface with one or more memory elements in a chip including vector processor 300.

[000189] In some demonstrative aspects, the DMA 340 may be configured to read inputs from a main memory, and/or write outputs to the main memory.

[000190] In some demonstrative aspects, the scalar processor 330 and the vector processing block 310 may use respective local memories to process data.

[000191] In some demonstrative aspects, as shown in Fig. 3, vector processor 300 may include a fetcher and decoder 350, which may be configured to control the scalar processor 330 and/or the vector processing block 310.

[000192] In some demonstrative aspects, operations of the scalar processor 330 and/or the vector processing block 310 may be triggered by instructions stored in a program memory 352.

[000193] In some demonstrative aspects, the DMA 340 may be configured to transfer data, for example, in parallel with the execution of the program instructions in memory 352.

[000194] In some demonstrative aspects, DMA 340 may be controlled by software, e.g., via configuration registers, for example, rather than instructions, and, accordingly, may be considered as a second "thread" of execution in vector processor 300. [000195] In some demonstrative aspects, the scalar processor 330, the vector processing block 310, and/or the DMA 340 may include one or more data processing units, for example, a set of data processing units, e.g., as described below.

[000196] In some demonstrative aspects, the data processing units may include hardware configured to preform computations, e.g., an Arithmetic Logic Unit (ALU).

[000197] In one example, a data processing unit may be configured to add numbers, and/or to store the numbers in a memory.

[000198] In some demonstrative aspects, the data processing units may be controlled by commands, e.g., encoded in the program memory 352 and/or in configuration registers. For example, the configuration registers may be memory mapped, and may be written by the memory store commands of the scalar processor 330.

[000199] In some demonstrative aspects, the scalar processor 330, the vector processing block 310, and/or the DMA 340 may include a state configuration including a set of registers and memories, e.g., as described below.

[000200] In some demonstrative aspects, as shown in Fig. 3, vector processor block 310 may include a set of vector memories 312, which may be configured, for example, to store data to be processed by vector processor block 310.

[000201] In some demonstrative aspects, as shown in Fig. 3, vector processor block 310 may include a set of vector registers 314, which may be configured, for example, to be used in data processing by vector processor block 310.

[000202] In some demonstrative aspects, the scalar processor 330, the vector processing block 310, and/or the DMA 340 may be associated with a set of memory maps.

[000203] In some demonstrative aspects, a memory map may include a set of addresses accessible by a data processing unit, which may load and/or store data from/to registers and memories.

[000204] In some demonstrative aspects, as shown in Fig. 3, the vector processing block 310 may include a plurality of Address Generation Units (AGUs) 320, which may include addresses accessible to them, e.g., in one or more of memories 312. [000205] In some demonstrative aspects, as shown in Fig. 3, vector processor block 310 may include a plurality of data processing units 316, e.g., as described below.

[000206] In some demonstrative aspects, data processing units 316 may be configured to process commands, e.g., including several numbers at a time. In one example, a command may include 8 numbers. In another example, a command may include 4 numbers, 16 numbers, or any other count of numbers.

[000207] In some demonstrative aspects, two or more data processing units 316 may be used simultaneously. In one example, data processing units 316 may process and execute a plurality of different command, e.g., 3 different commands, for example, including 8 numbers, at a throughout of a single cycle.

[000208] In some demonstrative aspects, data processing units 316 may be asymmetrical. For example, first and second data processing units 316 may support different commands. For example, addition may be performed by a first data processing unit 316, and/or multiplication may be performed by a second data processing unit 316. For example, both operations may be performed by one or more additional other data processing units 316.

[000209] In some demonstrative aspects, data processing units 316 may be configured to support arithmetic operations for many combinations of input & output data types.

[000210] In some demonstrative aspects, data processing units 316 may be configured to support one or more operations, which may be less common. For example, processing units 316 may support operations working with a Look Up Table (LUT) of vector processor 300, and/or any other operations.

[000211] In some demonstrative aspects, data processing units 316 may be configured to support efficient computation of non-linear functions, histograms, and/or random data access, e.g., which may be useful to implement algorithms like image scaling, Hough transforms, and/or any other algorithms.

[000212] In some demonstrative aspects, vector memories 312 may include, for example, memory banks having a size of 16K or any other size, which may be accessed at a same cycle.

[000213] In one example, a maximal memory access size may be 64 bits. According to this example, a peak throughput may be 256 bits, e.g., 64x4 = 256. For example, high memory bandwidth may be implemented to utilize computation capabilities of the data processing units 316.

[000214] In one example, two data processing units 316 may support 16 8-bit multiply & accumulate operations (MACs) per cycle. According to this example, the two data processing units 316 may not be useful, for example, in case the input numbers are not fetched at this speed, and/or there isn’t exactly 256 bits of input, e.g., 16x8x2 = 256.

[000215] In some demonstrative aspects, AGUs 320 may be configured to perform memory access operations, e.g., loading and storing data from/to vector memories 314.

[000216] In some demonstrative aspects, AGUs 320 may be configured to compute addresses of input and output data items, for example, to handle I/O to utilize the data processing units 316, e.g., in case sheer bandwidth is not enough.

[000217] In some demonstrative aspects, AGUs 320 may be configured to compute the addresses of the input and/or output data items, for example, based on configuration registers written by the scalar processor 330, for example, before a block of vector commands, e.g., a loop, is entered.

[000218] For example, AGUs 320 may be configured to write an image base pointer, a width, a height and/or a stride to the configuration registers, for example, in order to iterate over an image.

[000219] In some demonstrative aspects, AGUs 320 may be configured to handle addressing, e.g., all addressing, for example, to provide a technical solution in which data processing units 316 may not have the burden of incrementing pointers or counters in a loop, and/or the burden to check for end-of-row conditions, e.g., to zero a counter in the loop.

[000220] In some demonstrative aspects, as shown in Fig. 3, AGUs 320 may include 4 AGUs, and, accordingly, four memories 312 may be accessed at a same cycle. In other aspects, any other count of AGUs 32 may be implemented.

[000221] In some demonstrative aspects, AGUs 320 may not be "tied" to memory banks 312. For example, an AGU 320, e.g., each AGU 320, may access a memory bank 312, e.g., every memory bank 312, for example, as long as two or more AGUs 320 do not try to access the same memory bank 312 at the same cycle. [000222] In some demonstrative aspects, vector registers 314 may be configured to support communication between the data processing units 316 and AGUs 320.

[000223] In one example, a total number of vector registers 314 may be 28, which may be divided into several subsets, e.g., based on their function. For example, a first subset of vector registers 314 may be used for inputs/outputs, e.g., of all data processing units 316 and/or AGUs 320; and/or a second subset of vector registers 314 may not be used for outputs of some operations, e.g., most operations, and may be used for one or more other operations, e.g., to store loop-invariant inputs.

[000224] In some demonstrative aspects, a data processing unit 316, e.g., each data processing unit 316, may have one or more registers to host an output of a last executed operation, e.g., which may be fed as inputs to other data processing units 316. For example, these registers may "bypass" the vector registers 314, and may work faster than writing these outputs to first set of vector registers 314.

[000225] In some demonstrative aspects, fetcher and decoder 350 may be configured to support low-overhead vector loops, e.g., very low overhead vector loops (also referred to as “zero-overhead vector loops”), for example, where there may be no need to check a termination (exit) condition of a vector loop during an execution of the vector loop.

[000226] For example, a termination (exit) condition may be signaled by an AGU 320, for example, when the AGU 320 finishes iterating over a configured memory region.

[000227] For example, fetcher and decoder 350 may quit the loop, for example, when the AGU 320 signals the termination condition.

[000228] For example, the scalar processor 330 may be utilized to configure the loop parameters, e.g., first & last instructions and/or the exit condition.

[000229] In one example, vector loops may be utilized, for example, together with high memory bandwidth and/or cheap addressing, for example, to solve a control and data flow problem, for example, to provide a technical solution to allow the data processing units 316 to process data, e.g., without substantially additional overhead.

[000230] In some demonstrative aspects, scalar processor 330 may be configured to provide one or more functionalities, which may be complementary to those of the vector processing block 310. For example, a large portion, e.g., most, of the work in a vector program may be performed by the data processing units 316. For example, the scalar processor 330 may be utilized, for example, for "gluing" together the various blocks of vector code of the vector program.

[000231] In some demonstrative aspects, scalar processor 330 may be implemented separately from vector processing block 310. In other aspects, scalar processor 330 may be configured to share one or more components and/or functionalities with vector processing block 310.

[000232] In some demonstrative aspects, scalar processor 330 may be configured to perform operations, which may not be suitable for execution on vector processing block 310.

[000233] For example, scalar processor 330 may be utilized to execute 32 bit C programs. For example, scalar processor 330 may be configured to support 1, 2, and/or 4 byte data types of C code, and/or some or all arithmetic operators of C code.

[000234] For example, scalar processor 330 may be configured to provide a technical solution to perform operations that cannot be executed on vector processing block 310, for example, without using a full-blown CPU.

[000235] In some demonstrative aspects, scalar processor 330 may include a scalar data memory 332, e.g., having a size of 16K or any other size, which may be configured to store data, e.g., variables used by the scalar parts of a program.

[000236] For example, scalar processor 330 may store local and/or global variables declared by portable C code, which may be allocated to scalar data memory by a compiler, e.g., compiler 200 (Fig. 2).

[000237] In some demonstrative aspects, as shown in Fig. 3, scalar processor 330 may include, or may be associated with, a set of vector registers 334, which may be used in data processing performed by the scalar processor 330.

[000238] In some demonstrative aspects, scalar processor 330 may be associated with a scalar memory map, which may support scalar processor 330 in accessing substantially all states of vector processor 300. For example, the scalar processor 330 may configure the vector units and/or the DMA channels via the scalar memory map. [000239] In some demonstrative aspects, scalar processor 330 may not be allowed to access one or more block control registers, which may be used by external processors to run and debug vector programs.

[000240] In some demonstrative aspects, DMA 340 may be configured to communicate with one or more other components of a chip implementing the vector processor 300, for example, via main memory. For example, DMA 340 may be configured to transfer blocks of data, e.g., large, contiguous, blocks of data, for example, to support the scalar processor 330 and/or the vector processing block, which may manipulate data stored in the local memories. For example, a vector program may be able to read data from the main chip memory using DMA 340.

[000241] In some demonstrative aspects, DMA 340 may be configured to communicate with other elements of the chip, for example, via a plurality of DMA channels, e.g., 8 DMA channels or any other count of DMA channels. For example, a DMA channel, e.g., each DMA channel, may be capable of transferring a rectangular patch from the local memories to the main chip memory, or vice versa. In other aspects, the DMA channel may transfer any other type of data block between the local memories and the main chip memory.

[000242] In some demonstrative aspects, a rectangular patch may be defined by a base pointer, a width, a height, and astride.

[000243] For example, at peak throughput, 8 bytes per cycle may be transferred, however, there may be overheads for each patch and/or for each row in a patch.

[000244] In some demonstrative aspects, DMA 340 may be configured to transfer data, for example, in parallel with computations, e.g., via the plurality of DMA channels, for example, as long as executed commands do not access a local memory involved in the transfer.

[000245] In one example, as all channels may access the same memory bus, using several channels to implement a transfer may not save I/O cycles, e.g., compared to the case when a single channel is used. However, the plurality of DMA channels may be utilized to schedule several transfers and execute them in parallel with computations. This may be advantageous, for example, compared to a single channel, which may not allow scheduling a second transfer before completion of the first transfer. [000246] In some demonstrative aspects, DMA 340 may be associated with a memory map, which may support the DMA channels in accessing vector memories and/or the scalar data. For example, access to the vector memories may be performed in parallel with computations. For example, access to the scalar data may usually not be allowed in parallel, e.g., as the scalar processor 330 may be involved in almost any sensible program, and may likely access it's local variables while the transfer is performed, which may lead to a memory contention with the active DMA channel.

[000247] In some demonstrative aspects, DMA 340 may be configured to provide a technical solution to support parallelization of I/O and computations. For example, a program performing computations may not have to wait for I/O, for example, in case these computations may run fast by vector processing block 310.

[000248] In some demonstrative aspects, an external processor, e.g., a CPU, may be configured to initiate execution of a program on vector processor 300. For example, vector processor 300 may remain idle, e.g., as long as program execution is not initiated.

[000249] In some demonstrative aspects, the external processor may be configured to debug the program, e.g., execute a single step at a time, halt when the program reaches breakpoints, and/or inspect contents of registers and memories storing the program variables.

[000250] In some demonstrative aspects, an external memory map may be implemented to support the external processor in controlling the vector processor 300 and/or debugging the program, for example, by writing to control registers of the vector processor 300.

[000251] In some demonstrative aspects, the external memory map may be implemented by a superset of the scalar memory map. For example, this implementation may make all registers and memories defined by the architecture of the vector processor 300 accessible to a debugger back-end running on the external processor.

[000252] In some demonstrative aspects, the vector processor 300 may raise an interrupt signal, for example, when the vector processor 300 terminates a program.

[000253] In some demonstrative aspects, the interrupt signal may be used, for example to implement a driver to maintain a queue of programs scheduled for execution by the vector processor 300, and/or to launch a new program, e.g., by the external processor, for example, upon the completion of a previously executed program.

[000254] Referring back to Fig. 1, in some demonstrative aspects, compiler 160 may be configured to generate the target code 115 based on one or more loops, which may be based, for example, on source code 112, e.g., as described below.

[000255] In some demonstrative aspects, compiler 160 may be configured to compile one or more operations according to a compilation scheme, which may be configured to provide a technical solution to reduce, or even eliminate, usage of induction variables, for example, in one or more masked memory-access operations in a loop, e.g., as described below.

[000256] In some demonstrative aspects, the one or more masked memory-access operations in the loop may include a masked-load operation, a masked- store operation, a masked-select operation, and/or any other masked operation to access a memory, e.g., as described below.

[000257] In some demonstrative aspects, a masked memory-access instruction may include a conditional operation based on a mask expression including a logical condition, e.g., as described below.

[000258] In some demonstrative aspects, the conditional operation of the masked memory-access instruction may be performed, for example, based on whether the mask expression is true or false.

[000259] In some demonstrative aspects, a mask expression may include one or more Boolean conditions, which may be based on, and/or may represent, for example, a result of a condition.

[000260] In some demonstrative aspects, the mask expression may include one or more mask leaves corresponding to the one or more Boolean conditions.

[000261] In some demonstrative aspects, a mask leaf may correspond to a respective Boolean condition, e.g., as described below.

[000262] In one example, a loop may include a mask expression, which may be defined based on one or more Boolean conditions, e.g., as follows: char Mask = (a>x) I (b<10); [000263] For example, this mask expression may include a first leaf and a second leaf. For example, the first leaf may include a first Boolean condition (a>x), and the second leaf may include a second Boolean condition (b<10).

[000264] According to this example, a result of the mask expression may be true, for example, when the first Boolean condition of the first leaf (a>x) is true and/or the second Boolean condition of the second leaf (b<10) is true.

[000265] In some demonstrative aspects, for example, in some use cases, scenarios and/or implementations, there may be a need to address one or more technical issues when implementing a masked operation in a loop, e.g., as described below.

[000266] In some demonstrative aspects, for example, in some use cases, scenarios and/or implementations, computation of some masks in a loop may be computationally complex and/or expensive.

[000267] For example, computation of a mask (also referred to as an “induction-based mask”), which is based on an induction variable (IV) of a loop including the mask, may require maintaining an IV for the loop, comparing the IV against some bound, reserving mask-registers, and/or one or more additional or alternative operations based on the IV.

[000268] In one example, an induction variable of a loop may include a variable, which may be increased or decreased, e.g., by a fixed amount, for example, on every iteration of the loop. In another example, an induction variable of a loop may be a function, e.g., a linear function, of another induction variable of the loop.

[000269] For example, in some use cases, scenarios and/or implementations, some loop transformations, e.g., loop-vectorization transformations, may introduce one or more induction-based masks, for example, to filter out out-of-bounds values/computations .

[000270] For example, this filtering may be performed, for example, by a masked operation, which may be configured to select, according to an IV-based mask, for example, between loaded/computed values, and some default- values.

[000271] For example, in some use cases, scenarios and/or implementations, computing the masked operations may be computationally “painful”, for example, when implemented by one or more target processor architectures, which may not have efficient means to maintain inductions. [000272] In one example, some target architectures may have other Hardware (HW) mechanisms to control an execution of a loop, and to control bounds of memory accesses ("bounded loads/stores").

[000273] In some demonstrative aspects, complier 160 may be configured to identify one or more masked memory-access operations based on source code 112, and to compile the identified masked memory-access operations according to a masked- operation compilation scheme, e.g., as described below.

[000274] In some demonstrative aspects, complier 160 may be configured to generate the target code 115 by compiling the source code 112, for example, according to the masked-operation compilation scheme, e.g., as described below.

[000275] In some demonstrative aspects, the identified masked memory-access operation may be based on a mask expression, e.g., as described below.

[000276] In some demonstrative aspects, the masked-operation compilation scheme may be configured to provide a technical solution to reduce, eliminate, optimize, and/or exclude, usage of induction variables in the identified masked memory-access operations, e.g., as described below.

[000277] In some demonstrative aspects, the masked-operation compilation scheme may be configured to provide a technical solution to exclude one or more mask leaves, which may be based on an IV (IV-based mask leaf), from the mask expression, e.g., as described below.

[000278] In some demonstrative aspects, the masked-operation compilation scheme may be configured to provide a technical solution to maintain in the mask expression one or more mask leaves, which may not be based on an IV (non-IV-based mask leaves), e.g., as described below.

[000279] In some demonstrative aspects, the masked-operation compilation scheme may be configured to provide a technical solution to generate target code 115, for example, based on masked memory-access operations, which may not be based on, and/or which may not require handling induction variables, e.g., as described below.

[000280] In some demonstrative aspects, the masked-operation compilation scheme may be configured to provide a technical solution, which may improve performance of the executed program, e.g., an image processing program, for example, by excluding one or more, e.g., some or all, IV-based mask leaves from the mask expression, e.g., as described below.

[000281] In some demonstrative aspects, the masked-operation compilation scheme may be configured to convert a first mask expression into a second mask expression, for example, by reconfiguring the first mask expression, e.g., as described below.

[000282] In some demonstrative aspects, the second mask expression may be configured to simplify or exclude one or more mask leaves of the first mask expression, e.g., as described below.

[000283] In some demonstrative aspects, the masked-operation compilation scheme may be configured to convert a first mask expression into a logical form including a first logical expression part and a second logical expression part, e.g., as described below.

[000284] In some demonstrative aspects, the first logical expression part may be based on one or more mask leaves of the first mask expression, e.g., as described below.

[000285] In some demonstrative aspects, the first logical expression part may include an additional Expression (Exprl), which may be obtained from the mask expression, for example, by replacing the one or more mask leaves of the first mask expression and/or one or more don’t-care leaves of the first mask expression, for example, by a constant 0 or 1, e.g., as described below.

[000286] In one example, the masked-operation compilation scheme may be configured to convert an original mask expression, for example, into a logical form, which may be represented, e.g., as follows:

Pl & -P2 & P3 & ... & Exprl wherein Pl, P2, P3 denote mask leaves of the original mask expression, and the Expression Exprl may be obtained from the original mask expression, for example, by replacing the mask leaves Pl, P2, and/or P3, and/or one or more don’t-care” mask leaves, for example, by a constant “0” or “1”.

[000287] In some demonstrative aspects, the masked-operation compilation scheme may be configured to build a truth table of the first mask expression, e.g., as described below. [000288] In some demonstrative aspects, the masked-operation compilation scheme may be configured to build the truth table of the first mask expression, for example, based on the mask leaves of the first mask expression, e.g., as described below.

[000289] In some demonstrative aspects, the masked-operation compilation scheme may be configured to identify one or more mask leaves to be simplified and/or replaced, for example, according to the truth table, e.g., as described below.

[000290] For example, the identified mask leaves may be represented by one or more “ANDed” leaves of the logical form corresponding to the first mask expression, e.g. as described below.

[000291] In some demonstrative aspects, the masked-operation compilation scheme may be configured to replace one or more of the identified mask leaves with Iterator min/max parameters, e.g., as described below.

[000292] For example, the masked-operation compilation scheme may be configured to assign the identified mask leaves, e.g., which may be represented by the literals Pl & ~P2 & P3 of the logical form, for example, to one or more AGUs, e.g., as described below.

[000293] In some demonstrative aspects, the masked-operation compilation scheme may be configured to generate the second mask expression, for example, based on the second logical expression part, e.g., the Expression Exprl of the logical form, which may remain, for example, after the identified mask leaves are assigned to the AGUs, e.g., as described below.

[000294] In some demonstrative aspects, compiler 160 may be configured to identify a first masked memory-access operation, e.g., in a loop, for example, based on a source code 112, e.g., as described below.

[000295] In some demonstrative aspects, the first masked memory-access operation may be based on a first mask expression including one or more mask leaves, e.g., as described below.

[000296] In some demonstrative aspects, compiler 160 may be configured to determine an identified mask leaf of the one or more mask leaves of the first mask expression, for example, based on at least one predefined criterion, e.g., as described below. [000297] In some demonstrative aspects, compiler 160 may be configured to determine an identified mask leaf of the one or more mask leaves of the first mask expression, for example, based on a criterion relating to an effect of the identified mask leaf on a logical value of the first mask expression, e.g., as described below.

[000298] In some demonstrative aspects, compiler 160 may be configured to determine a second masked memory-access operation by reconfiguring the first masked memory-access operation, for example, based on the identified mask leaf of the first mask expression, e.g., as described below.

[000299] In some demonstrative aspects, the second masked memory-access operation may be based on a second mask expression, e.g., as described below.

[000300] In some demonstrative aspects, the second mask expression may be logically simplified, for example, compared to the first mask expression, e.g., as described below.

[000301] In some demonstrative aspects, compiler 160 may be configured to configure the second masked memory-access operation, for example, such that a count of mask leaves in the second mask expression is less than a count of mask leaves in the first mask expression of the first masked memory-access operation, e.g., as described below.

[000302] In some demonstrative aspects, the second masked memory-access operation may include a masked load operation to conditionally load values from a memory according to the second mask expression, e.g., as described below.

[000303] In some demonstrative aspects, the second masked memory-access operation may include a masked store operation to conditionally load values in a memory according to the second mask expression, e.g., as described below.

[000304] In some demonstrative aspects, the second masked memory-access operation may include any other additional or alternative type of masked operation.

[000305] In some demonstrative aspects, compiler 160 may be configured to generate target code 115, for example, based on compilation of the source code 112, e.g., as described below. [000306] In some demonstrative aspects, the target code 115 may be based, for example, on the second masked memory-access operation, e.g., as described below.

[000307] In some demonstrative aspects, compiler 160 may be configured to generate the target code 115 configured, for example, for execution by a Very Long Instruction Word (VLIW) Single Instruction/Multiple Data (SIMD) target processor, e.g., processor 180.

[000308] In other aspects, compiler 160 may be configured to generate the target code 115 configured, for example, for execution by any other suitable type of processor.

[000309] In some demonstrative aspects, compiler 160 may be configured to generate the target code 115, for example, based on the source code 112 including Open Computing Language (OpenCL) code.

[000310] In other aspects, compiler 160 may be configured to generate the target code 115, for example, based on the source code 112 including any other suitable type of code.

[000311] In some demonstrative aspects, compiler 160 may be configured to compile the source code 112 into the target code 115, for example, according to a Low Level Virtual Machine (LLVM) based (LLVM-based) compilation scheme.

[000312] In other aspects, compiler 160 may be configured to compile the source code 112 into the target code 115 according to any other suitable compilation scheme.

[000313] In some demonstrative aspects, the identified mask leaf may be based, for example, on an induction variable of the loop, e.g., as described below.

[000314] In some demonstrative aspects, compiler 160 may be configured to determine the identified mask leaf, for example, based on a determination that the identified mask leaf is based on an IV of a loop including the first masked memoryaccess operation, e.g., as described below.

[000315] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions, for example, based on the identified mask leaf, e.g., as described below. [000316] In some demonstrative aspects, the AGU instructions may include memoryaccess instructions of an AGU to perform the second masked memory-access operation, e.g., as described below.

[000317] In some demonstrative aspects, compiler 160 may be configured to generate the target code 115, for example, based on the AGU instructions, e.g., as described below.

[000318] In some demonstrative aspects, the AGU instructions may include at least one of a lower bound and/or an upper bound of a memory-access range to be applied by the AGU for the second masked memory-access operation, e.g., as described below.

[000319] In some demonstrative aspects, compiler 160 may be configured to configure the AGU instructions to define a memory-access range, for example, based on the identified mask leaf, e.g., as described below.

[000320] In some demonstrative aspects, compiler 160 may be configured to configure the AGU instructions to configure the AGU to apply the memory access range for the second masked memory-access operation, e.g., as described below.

[000321] In some demonstrative aspects, compiler 160 may be configured to configure the AGU instructions to define a lower bound of the memory-access range, for example, based on the identified mask leaf, e.g., as described below.

[000322] In some demonstrative aspects, compiler 160 may be configured to configure the AGU instructions to define an upper bound of the memory-access range, for example, based on the identified mask leaf, e.g., as described below.

[000323] In some demonstrative aspects, the second mask expression may exclude the identified mask, e.g., as described below.

[000324] In some demonstrative aspects, compiler 160 may be configured to configure the second masked memory-access operation to exclude one or more IV- based mask leaves of the first masked memory-access operation, which are based on an IV of a loop including the first masked memory-access operation, e.g., as described below.

[000325] In some demonstrative aspects, compiler 160 may be configured to configure the second masked memory-access operation to exclude any IV-based mask leaves of the first masked memory-access operation, which are based on an IV of a loop including the first masked memory-access operation, e.g., as described below.

[000326] In some demonstrative aspects, compiler 160 may be configured to configure the second masked memory-access operation to include, for example, only non-IV-based mask leaves, which are not based on an IV of a loop including the first masked memory-access operation, e.g., as described below.

[000327] In other aspects, compiler 160 may be configured to configure the second masked memory-access operation to exclude only some of the IV-based mask leaves of the first masked memory-access operation.

[000328] In some demonstrative aspects, compiler 160 may be configured to configure the second masked memory-access operation to maintain, for example, one or more, e.g., some or all, non-IV-based mask leaves of the first masked memory-access operation, which are not based on an IV of a loop including the first masked memoryaccess operation, e.g., as described below.

[000329] In some demonstrative aspects, compiler 160 may be configured to determine the identified mask leaf of the first mask expression, for example, based on a criterion, which may include a requirement that all possibilities of a True logical value of the first mask expression may result from a same logical value of the identified mask leaf, e.g., as described below.

[000330] In some demonstrative aspects, compiler 160 may be configured to determine the identified mask leaf of the first mask expression, for example, based on a criterion, which may include a requirement that all possibilities of a True logical value of the first mask expression may be independent of a logical value of the identified mask leaf, e.g., as described below.

[000331] In some demonstrative aspects, compiler 160 may be configured to determine the identified mask leaf of the first mask expression, for example, based on any other additional or alternative criterion.

[000332] In some demonstrative aspects, compiler 160 may be configured to determine the identified mask leaf, for example, based on a truth table corresponding to the first mask expression, e.g., as described below. [000333] In one example, compiler 160 may compile a source code 112 of a program to be executed by a target processor, e.g., processor 180, for example, a target vector processor.

[000334] For example, complier 160 may identify a loop including a first masked memory-access operation, e.g., as follows: for(int y = 0; y < height; y++) for(int x = 0; x < width; x++) { for(int z = 0; z < depth; z++) { int index = y * ystride + x * xstride + z; char s = inpl [index]; char t = inpl [index + 1]; char Mask = ~((x < a) I (~(s >= b) & (t <= 10))); char val = masked_load(inp2+ index, 0, Mask); out[index] = val + 7 ;

}

}

}

Example (4a)

[000335] As shown in Example 4a, the first masked memory-access operation may include a first masked load operation, e.g., char val = masked J.oad(inp2+ index, 0, Mask), which may be based on a mask, e.g., Mask.

[000336] As shown in Example 4a, the first masked load operation may be based on a first mask expression, e.g., char Mask = ~((x < a) I (~(s >= b) & (t <= 10))).

[000337] As shown in Example 4a, the first mask expression may include three mask leaves. For example, the first mask expression may include a first mask leaf, e.g., (x < a), a second mask leaf, e.g., (s >= b), and/or a third mask leaf, e.g., (t <= 10). [000338] As shown in Example 4a, the first mask leaf may include an IV-based mask leaf, which may be based on an induction variable x of the loop including the first masked load operation.

[000339] As shown in Example 4a, the second and third mask leaves may include non-IV-based mask leaves, for example, as they may not be based on any induction variable of the loop including the first masked load operation.

[000340] For example, as shown in Example 4a, the second mask leaf may be based on variables 5 and b, and/or the third mask leaf may be based on a variable t.

[000341] In some demonstrative aspects, compiler 160 may be configured to identify the first masked load operation in the loop, for example, based on the source code 112.

[000342] In some demonstrative aspects, compiler 160 may be configured to determine the first mask leaf as the identified mask leaf of the first mask expression, for example, based on a determination that the first mask leaf is an IV-based leaf, e.g., as described below.

[000343] In some demonstrative aspects, compiler 160 may be configured to determine the first mask leaf as the identified mask leaf of the first mask expression, for example, based on a criterion requiring that all possibilities of a True logical value of the first mask expression may result from a same logical value of the first mask leaf, e.g., as described below.

[000344] In some demonstrative aspects, compiler 160 may be configured to determine whether or not the criterion is met with respect to the mask leaves of the first mask expression, for example, based on a truth table corresponding to the first mask expression, e.g., as described below.

[000345] In some demonstrative aspects, the first mask expression may be represented by the three mask leaves, e.g., as follows:

~(P I (~Q & R))

Expression (1) wherein, P = (x < a), Q= (s >= b), and /? = (t <= 10).

[000346] In some demonstrative aspects, compiler 160 may be configured to determine a truth table corresponding to the Expression (1), e.g., as follows:

Table (1)

[000347] As shown by the truth Table (1), the mask leaf P may be required to always be 0, for example, in order to make Mask=True. For example, as shown by the truth Table (1), the mask leaf P may be invariant in the truth table, e.g., the value of the mask leaf P may be 0 in all the entries of the truth table.

[000348] For example, based on this determination, the mask leaf P may be extracted outside of the logical expression with a negative sign (logical NOT), for example, while replacing the mask leaf P with a constant logical “0”, e.g., as follows:

~P & ~(0 I (~Q & R)).

Expression (2)

[000349] As shown by the truth Table (1), values of the other mask leaves, e.g., the leaves Q and R, may vary in the truth Table (1). For example, these mask leaves may not be invariant or don’t care. Accordingly, these mask leaves Q and R may remain in the logical expression.

[000350] As shown by Expression (2), the Expression (2) may include a constant value, e.g., 0, for example, instead of the mask leaf P. For example, as the sign of the mask leaf P is negative, the constant value of zero may be selected.

[000351] For example, Expression (2) may be logically equivalent to the Expression

(1). For example, when P = 0, the second part (~(0 I (~Q & R))) of Expression (2) may be exactly equal to the Expression (1), and the first part (~P) of Expression (2) may not change the second part of Expression (2), e.g., as ( ~P)=1. For example, the Expression

(2) may be a logical AND operation of the first part of Expression (2) with the logical value “1”, e.g., since ~P = 1. [000352] For example, when P = 1, the logical NOT operation may be equal to zero, e.g., ~P = 0. Accordingly, Expression (2) may be equal to zero. For example, as shown by the truth Table (1), Expression (1) may be zero, when P=l.

[000353] In some demonstrative aspects, compiler 160 may be configured to further simplify the Expression (2), for example, based on the equality: "0 I A = A".

[000354] For example, compiler 160 may be configured to further simplify the expression (~(0 I (~Q & R))) into the expression (Q & ~R). For example, compiler 160 may be configured to optimize, e.g., standardly optimized, the other mask leaves to be (Q \ ~R) = (s >= b) \ ~(t <= 10).

[000355] For example, compiler 160 may be configured to further simplify the Expression (2), for example, by an instruction combining (instcombine) operation, e.g., after this pass.

[000356] In some demonstrative aspects, compiler 160 may be configured to utilize a truth table to provide a technical solution to support determining a logical expression, e.g., the Expression (2), based on a first mask expression, e.g., Expression (1), for example, even with respect to relatively complex mask expressions.

[000357] In some demonstrative aspects, the truth table may be implemented to provide a technical solution to support determining a simplified logical expression based on a mask expression, for example, even with respect to mask expressions, which may not easily be simplified, for example, using one or more transformations, e.g., according to de-Morgan laws and/or any other transformation rules and/or laws.

[000358] In one example, a mask expression may include the following mask with the additional mask leaves A and B:

Mask2 = (~(P I (~Q & R)) & A) I (~(P I (~Q & R)) & ~A & B) I (~(P I (~Q & R)) & -A & ~B)

Expression (3)

[000359] For example, a truth table may be utilized to determine that the logical expression ~P & ~(0 I (~Q & R)) may be logically equivalent to the mask Mask2, for example, even in case the mask Mask2 may not be easily transformed into a simplified logical expression, e.g., based on the de-Morgan rules. [000360] In some demonstrative aspects, compiler 160 may be configured to determine a second masked memory-access operation by reconfiguring the first masked load operation, for example, based on the first mask leaf P.

[000361] In some demonstrative aspects, the second masked memory-access operation may be based on a second mask expression, which may be logically simplified, for example, compared to the first mask expression.

[000362] For example, the second mask expression may be based on the second part of Expression (2), e.g., ~(0 I (~Q & R)), which may be logically simplified, for example, compared to the Expression (1).

[000363] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions including memory-access instructions of an AGU to perform the second masked memory-access operation, e.g., as described below.

[000364] In some demonstrative aspects, compiler 160 may configure the AGU instructions based on at least one mask leaf of the first masked memory-access operation, e.g., as described below.

[000365] In some demonstrative aspects, compiler 160 may configure the AGU instructions, for example, to selectively restrict memory access of the second masked memory-access operation, for example, based on at least one mask leaf of the first masked memory-access operation, which is to be excluded from the second masked memory-access operation, e.g., as described below.

[000366] In some demonstrative aspects, compiler 160 may configure the AGU instructions, for example, to selectively restrict memory access of the second masked memory-access operation, for example, in a manner, which may be logically equivalent to the at least one mask leaf of the first masked memory-access operation, which is to be excluded from the second masked memory-access operation, e.g., as described below.

[000367] In some demonstrative aspects, compiler 160 may configure the AGU instructions based on the first mask leaf of the first masked memory-access operation, e.g., as described below.

[000368] In some demonstrative aspects, compiler 160 may configure the AGU instructions, for example, to selectively restrict memory access of the second masked memory-access operation, for example, based on the first mask leaf of the first masked memory-access operation, e.g., as described below.

[000369] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to define a memory-access range to be accessed by the second masked memory-access operation, e.g., as described below.

[000370] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to define the memory-access range, for example, based on the first mask leaf of the first masked memory-access operation, e.g., as described below.

[000371] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to selectively restrict the second masked memory-access operation to the memory-access range, which may be based on the first mask leaf of the first masked memory-access operation, e.g., as described below.

[000372] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to selectively restrict the second masked memory-access operation to the memory-access range, for example, in a way, which may be logically equivalent to the first mask leaf of the first masked memory-access operation, e.g., as described below.

[000373] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to define a lower bound and/or an upper bound of the memory-access range to be applied by the AGU for the second masked memory-access operation, e.g., as described below.

[000374] For example, compiler 160 may configure the lower bound and/or the upper bound of the memory-access range, for example, based on the first mask leaf P, e.g., as described below.

[000375] In some demonstrative aspects, compiler 160 may be configured to identify a first mask leaf in a first mask expression of a first masked memory-access operation in a loop, for example, based on a determination that the first mask leaf is based on an induction variable, e.g., an induction variable x, of the loop, e.g., as described below.

[000376] In some demonstrative aspects, compiler 160 may be configured to configure a second masked memory-access operation, for example, by reconfiguring the first masked memory-access operation based on the first mask leaf, e.g., as described below.

[000377] In some demonstrative aspects, compiler 160 may be configured to configure AGU instructions to define a lower bound, e.g., a lower bound xmin, and/or an upper bound, e.g., an upper bound xmax, of a memory-access range to be applied by the AGU for the second masked memory-access operation, e.g., as described below.

[000378] In some demonstrative aspects, compiler 160 may be configured to configure the AGU instructions to define the lower bound, e.g., the lower bound xmin, and/or the upper bound, e.g., the upper bound xmax, for example, based on a logical condition on the induction variable, e.g., an induction variable x, which may be defined by the first mask leaf, e.g., as described below.

[000379] In some demonstrative aspects, compiler 160 may be configured to translate the first mask leaf ~P = (x >= a) in the Expression (2), for example, into a bound for an AGU memory-access instruction, e.g., for the second masked memory-access operation.

[000380] For example, compiler 160 may be configured to configure an AGU lower bound (xmin) of the AGU memory-access instruction in a compiled loop, which may be based on the loop of Example 4a, e.g., as described below.

[000381] For example, compiler 160 may be configured to configure the AGU lower bound (xmin) of the AGU memory-access instruction, for example, based on the first mask leaf ~P = (x >= a) in the Expression (2).

[000382] For example, compiler 160 may be configured to configure the AGU lower bound (xmin) of the AGU memory-access instruction, for example, by setting the AGU lower bound (xmin) to the value of a (xmin=a), which may be logically equivalent to the condition of the first mask leaf ~P = (x >= a) in the Expression (2).

[000383] For example, compiler 160 may be configured to configure the AGU instructions of the AGU memory-access instruction in a compiled loop, which may be based on the loop of Example 4a, for example, to define an AGU lower bound (xmin = a), which may be based on the first mask leaf ~P = (x >= a) in the Expression (2), e.g., as follows: agul = allocate_agu(“load”); set_base(agul, inpl)

// ... other agul parameters agu2 = allocate_agu(“load”); set_base(agu2, inp2) set_x_minmax(agu2, a, width);

// ... other agu2 parameters agu3 = allocate_agu(“store”); set_base(agu3, out);

// ... other agu3 parameters

Loop: char s = agul.load(); char t = agul.load(); char NewMask = (s >= b) I (t > 10); char val = agu2.masked_load(0, NewMask); agu3.store(val + 7);

Example (4b)

[000384] As shown in Example 4b, the compiled loop may include a masked memoryaccess operation, which may include a masked load operation based on the second mask (NewMask), e.g., char val = agu2.masked_load(0, NewMask).

[000385] As shown in Example 4b, the masked load operation may be based on the second mask, e.g., NewMask, which may be defined based on the second mask expression, e.g., char NewMask = (s >= b) I (t > 10).

[000386] As shown in Example 4b, the second mask expression may be based on the second part of Expression (2), which may be logically simplified, for example, compared to the Expression (1).

[000387] As shown in Example 4b, the second mask expression may include only two mask leaves, for example, two non-IV-based mask leaves, e.g., ~(s >= b), and t (t < = 10).

[000388] As shown in Example 4b, the second mask expression may include only non-IV-based mask leaves. [000389] As shown in Example 4b, the second mask expression may exclude any IV- based mask leaves of the mask Expression (1).

[000390] As shown in Example 4b, the second mask expression may exclude any IV- based mask leaves.

[000391] As shown in Example 4b, the second mask expression may not include the first mask leaf P of Expression (1). For example, the second mask expression may exclude the first mask leaf P, which may be based on the induction variable x.

[000392] In some demonstrative aspects, as shown in Example 4b, compiler 160 may assign a first AGU, e.g., agul, for example, to load data from a first input pointer, e.g., inpl.

[000393] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate the compiled loop to include a first load instruction, e.g., char s = agul. load] ), for example, to load by agul a char value, which is based on the pointer inpl [index] , into a char variable 5.

[000394] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate the compiled loop to include a second load instruction, e.g., char t = agul. load] ), for example, to load by the agul a char value, which is based on the pointer inpl [index+ 1 ], into a char variable t.

[000395] In some demonstrative aspects, as shown in Example 4b, compiler 160 may assign a second AGU, e.g., agu2, for example, to perform a masked load operation, for example, to load data from a second input pointer, e.g., inp2, according to the mask NewMask.

[000396] In some demonstrative aspects, as shown in Example 4b, compiler 160 may configure an AGU instructions for the second AGU, for example, to set a lower bound and an upper bound for a dimension of the agu2 corresponding to the induction variable x.

[000397] In some demonstrative aspects, as shown in Example 4b, compiler 160 may set the lower bound and/or the upper bound of the second AGU, which to perform the masked load instruction, for example, based on the first leaf of Expression (1), e.g., ~ P=~ (x<a). [000398] In one example, setting the lower bound for the masked load instruction to be performed by the second AGU according to the condition (x>=a) may be logically equal to the leaf ~ P=~ (x<a).

[000399] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate an AGU instruction, e.g., set_x_minmax(agu2, a, width), to set to a the lower bound for the dimension of the agu2 corresponding to the induction variable x.

[000400] For example, the AGU instruction, e.g., set_x_minmax(agu2, a, width), may restrict the agu2, for example, to load data from the pointer inp2, for example, only when the IV x is equal to or greater than a. For example, this restriction may be in accordance with the condition of the first leaf of the Expression (1), e.g., ~ P=~ (x<a)= (x>=a).

[000401] In some demonstrative aspects, as shown in Example 4b, compiler 160 may set the upper bound of the AGU instruction for agu2 to width, for example, to load data from the pointer inp2, for example, according to the condition of the IV x in the inner loop of Example 4a, e.g., for(int x = 0; x < width; x++).

[000402] In some demonstrative aspects, as shown in Example 4b, the first mask leaf of Expression (1) may become redundant, for example, when configuring the agu2 according to the instruction set_x_minmax( agu2, a, width ).

[000403] For example, the mask NewMask may not be required to compute the condition ~(x<a)= (x>=a), for example, as this condition may already be maintained by setting the low bound of the agu2 (xmin=d).

[000404] In some demonstrative aspects, as shown in Example 4b, compiler 160 may exclude the mask leaf P from the mask NewMask.

[000405] For example, as shown in Example 4b, the masked load instruction char val = agu2.masked_load(0, NewMask) may be based on the mask NewMask.

[000406] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate the compiled loop, which may be configured, for example, to define the second mask expression, for example, based on the mask NewMask, e.g., char NewMask = (s > = b) I (t > 10), which may exclude the first mask leaf P. [000407] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate the compiled loop to include a third load instruction, e.g., char val = agu2.masked_load(0, NewMask), for example, to load by agu2 a char value based on the pointer inp2 into a char variable val, for example, based on the mask NewMask.

[000408] In some demonstrative aspects, as shown in Example 4b, compiler 160 may assign a third AGU, e.g., agu3, for example, to store data based on an output pointer, e.g., out.

[000409] In some demonstrative aspects, as shown in Example 4b, compiler 160 may generate the compiled loop to include a store instruction, e.g., agu3.store(yal + 7), for example, to store by agu3 a result of the sum val+7 to the output pointer out.

[000410] Reference is made to Fig. 4, which schematically illustrates a method of compiling code for a processor. For example, one or more operations of the method of Fig. 4 may be performed by a system, e.g., system 100 (Fig. 1); a device, e.g., device 102 (Fig. 1); a server, e.g., server 170 (Fig. 1); and/or a compiler, e.g., compiler 160 (Fig. 1), and/or compiler 200 (Fig. 2).

[000411] In some demonstrative aspects, as indicated at block 402, the method may include identifying a first masked memory-access operation based on a source code, wherein the first masked memory-access operation is based on a first mask expression including one or more mask leaves. For example, compiler 160 (Fig. 1) may be configured to identify the first masked memory-access operation in a loop operation, for example, based on the source code 112 (Fig. 1), e.g., as descried above.

[000412] In some demonstrative aspects, as indicated at block 404, the method may include determining a second masked memory-access operation, for example, by reconfiguring the first masked memory-access operation based on an identified mask leaf of the one or more mask leaves. For example, the second masked memory-access operation may be based on a second mask expression, which is logically simplified compared to the first mask expression. For example, compiler 160 (Fig. 1) may be configured to determine the second masked memory-access operation by reconfiguring the first masked memory-access operation, based, for example, on the identified mask leaf, e.g., as descried above. [000413] In some demonstrative aspects, as indicated at block 406, the method may include generating target code based on compilation of the source code, wherein the target code is based on the second masked memory-access operation. For example, compiler 160 (Fig. 1) may be configured to generate target code 115 (Fig. 1), for example, based on the second masked memory-access operation, e.g., as descried above.

[000414] Reference is made to Fig. 5, which schematically illustrates a product of manufacture 500, in accordance with some demonstrative aspects. Product 500 may include one or more tangible computer-readable (“machine -readable”) non-transitory storage media 502, which may include computer-executable instructions, e.g., implemented by logic 504, operable to, when executed by at least one computer processor, enable the at least one computer processor to implement one or more operations at device 102 (Fig. 1), server 170 (Fig. 1), and/or compiler 160 (Fig. 1), to cause device 102 (Fig. 1), server 170 (Fig. 1), and/or compiler 160 (Fig. 1) to perform, trigger and/or implement one or more operations and/or functionalities, and/or to perform, trigger and/or implement one or more operations and/or functionalities described with reference to the Figs. 1-4, and/or one or more operations described herein. The phrases “non-transitory machine-readable medium” and “computer- readable non-transitory storage media” may be directed to include all computer- readable media, with the sole exception being a transitory propagating signal.

[000415] In some demonstrative aspects, product 500 and/or machine-readable storage media 502 may include one or more types of computer-readable storage media capable of storing data, including volatile memory, non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and the like. For example, machine-readable storage media 502 may include, RAM, DRAM, Double-Data-Rate DRAM (DDR-DRAM), SDRAM, static RAM (SRAM), ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content addressable memory (CAM), polymer memory, phase-change memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk, a hard drive, and the like. The computer-readable storage media may include any suitable media involved with downloading or transferring a computer program from a remote computer to a requesting computer carried by data signals embodied in a carrier wave or other propagation medium through a communication link, e.g., a modem, radio or network connection.

[000416] In some demonstrative aspects, logic 504 may include instructions, data, and/or code, which, if executed by a machine, may cause the machine to perform a method, process and/or operations as described herein. The machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware, software, firmware, and the like.

[000417] In some demonstrative aspects, logic 504 may include, or may be implemented as, software, a software module, an application, a program, a subroutine, instructions, an instruction set, computing code, words, values, symbols, and the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a processor to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, machine code, and the like.

EXAMPLES

[000418] The following examples pertain to further aspects.

[000419] Example 1 includes a product comprising one or more tangible computer- readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one processor, enable the at least one processor to cause a compiler to identify a first masked memory-access operation based on a source code, wherein the first masked memory-access operation is based on a first mask expression comprising one or more mask leaves; determine a second masked memoryaccess operation by reconfiguring the first masked memory-access operation based on an identified mask leaf of the one or more mask leaves, wherein the second masked memory-access operation is based on a second mask expression which is logically simplified compared to the first mask expression; and generate target code based on compilation of the source code, wherein the target code is based on the second masked memory-access operation.

[000420] Example 2 includes the subject matter of Example 1, and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask leaf based on a criterion relating to an effect of the identified mask leaf on a logical value of the first mask expression,

[000421] Example 3 includes the subject matter of Example 2, and optionally, wherein the criterion comprises a requirement that all possibilities of a True logical value of the first mask expression result from a same logical value of the identified mask leaf.

[000422] Example 4 includes the subject matter of Example 2 or 3, and optionally, wherein the criterion comprises a requirement that all possibilities of a True logical value of the first mask expression are independent of a logical value of the identified mask leaf.

[000423] Example 5 includes the subject matter of any one of Examples 1-4, and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask leaf based on a determination that the identified mask leaf is based on an Induction Variable (IV) of a loop comprising the first masked memory-access operation.

[000424] Example 6 includes the subject matter of any one of Examples 1-5, and optionally, wherein the instructions, when executed, cause the compiler to configure Address Generation Unit (AGU) instructions based on the identified mask leaf, wherein the AGU instructions comprise memory-access instructions of an AGU to perform the second masked memory-access operation, wherein the target code is based on the AGU instructions.

[000425] Example 7 includes the subject matter of Example 6, and optionally, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define a memory-access range based on the identified mask leaf, the memory access range to be applied by the AGU for the second masked memory-access operation. [000426] Example 8 includes the subject matter of Example 7, and optionally, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define at least one of a lower bound or an upper bound of the memoryaccess range based on the identified mask leaf.

[000427] Example 9 includes the subject matter of any one of Examples 1-8, and optionally, wherein the second mask expression excludes the identified mask leaf.

[000428] Example 10 includes the subject matter of any one of Examples 1-9, and optionally, wherein the instructions, when executed, cause the compiler to configure the second masked memory-access operation to exclude one or more Induction Variable (IV) based (IV-based) mask leaves of the first masked memory-access operation, which are based on an IV of a loop comprising the first masked memory-access operation.

[000429] Example 11 includes the subject matter of any one of Examples 1-10, and optionally, wherein the instructions, when executed, cause the compiler to configure the second masked memory-access operation to exclude any Induction Variable (IV) based (IV-based) mask leaves of the first masked memory-access operation, which are based on an IV of a loop comprising the first masked memory-access operation.

[000430] Example 12 includes the subject matter of any one of Examples 1-11, and optionally, wherein the instructions, when executed, cause the compiler to configure the second masked memory-access operation to maintain one or more non Induction Variable (IV) based (non-IV-based) mask leaves of the first masked memory-access operation, which are not based on an IV of a loop comprising the first masked memoryaccess operation.

[000431] Example 13 includes the subject matter of any one of Examples 1-12, and optionally, wherein the instructions, when executed, cause the compiler to configure the second masked memory-access operation to include only non Induction Variable (IV) based (non-IV-based) mask leaves, which are not based on an IV of a loop comprising the first masked memory-access operation.

[000432] Example 14 includes the subject matter of any one of Examples 1-13, and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask leaf based on a truth table corresponding to the first mask expression. [000433] Example 15 includes the subject matter of any one of Examples 1-14, and optionally, wherein a count of mask leaves in the second mask expression is less than a count of mask leaves in the first mask expression.

[000434] Example 16 includes the subject matter of any one of Examples 1-15, and optionally, wherein the second masked memory-access operation comprises a masked load operation to conditionally load values from a memory according to the second mask expression.

[000435] Example 17 includes the subject matter of any one of Examples 1-16, and optionally, wherein the second masked memory-access operation comprises a masked store operation to conditionally store values in a memory according to the second mask expression.

[000436] Example 18 includes the subject matter of any one of Examples 1-17, and optionally, wherein the source code comprises Open Computing Language (OpenCL) code.

[000437] Example 19 includes the subject matter of any one of Examples 1-18, and optionally, wherein the computer-executable instructions, when executed, cause the compiler to compile the source code into the target code according to a Low Level Virtual Machine (LLVM) based (LLVM-based) compilation scheme.

[000438] Example 20 includes the subject matter of any one of Examples 1-19, and optionally, wherein the target code is configured for execution by a Very Long Instruction Word (VLIW) Single Instruction/Multiple Data (SIMD) target processor.

[000439] Example 21 includes the subject matter of any one of Examples 1-20, and optionally, wherein the target code is configured for execution by a target vector processor.

[000440] Example 22 includes a compiler configured to perform any of the described operations of any of Examples 1-21.

[000441] Example 23 includes a computing device configured to perform any of the described operations of any of Examples 1-21.

[000442] Example 24 includes a computing system comprising at least one memory to store instructions; and at least one processor to retrieve instructions from the memory and execute the instructions to cause the computing system to perform any of the described operations of any of Examples 1-21.

[000443] Example 25 includes a computing system comprising a compiler to generate target code according to any of the described operations of any of Examples 1-21, and a processor to execute the target code.

[000444] Example 26 comprises an apparatus comprising means for executing any of the described operations of any of Examples 1-21.

[000445] Example 27 comprises an apparatus comprising: a memory interface; and processing circuitry configured to: perform any of the described operations of any of Examples 1-21.

[000446] Example 28 comprises a method comprising any of the described operations of any of Examples 1-21.

[000447] Functions, operations, components and/or features described herein with reference to one or more aspects, may be combined with, or may be utilized in combination with, one or more other functions, operations, components and/or features described herein with reference to one or more other aspects, or vice versa.

[000448] While certain features have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the disclosure.