ptlj Many high speed electronic ays tests operate with critical timing requirements that dictate a need to generate & periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of eompnimg integrated circuits and the growing tread to include several computing devices on the same board present a challenge with respect to synchronizing the time names of all the components

[002] While the operation of all components in the system should he highly synchronized, fe,, the maximum skew in time between significant edges of the internally generated clocks of ail the components should be minimized, u is not enough to feed the external clock of the system to all the components. This is because di ITerem chips may have diftcuent manufacturing parameters, which when taken together with additional factors such ns ambient temperature voltage, and processing variations may lead to large differences i» the phases of the respective chip generated clocks

[003] Synehr oumation can he aehiev ed by using a urn tug circuit, such as a digital delay locked loop (DOLL) circuit, to detect the phase difference between dock signals of the same frequency and produce a digital signal related to the phase difference. During initialization, DDLL circuits may require a relatively large number of clock cycles to synchronise. ¾ conjunction with a DLL circuit, an open-loop topology may be used, such as a measure- controlled delay (hi CD) circuit where a timing measurement directly controls a variable delay. MOD circuits exhibit tt last lock capability te g-- within 1-4 clock cycles alter initialization}. The MCD circuit generates an imual measurement, and the DDLL takes over to mat mam the lock and track v ariations over rime

[004] As part of the process of obtaining a locked condition alter initialization a fine delay ts adjusted after a coarse delay is initially set. The line delay adjustment may require more time than desirable due to the manner in which the fine delay is adjusted. Therefore, it may he desirable to reduce the time for delay to he adjusted to obtain a locked condition.

SIJMliMX

fOMJ AppaMnses and methods for adjusting a phase mixer circuit are disclosed. To an aspect of the disclosure an apparatus includes a shift moisten which includes & plurality of registers coupled in senes to one another. Hie plurality of registers ;u¾ grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers, and die second group of registers Includes a third register. The first and second registers of die first group of registers at» configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store fist output of the third register responsive to a shift clock.

[006] In another aspect of the disclosure an apparatus includes a phase mixer circuit and a shift register. 1¾e phase mixer cireuft is configured to receive first and second clocks and provide an output dock based on the first and second clocks, wherein die first and second docks have a phase difference relative to oh e another. The shift register is configured to provide control signals to the phase mixer entail to adjust a delay of the Output clock. The shi ft register includes a plurality of registers coupled in series, each register of the plurality of registers is configured to receive a shift clock and further configured to store a respective data value and provide a respective one of the control signals based on the respective val ue stored. The shift register is configured in a first mode to change the respective data values stored by the plmlity ofregisters by more than one register at a time responsive to the shift dock and configured masecondmodetoebange the respectivevaltK¾¾ored for the plurality of registers one register at a time responsive to the shift clock.

[007] In another aspectof the disclosure, a method mdudeS adjdsting adelay ofa phasertiixer circuit by minimum delay adjustments during normal operation of the phase mixer circuit, and adjusting the delay of the phase mixer circuit by greater than the minimum delay adjustments during initialization of the phase mixer circuit.

[008] In another aspect of the disetosure, a method inc ludes changing data values stored by a plurality of shift registers, wherein the data values are changed by groups of Shift registers of the pluralityof shiftregfetemduritiga first mode of opeMton, aid wherein die data values ath changed by individual shift refers of theplurality of shift registers during a second mode of operation.

§EifcT.jp>ssmim..O£..ia£.eMmag·

Figure I is a block diagram of an apparatus according to an embodiment of the disclosure.

[010] Figure 2 is » block diagram o f « clock generator circuit according to an embodiment of the disclosure. [011] Figure 3 is a flow diagram of a typical initialization operation for a clock generator circuit

[012] Figure 4 is a block diagram of an adjustable delay circuit according to an embodiment ofthe disclosure,

[013] Figure 5 is a block diagram of a fine phase adjust cirfeuit according to an embodiment of the disclosure.

[014] Figure 6 is a block diagram of a phasemixer circuit according to an embodiment ofthe disclosure.

[015] Figure 7 is a schematic diagram ofa driver citcuit accordingtoan embodiments of the disclosure.

[016] Figure 8 is schematic diagram of ashift register circuit aCcdrding to an embodiment of tin; disclosure.

[017] Figure 0 is a schematic diagram of a shift register according to an embodiment of the disclosure.

[018] Figures lOA-lOD illustrate various examples of deration for a shift register circuit according to various embodiments of tire disclosure;

[019] Figure 1 1 illustrates an example operation for a shift register circuit according to various embodiments of tire disclosure.

[020] Figure 12 is a schematic diagram of a shift register circuit according to an embodiment Of the disclosure.

[021] Figures 13A-13G illustrate various examples of operation for a shift register circuit according to various embodiments of the disclosure.

[022] Certain details are set fortb below to provide a sufficient understanding of examples of the disclosure. However, it will be clear ip; one having skill in the art that examples of the disclosure may be practiced wi thout these particular details. Moreover, tire particular examples described herein should not be construed to !imii the scope of the disclosure to these particular examples. In other instances, well-known circuits; control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring embodiments of the disclosure. Additionally, terms such as "couples" and "coupled" mean that two components may be directly Pr indirectly electrically coopted. Indirectly coupled may imply that two components are coupJed through one or mote inteonediate c<8itpc«t«its.

[023] Figure 1 is a Mode diagram of an apparatus according to an embodiment of the disclosure. The apparatus may be a semiconductor device 100, and will be referred as such. In some embodiments, the semiconductor device 100 mayinclude, without limitation, aDRAM device, sock as low power DDR (LPDDR) memory integrated into a single semiconductor chip, for example. The semiconductor device lOO includes a memoty array ISO. The memory array 150 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality Of bit lines BL, raid a plurality of memory cells MC arranged at intersections of the plurality ofword Imes WL andthe plurality of bit lines BL. Tbeseleciion oftheword lineWL is performed by a row decode 140 and tile selection of the Mtline BL is perfarmed by a column decoder 145, Sense amplifiers (SAMP) are located for their corresponding bit lmes BL and connected to at least one respectlve local 1/O Jine pair (LIOT/B), which is in turn coupled to at least respective one main VO line pair (MIdT/B). via transfer gabs (TO), which function as switches.

[024] Thesemiconductor device 100 may employ a phna% of external terminals that include command terminals an d address terminals coupled to a command bus and an address bus to receive Commands COM and addresses ADD and BADD, clock terminals id refeeiVe clocks CLKT and CLSKB, strobe clock teminals to provide or recrave strobe docks DQS and DQSB, dam terminals DQ and DM, and power supply terminals VODQand VSSQ-

[025] The address terminals may be supplied with an address ADD and a bank address BADD, for example, from a memory controller. The address ADD and the bank address BADD supplied to the address terminals are transferred, _: Via an address input circuit I02, tb rat address decoder ll2. The addressdeepder 112 receives theaddress and suppliesadecoded row address XADD to the row decoder 140, and a decoded column address YADD to the column decoder 145, The address decoder 112 also receives the bar* address and supplies a decoded bank address BADD to the row decoder 140 the columndecoder 145.

[026] The command terminals may be supplied with command COM from, for example, a memory controller. The command may be provided as internal command signals to a command decoder 115 via the command input circuit 105. The command decoder 115 includes circuits to deeode the internal command signals to generate various internal signals and commands for perforating operations. For example, the command decoder 115 may provide a row command signal to select a word hire and a column command signal to select a bit line. [027] When a read command is received and a row address and a column address are timely supplied with the road command, read data is road from a memory ceil in Che memory array 150 designated by the row address and cohimn address, I¼read cemmattd is received by the command decoder 115, which provides internal commands to input/output circuit 160 to that read data is output to outside Soto the data temitnais DQ via read/write amplifiers 155, and strobe clocks DQS and DQSB areprovided to outside front the strobe dock terminals.

[028] Whenthe write command is received and a row address and a cd umn addross are timely supplied with this command, then write darn is supplied to the data terminals DQ according to the DQS and DQSB strobe docks provided to the strobe clodctermtnate. A data mask may be provided to the data terminate DM to mask portions of the data when written to memory. The write comniand is received by the command decoder 115, which provides internal commands to the input/output circuit 160 so (hat the write data is received by data receivers in the input/output circuit 160, and supplied via the inputtoutput circuit 160 and the road/write amplifiers 155 to the memory array 150. The write data is written in die memory cell designated by the row address and the column address.

[029] The clock terminate and data dock terminals are supplied with external clocks. The external clocks CLKT mid CLKB aro supplied to to* input buffer 120. The CUCT and CLKB docks are complementary. The input buffer 120 generates an internal clock ICLK based on the CLKT and CLKB clocks. The ICLK dock is provided to an internal clock generator 122.

[030] the internal clock generator f 22 provides variou$ internal clocks based on the ICLK clock, The internal clocks may be used for toning toe operation of various internal circuits, For example, the clocks may be provided to the input/output circuit 160 for timing the operation of the mputfoutput circuit 160 to provide and receive data on the data terminals DQ. The internal clock generator 122 may alto pfovkje strobe clocks DQS and DQSB based on fob ICLK clock. The DQS and DQSB clocks may be provided by the semiconductor device 100 and used by other devices to time the receipt of data DQ, fm example, for a roadoperation. An input/output buffs ^* 162 receives strobe clocks that are provided to the semiconductor device 100, for example, for a write operation, and provides strobe clocks, for example, for a read operation. The input/output buffer 162 proyfoes an internal strobe clocks to toe input/output circuit 160 for controlling an input timing of write data, and receives internal strobe clocks to be provided as extema! strobe clocks.

[031] The power supply terminals are supplied with power supply potentials VDDQ and VSSQ. the power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 16f). The power si¾¾>ly potentials VDBQ and VSSQ are used for the input/output circuit 160 so thatpower supply noise generated by die input/cmiput circuit 160 docs not propagate to the other circuit Modes.

[032] Fiynt 2 isa block diagr$unofaciockg$rieratdrcijrctiit 200accordi»|toa« embodiment bf the disclosure. The dock generates circuit 200 may be included in the internal clock generator 122 of Figure 1 in some embodiments of Be disclosure. In such embodiments, the ICLK clock is provided to Be clock generator circuit 200 as an input clock CLKS.

[033] The clock generator circuit 200 may be a delay-locked loop (DLL) circuit. The clock generator circuit 2O0 includes an adjustable delay line 210 that receives the input dock CLKS and provides an output dock DLLR having a delay relative to the CLKS dock. The adjustable delay line 210 includes a coarse delay line and a fine phase adjust circuit (not shown) that provide delay to the CLKS clock. Tbe coarse delay line may include series coupled unit delay stages that ara controlled to adjust the delay by a unit delay time; Fes- example, the a unit delay time may be added by activating a unit delay stage and removed by deactivating the unit delay stage. The fine phase adjust circuit may te ccmirolled to provide finer dock timisg adjustmeut (e.g., fine delay) than * unit delay stage.

[034] The delay provided by the adjustable delay line 210 is controlled hy phase information Base Into provided by a phase detector circuit 220. The Phase Info represents a phase difference between the CLKS clock mid a feedback clock FB. The FB dock is based on the DLLR clock, tor example, having delay relative to Be DLLR dock. The delay relative to Be DLLR clock of Be FB clock may be related to propagation delays of circuits through which the DLLR dock propagates (e.g, signal buffer circuits, signal lines, clock tree circuits, etc.) before being provided to a circuit that operates according to the DLLR Clock. AS the timing Of B6 DLLR dock is adjusted by the aBastable deiay ime 2J0, the timing ofthe FB dock is alto adjusted. The adjustable delay line 210 is adjusted to reduce the phase difference between the CLKS and FB clocks.

[035] The Phase Info is provided to an ayerajpng filter 230 which performs low pass filtering on the Phase Info. The averaging filter 230 provides the filtered Phase Mo as control signals Shift to the adjustable delay line 216. By lew pass filtering the Phase Info, the delay bf Be adjustable delay line 210 is adjusted more smoothly instead of being adjusted with every change of Be Phase Mo.

[036] In operation, the adjustable delay line 21 ti is adjusted imtil the CLKS and FB clocks are in phase, as radicated by Be Phase Mb (representedby Be Shift signal). After the CLKS and FB clocks are in phase and foe Shift signal remains unchanged for a number of clock cycles, a phase lock filter 240 provides an inactive(e.g., lQw logic level) control signal Unlocked to a lock control circuit 250, In turn, the lock control circuit 250 provides an active fe.g., high logic level) control signal SyhcLock indicating that foe CLKS and FB clods are m phase and a “locked"’ condition has been achieved. The SyncLock signal is provided to a power control circuit 260 that provides control signals DtlFPOnF and DHPDOnF, which may be used to control foe clock generator ciFcuft 200 to enter a lower power operating condition to reduce power consumption after a locked condition is achieved.

[037] Achieving a locked Condition feat the clock generator circuit 200 may be lime consuming, for example, taking hundreds of clock cycles of the CLKS clock, lids may especially be foe case idler foe clock getierator circuit 200 is initialized, for exampie, when initially powered up or reset.

[038] Figure ! i s a flow diagram of a typical mitialization operation !OO for a dock generator circuit, for example, clock generator circuit 200.

[039] At step 310, foe clock generator circuit is reset (e.g,, power up, reset _s tic.) to begin imtializatron, At step 320 a loop delay of foe clock generator circuit is measured during a measure initialization operation to determine an initial delay setting, as represented by a Measure Signal. The loop delay offoe ddck generator cireuit may be a propagation delay of foe CLKS clock through the circuits of the dock generator circuit when providing the FB clock. For example, with reference to the clock generator circuit 200 of Figure 2, foe loop delay may include foe propagation delay ofthe CLKS clock through the adjustable delay line 210 set with minimal delay, and other circuits of the dock path before returning as the FB dock tothe phase detector circuit 220.

[040] When themrsasute initializatidi Operation pf stop 320 «completed, tfteMeasure Signal is asserted, and a coarse delay of the adjustable delay circuit & set to an initial delay and the further adjusted over several clock cycles at step 330. Following foe clock cycles of coarse delay adjustment, a control fotproyh «eMs asserted to the coarse delay adjustment and a fine delay of foe adjustable delay cirouit is then adjusted over several clbek cycles a? Step 340, Foltowingthe clock cycles of fine delay adjustment, a Control signal SyncMtLock is asserted to indicate completion of the fine delay adjustment, hi the embodiment shown in Figure 3, foe coarse delay is adjusted over 32 clock cycles of foe CLKS dock and foe tips delay is adjusted over 64 clock cycles of foe CLKS clock. However, foe number of clock cycles for the coarse delay adjustment and/or the fine delay adjustment may be greater car less than shown for other embodiments of the disclosure.

[041] With the SyncInitLock signal asserted following step 340, a count is reset and a number of Clock cycles aremeasured at Step 350 to determine whether a locked condition for die clock generator ciieuifhas been achieved. A locked condition is considered achieved when a count of dock cycles has reached a count threshold while the SynelnitLock signal is asserted. Counting of foe number of dock cycles and determining whether foe coum threshold # reached may be performed by a filter circuit (e.g.„ referenced as a“PbaseNotlqual: filter circuit at step 350). once the count threshold is reached* the SynCLock Signal is asserted at Sep 360 to indicate a locked condition. However, if the SynclnitLodi sigrial is deasserted before tie count readies the threshold (indicating dial the fine delay was adjusted due to a phase difference between CLKS and FB clocks), the count is reset. Thus, when the count readies the threshold, there is assurance that a locked condition has been achieved. in the embodiment shown in Figure 3, the count threshold is 158 clock cycles before a locked condition is considered achieved However, the number ofclockcycles for toe count threshold may be greater or less than shown for other embodiments of the disclosure.

[042] The setting of toe coarsedelay to an initial delay as previously described with reference to Figure 3 typically reduces the time tor toe clock generator ciriaiit to achieve a locked condition, as compared to incrementally adjusting the coarse delay following reset. However, when further coarsely adjusting the initial coarse delay by a unit delay causes the Phaselnfo (and toe Shift) signal to search between adding and removing the unitdel&y, assertion of toe lnternalLock signal may be deteyed. That is, toe unit delay of the adjustable delay circuit may be too targe a Step to provide equilibrium for the coarse delay adjustment.

[043] Figure 4 is a block diagram of an adjustable delay circuit 400 according to ^an embodiment of the disclosure. The adjustable delay circuit 400 may he included in toe adjustable delay circuit 210 of Figure 2 in some embodimentsof thedisclosure.

[044] The adjustable delay circuit 400 tocludes a coarse delay line 410 and a fine phase adjust circuit 420. The coarse delay line 410 includes a plurality of unit delay stages, of which, unit de!ay ¾ages 4 l2(«Hi2{2) ate show». Each of the unit delay stages 412 provides a unit delay tone when acti vated, to some embodiments of tod disclosure, the unit delay time of a unit delay stage is provided by series coupled logic gates, which when activated, may be represented by series coupled inverter circuits, as shown in Figure 4. the fine phase adjust circuit 420 receives a clock O provided by the unit delay stage 412(0) and actock E provided by the unit delay stage 412(1). The E clock is phase shifted relative to die O clock due to the unit delay time of unit delay stage 432(1}.

[045] The fine phase adjust eircuit420 provides an outputclock DLLR that is based on the O and E docks. For example, (he O and E clocks are weighted and combined by the fme phase adjust circuit 420 to provide the DLLR dock. The weighting of the O and E clocks is controlled by control signal MIX. The timing of the DLLR dock may be sdiusted by dinging the weighting of the O and E clods. For example _* the timingofthe DLLR clock may be adjusted over die phase difference of the O clock and the E clock, which in Figure 4 is shown to correspond to One unit delay time Of a unit delay stage. Ibe range ofadjosttnent ofthe DLLR dock is over the phase difierence between the 0 clod and the E clock As an example, where the O and E docks ate weighted evenly, the fine phase adjust circuit 420 provides a DLLR dock having a timing at halfway between the phase difference between the O dock and the E dock.

[046] Figure 5 is a block diagram of a fine phase a#u$t circuit 500 according to an embodiment of the disclosure The fine phase adjust circuit 500 may be included in the fine phase adjust circuit 420 of Figtire 4 in some embodimmis ofthe disclosure.

[047] The fine phase adjust circuit S00 includes a phase mixer circuit $10 and a shift register 520. The phase mixer circuit 510 receives input docks O and E. The O and B clocks have a phase difference between them. The phase difference between toe O and E clacks may be provided by toe E dock having a delay relative to the O dock. The O and E clocks may be provided by, tor example, a coarse delay line having umt delay stages, and toe O and E clocks may have a phase difference corresponding to toe delay of a unit delay stage. The phase mixer circuit 510 combines the O and E c!ocks as weighted by a control signal SHFT to provide an output dock DLLR. The SHFT signal «provided by the shift register 520. The SHFT signal may be a multibit signal in some ents of toe disclosure. The shift register520 provides the SHFT signal based on a control signal MIX, which indicates the weighting of the O and E clocks for providmgthe DLLR clock. The shift register 520 may operate in a mode where the delay provided by the phase mixer circuit $10 is adjusted incrementally, tor example, during normal operations. The merementa! delay adjustmentprovides a minimum delay atljustinrot. Additionally, the shift register 520 may operate in a mode where the delay provided by toe phase mixer circuit 510 is adjusted in larger stops toan when adjusted incrementally, for example, tollowmg/dnring initialization of a clock generator circuit toat includes toe fine phase adjust circuit 500. The delay adjustment by iarger steps provides larger adjustments than the minimi»» delay adjustments.

Figure 6 is a block diagram of a phase mixer circuit <>00 according to an embodiment of the disclosure, The phase mixer circuit 600 may be ineluded in the phasemixer circuit 510 bf Figure 5 in sdme emlxxiiments ofthe disclosure.

[049] The phase mixer circuit 600 includes a driver circuit 610 and a driver circuit 620. The driver circuit -.610 receives an input clock O and provides an output clock DRVO to an output node 630. The drive strength of dee driver circuit 610 when providing the DRVO clock is controlled by a control signal SHIT. The driver circuit 620 receives an input clock E and provides anoutput clock DRVE to theoutpat node 630. The drive strength of the driver circuit 620 when providing the DEVEcUxk is controlled by the SHFT signal. Anoutput clock DLLR is provided at the output node 630. The DLLR clock is a combination of theDRVO and DRVE docks, For example, the DRVO and DRVE clocks ate combined together at the output node 630 to provide the DLLR dock.

[050] A timing of the DLLR clock may be adjusMbychangingthe weighting ofthe O block and die E clock in providing the DRVO and DRVE clocks, respectively. Changing the weighting results in changing the drive strengths ofthe respective driver circuits 610 and 620. The range of timing adjustment forthe DLLR clock correSponds to a phase difference between the O clock and the E clock. The weighting for the O and E clocks may be changed to adjust a timing of the DLLRelock over the rangeprovided by the phase difference between the O and E clods. For example, when the O dock and E clock am weighted equally, the driver strengths ofthe driver circuits 610 and 620 areequal, and the resulting DLLR clock has a timing relative to the O clock that isone half ihe phase difference between the O clock and the E dock. When theO e!dck has full weight abd the E clock has no weight, the driver circuit 610 is at maXimtmi drive strength and the driver circuit 620 is at minimum drive strength, resulting in a DLLR dock that is nearly in phase with the O clock. Conversely, when the E clock has lull weight and the O dock has no weight, the driver circuit 610 is at minimum chive strength and the driver circuit 620 is at maximum drive strength, resulting in a DLLR clock that is nearly in phase With the E dock.

[051] Figure 7 is a schematic diagram of a driver circuit 700 according to an embodiment of thedisclosure The driver circuit 700may beineluded in ^edriver circuit 610 and/br the driver circuit 620 in some embodiments of the disclosure, The (fewer circuit 700 receives an input dock 1NCK. and a control signal SHFT, The SHFT sijpial may include a plurality of control signals. The 1NCK, clock may be either the 0 clock or the E clock in embodiments where the drive- cireuitTOO is included in the driver circuit did and/otdriver circuit 620.

[052] The driver circuit 700 includes signal driver circuits 719(0)~719(9), each of which receives the lNCK clock. Each of the signal driver circuits 710(0>710(9) recrivesatospective tme of the eontrol signals included in the SHFT signal. For exampJe, the signal driver circuit 710(0) receives the SHFT(0) signal, the signal driver circuit 710(1) receives the SHFT(1) signal, the signal drive· circuit 710(2) receives the SHFT{2) signal, and so cm. Each of ihe signal driver circuits 710(ti>710(9) is activated by an active respective SHFT signal (e.g., active high tope level). When activated, a signal driver circuit 7 Ml drives the IN€K clock to a common output node (not shown in Figure 7) at wMch an output clock is provided. The signal driver circuits 719 are“wired OR” coupled to the common output node.

[053] The output clock may be either the DRVG clock or tie DRVE clock to embodiments where the driver cimiit 709 is toetoded in the driver citcait OlO and/or driver circuit (S¾(k The «milting output clock is driven with a drive strength that is seated to the number of signal driver circuits 7iti(0).710(9) that are activated. For example, the output cloek is driven with a greater (hive strength when nwe signaldriver circuite 7 lO are activated, and conversely, driven with lessor drive strength when fewer signal driver circuits 710 am activated, Thus, the drive streegStii toby be controlled by the SHFT signal, Changing thCdrive sirehgth of the signal driver circuits causes a timing of the output dock to change.

[054] lnoperation,eachof the driver circuits 710 are activated when the coirespondtogSHFT siptal indicates ^*1 ! ^* *, In embodiments Where the driver circuit 799 is included!» both the driver circuit 619 and driver circuit 029, one of the driver circuits operates according to the true SHFT signals, and the Other driver circuit operates according to the complement Of the SHFT signals. For example, when tbe 19 bits gre "999991 li l t” (as represented by the SHFT signals), the 1 st to Sth signal driver circuits are not activated and the 6th to 19& signal driver circuits are activated in the first driver circuit, while the 1st to :5th signal driver circuits are activated and the 6th to 10th signal driver circuits are not activated in the second driver circuit The drive strengths of toe driver circuits 619 and 620 are equal and the resulting DLLR clock becomes weighted as Odd: 59%, Evett 50%. When the 19 bits are“09001111 I I (as represented by the SHFT signals), six spud driver circuits are activated to one of tire driver circles and four signal driver circuits are activated in the oiherdriverckcutt- When the bits are all **!*, all the signal driver circuits to one of the driver ci rcuits are activated, and all the signal driver ci rcuits to the other driver circuit are not activated. The driver circuit 700 is shown as including 10 signal driver circuits. Other embodiments of die disclosure may include greater or fewer signal driver circuits, however,

[055] Figure 8 is schematic diagram of a shift register circuit 800 according to an embodiment of the disclosure, The sbift register ciit uit 800 may be included in the shi ft r^ster circuit 520 of Figure s m tome embodiments df the disclosure;

[056] The shift register circuit 800 includes shift registers 810(0>81O(9). The dull registers

810(0)-8i0(9) are coupled in series, and receive various control signals and clock. The shift registers 8lti(G)-810(9}receive control signals SRightand SRightF thatconiroi a shift direction for a shift register. That is, the SRight and SRightF signals cdtitrol from which node of die shift register data is received. For example, an active SRtghi signal (e¾ g,, high logic level) ad inactive SRightF signaKe g., low logic level) controls the shift register 810 to receive data piovided to input nodes QR or mQR of the shift register s 10 arid prov ide the data value to the output nodes Q (e.g., left Q node ami right Q node) responsive to drift clocks FSclkD and _: FSclkDF. An inactive SRight signal (e.g., low logic level) and inactive SRightF signal (e g., high logic- level) control the shift register 8 to to receive data provided to input nodes QL or tnQL nodes of the shift register 810 and provide lire data to die left Q node and tire right Q node responsive to the FSclkD and FSclkDF clocks. The FSclkD and FSclkDF clocks ate complementary.

[057] Selection of which input data (e.g., data received at the QR and QL nodes or data received at ft» mQR andtnQL nodes) to provide to the left and right Q nodes is controlled by control signal EnFineShiftF. For example, tm active BaFint^hiftF signal (e.g., low lope level) controls the shift registers 810(0)410(9) to provide the data from the respective QR and QL nodes, while an inactive EnFineShiftF signal (e.g., high logic level) controls the shift registers 810(0)410(9) to provide the data from the respective mQR and mQL nodes.

[658] A reset signal RstF is also provided to the shift registers 810(0)410(9). An active RstF signal (e.g., tow logic level) conirols the shift registers 810(0>810(9) to reset to a known data value that is based on input data value to the respective shift register ft 10(0)410(9),

The shift register 810(0) is provided at its QR sod mQR nodes an output from inverter circuit 802. The inverter circuit 862 hiw ah itiput coupled to a low logic teVril power supply, causing the inverter circuit 802 to provide a high logic level input to the drift register 810(0). The shift register 810(1) receives at its QR node the ouiput from the left Q: node of tire shift register 810(6); the shifl register 810(2) receives at its QR node die output ftom the left Q node of the shift register 810(1)· the shift register 816(5) receives at its QR node the oatputftom the left Q node of the shift register 81(1(2); end the shift register810(4) receives at its QR node the output ftom the left Q node of We shift; register 810(3). the left Q node of We shift; register 810(4) provides its output to the QR node of the shift register 810(5) and to the buffer 814. The shift register 810(0) receives at its QL node theoutput front the right Q node of the Shift register 810(1); the shift register 810(1) receives at its QL node the output from the ri|ht Q node of We Will register 810(2); the shift register 810(2) receives at its QL node the output from theright Q node of die shift roister gt0$k and the shift register 810(3) receives pi its QLnodetbe outputfrom We right Q node of the shift register 8) 0(4). The shift register 810(4) receives at ilsQL node theoutput from the right Q node of theshift register 810(5). Ihe output from Wetight Q tiode of We shift register 810(5) is also provided to themQLnodes of die shift registers 81<XO)~8iO(4) by wayof buffer 812.

[060] The shift register 810(9) is provided al its QL and mQL nodes ah output from inverter circuit 804. The inverter ci rcuit 804 has an iitppl coupled to a high logic level power supply, causing the inverter circuit 804 to provide a low logic level input to ft® shift register 810(0). The shift register 810(8) receives at its QL node We output from the right Q node of the shi ft register 810(9); the shift register 810(7) receives at its QL node We output from the right Q node of the shift register 810(8); the shift register s 10(6) receives at its QL node We output from We right Q node pfWe shift regi$ter8ia(7); and the $hift regi$ter 810(5) receives at its QL node ft® output from ft® right Q node of We shift register 810(6). The right Q node ofthe shift register 810(5) provides its output to ft® QL node of ft® shift register 810(4) and to the buffer 8t2, as previously described. Additionally, the shift register 810(9) receives at its QR node We output from the left Q node of the shift register 810(8); the shift register 810(8) receives at its QR node We output from the left Q node of the shift noisier 810(7); the Shift register 810(7) receives ai its QR node ¾ Output from the left Q node of the shift register 810(6); and the shift register 810(6) receives at ire QR node the output from We left Q node of the shift register 810(5). The shift register 810(5) receives at its QR node We output from We left Q node of the drift register 810(4), The output from the left Q node of We shift register 810(4) is also provided to the mQR. nodes of the shift registers 8 t0(5>810(9) by way of We buffer814.

[061] Each of We Shift registers 81O(0)-81O(9) further provides an output from its respective right Q code to a respective register 820(0)4120(9). The outputs from the right Q nodes are stored by the respective register 820(0)-8¾K¾ which each provides a respective control signal SHFT(0)-SHFT(9). The SHFT(0)-SHFT(9) signals may be included in a control signal SHFT. In some embodiments of 0» disclosure, toe SHFT(0)~SHFTi9) signals are included in a SHFT signd tommay be providNx$, ¾examp|e/to aphase mixer to control weightihgof input clod» (e.g„ O dock and E clock) in providing an output clock DLXJL

[062] The buffers 812 and 814 ate shewn id Figure 8 an including series coupled inverter circuits. However, buffers including alternative or additional circuits may be used as well in otherembodtments of the disclosure.

[063] As will be described in grottier detail below, the shift register circuit 8# may be controlled to shift data one register at a time to the left (e.g., toward shift register 810(9)) or to the right (&g., toWato toift register 81(1(0})- The data values are changed by individual shift registers. The shift register circuit 800 may also be controlled tb shift data to mote than one register at a time to toe left or to the right. The data Values are changed by a group of shift registers. The shift register circuit 800 has toe shift register Mages 81O(0)*810(9) divided into tyro groups of shift registers to provide shifting of data to toe left or right lor two different groups of shift registers. The two groups of shift registers of toe shift register circuit 800 are: (j) shift registers 8IO(O)~810(4) and (2) shift tegisters 810(5)-8I0(9)- Control of toe shift operation ibr one registeror multiple registers at a tone is provided by the EnFmeShiftF signaL Operation of the shift master circuit 800 accredit to various embodiments of toe disclosure will be described below with reference to Figures iOA-lOD.

[064] Figure 9 to a schematic diagram of a shift register 900 according to m embodiment of the disclosure. The shifiregtster 900 may be included in one or more of toe shift registers 810 of Figure 8 in some embodiments of toe disclosure.

[065] The shift register 960 includes a shift stage 910, and multiplexer emmite 920 and 930.

The shift Stage 910 Includes inverter circuits 912 and 916, and NOR logic gate 914. The shift Stage 910 further includes clocked inverter circuits 9Q2> 904, and 906, and NAND logic gate 908, each of which is provided shift docks FSclkD and FSdkDF. The FSclkD and FSclkDF clockare complementary. When activated, the docked inverter circuits 902,904, and 906, and NANb logic gate 908 are activated to provide an output that ½ toe complement of an input. The clocked reverter circuit 902 and NAND logic gate 908 are activated when toe FSclkD clock changes to a low dock level (mid: toe FSclkDF elock chaages to a high clock level), and the docked inverter circuits 904 and 906 are activated when the FSclkD clock changes to a high dock level (and toe FSclkDF clock changes to a high dock level).

[066] The inverter circuit 912 and toe docked NAND logic gate 908 are provided a reset signal RstF. An active R$fF signal (e.g., low logic level) is used to reset the shift regisier 900 to a known data value. An inactive RstF signal (e.g., high logic level) provides normal operation of the shiftregister §00, When the RstF signal is inactive, the NOR logic gale §14 effectively operates as an inverter circuit forthe oatputofthe clocked inverter circuit 902, and the clocked N AND logic gate 908 operates 4s a docked inverter circuit. As a result, when the RstF signal P roactive, the clocked inverter circuit 904 and the NOR logic gate 914 operate as a first clocked latch circuit, and the clocked NAND logic gate 90S and die inverter circuit 916 operate as a second clock latch circuit.

[067] 1» operation, assuming the RstF signal is inactive, a data value at the kaput of die clocked inverter 902 is provided as a complement to the first clocked latch when the FSclkD dockehanges to a low dock level (and the FScIkBF clock changes tie a high dock level). The complement Of the original data value is latched by the first clocked latch when the FSclkD clock changes to a high clock level (and the FSclkDF clock changes to a low clock level). The original data value is provided by ihe NOR logic gato§l4 to the clocked inverter circuit $0$, which also activated by the high clock level FSclkD clock. The activated clocked inverter circuit 906 provides the complement of the original data value to the second docked latch. The second clocked latch latches the complementary data value when FSclkD clock changes to a low clock level again, and the inverter circuit 916 provides die original data value to a Q node as an output of the shifi register 900, Insummary, the shift Stage 91® hitches a data value d its input on a Ming dock edge of the FSclkD dock, and shifts the data va!ue through the shift stage 910 to be provided a its Q node on a next falling dock edge of the FSclkD clock. The shift stage 910 is shown in Figure 9 as a ^<s reaet* iype flip Hop as the shill stage 910. Thus, the shift stage 910 sets“0” at the node Q when the shift stage 910 receives the active reset signal RstF. The shift stage 910 may also be modified to a“set” type (lip flop so that the shift Stage 910 sets“G at the node Q when the shift stage 910 receives the active reset signal RstF. For example, the NOR logic gate 914 may he replaced with a NAND logic gate, and the docked NANO logic gate 90S may be replaced witit a clocked NOR logic pte to modify the shift stage 910 to operate as a set type flip flop, in another example, inverter circuits may be iucluded at the input andoutput of the shift stage 910 to provide a set type flip flop.

[068] The multiplexercircuit 920 tndudes multtplexers 922 and 924. The multiplexer 922 is provided data flora the inQL and QL nodes and the multiplexer 924 is provided data from the nsQR and QR nodes. The multiplexer circuit 920isrontrotied by a control signal EnFineShtftF to provide as an output flie data from either the QL and QR nodes, or from themQLand mQR nodes. For example, the multiplexer circuit 920 provides data from the QL and QR nodes when the EnFineShiftF signal is active (e g., low logic level) and provides data from the mQL and mQR nodes when the Enf¾e§fe|ftF signal is inactive (e.g., high logic level), the multiplexer circuit 930 is: provided the outputs from die multiplexer 922 (data from dither the niQL or QL nodes) and from the multiplexer 924 (data from either the mQR Or QR nodes). The multiplexer circuit 930 is continued by Ctmtrol tignals SR*$ft and SRightF to provideas an outputtltedafa from either the multiplexer 922 or the multiplexer 924.

[069] In operation, the multiplexer circuit 920 is controlled by the EnFineShiftF signal to provide an output selected from either the data provided to the QL and QR nodes or the data provided to the mQL and mQR nodes, and the multiplexer 930 is controlled by the SRight and SRightF signals to provide to die shift stage 910 an Output selected from either the data provided to ode Of the left input nodes or the data provided to one Of the right input nddes. By tismg mt JbTir me¾tiiitr signal and m& SRigtit and bRigutr signals, data provided tp otie ot ttie inputs QL, QR, mQL, car mQR» is provided to the shift stage 91 O for latching and shifting,

[078] Operation of the shift register circuit 800 according to an embodiment of the disclosure will be described with reference to Figures 10A-40D. As previously described, toe shift register circuit 800 may be controlled to shift data to more than one register at a time to tire left or to the right The data values are changed by a group of shift registers. Tito EnFineShiftF signal is a high logic level to control the Shift register circuit 800 to operate tit this manner. Figures 10A-10D illustrate operation in tilts manner tor toe shift register circuit 800 according to various embodiments of the disclosure

[071] Figure 10A shows a condition of the shift register circuit 800 following a reset by an active RstF signal. The RstF signal is strobed to a low logic level which causes die Shift registers 810(0>8l0(9) to reset to a known data value. When the RstF signal returns to a high logic level, initial data virtues are stored by toe shift regi$ters 810(0^810(9) as shbwb in Figure 10A. For example, the shift registers 8!0(0>810(4) are reset sad store high jtogic data value (e.g.," ") (e.g _> , shift registers 819(0)~810(4) include a shift stoge configured as a set type flip ftopX and the shift registers 810(5)410$) «re reset and store low logic data value (e.g., *¾F) <e.g,. shift registers R10(5)~810(9) include a shift stage configured as a reset type flip flop).

[072] Thus, as shown by Figure 10A, fotlowiag reset of the shift register circuit 800 by aft active RstF signal, the shift registers 8!O(0)-8iO(4) are set to a“F and toe shift registers 81$5)410ί9) are set of * The corresponding SRFT signal provided by the registers 82<KO>420(9) includes S«FT(<)^SHFT(4) as and SHFT(5>.$HFT(9)as“0’\ [073] In embodiments of Ole disclosure where the SHFT(0)-SHFr(9) signals are provided to a phase mixer circuit (&&, phase mixer circuit s 10 of Figure 5), following reset of the drift register circuit 800, clocks provided to the phase mixer circuit (e g., O clock and E clock) are equally weighted and theresuUingDLLR ctock has a Sad delay ofone-half(50%)of the total range of fmedelay provided by die phase mixer circuit.

[074] Figure 10B shows a condition of the shift register circuit 800 when controlled to shift data to mote than one register at a time to the left (e.g., toward the shift register 810(9)) following the shift registers 810(0>810(4) storing a ^** !* data vtihte and the shift registers 8l(K$)-810(9) storing a“0” date value (e.g,, condition shown in Figure 10A); The EnFineShiftF i$ at a high logic level, and consequently, data input from ihe mQR nodes are latdtod by the shift rcgfetote 81O(ti)-810(4) arid data input from the mQL nodes are latched by the shift registers 810(5>810(9). The shift registers 8ltii(5) 8i0(9) are controlled by die S Right andSRightF signals to output at the respecii ve Q nodes the data at the mQR nodes. As a result, tire^P date value stored by the shift register 810(4) mid provided through the buffer 814 to toe mQR nodes oftheshift tegisters 8 I0(5>81<¾(9) is latched to setali ofthe shift registers 8id(5>- 810(9) to store“Pdate. TiaPP data value latched by the shift toasters 8MK5>810<9) causes the corresponding SHFT(5)hSHFT(9) signals to changeto“ P, Which results in the shift tester circuit 800 primdhig SHFT(0^SHFT(9) signals that am all“Pi

[075] In embodiments of the disclosure where the SHFT(0)-SHFT(9) signals are provided to a phase mixer circuit, one ofthe clocks provided to the phase mixer circuit has full weightand the other clock has no weight (e.g., O clock has Ml weight (I00%) and E clockhas no weight (0¾)), and the resulting DLLR clock has a timing that is based on the fully weighted dock (e.g., based on the tinting of the O dock and not the E clock).

[075] Figure IOC shows a condition dfftie shift register Circuit 800 when controlled to shift data to more than one register at a time to the right (e,g., toward the shift register 810(0)) following all of the shift registers 810(0)-8l0(9) storing *P date (e.g,, condition shown in Figure iOB). The EnFineShiftF is at the high logic level so that the mQR and mQL nodes are input to the shift registers 81(KO>-810(9). The shift registers 810(5)4110(9) are controlled by the SRigfat and SRightF signals to outpttt at the reflective Q nodes the data at the mQL nodes» As a resulf the“0* data value provided by the tnyetier 804 and provided to the mQL itodes of the shift register 8!0(5f8lp<9> is latohed tp set all of the shift register 8T0(5>8i9(9) to store < ⁴ 0 ^rt date. The“0* data value latched by tire shift registers 8l0(5)-8iti(9) causes the corresponding $HFT(5)HSHFT(9) signals to change to KT, which results in the shift register circuit 800 providing SHFT(0>SHFT(4) as“G and SHFT(5>SHFT(0) as ^<, (r ,

As previously described, in embodiments of the disclosure where the SHFT<0> $HFT(9) signals are provided to a phase mixer ctseui t, providing a SHFT sign*! including SHFT(0)-SHFT(9) signals having hairT’and the other half“0”causesthe phase mixer circuit to equally weight the input clocks (e.g., O clock and E clock), resulting in a DLLR clock having a fine delay of one-half (50%) of the total range of fine delay provided try toe phase mixer circuit.

[078] Figure lOD sbows a condition of the shift register circuit 800 when controlled to shift data to more than one register m a tune to the right (eigi, toward the shift register 810(0)) fbllowingtheshift registers 810(0)-8I0<4)Storing" " dataand the shift registers 810(5)410(9) storing *" data (e.g., conditions shown in Figures 10A and IOC). The EoFineShtftF is at the high logic level so that the mQR and mQL nodes are input to the shift registers 810(0)411(0% The shift registers 810(0)410(4) are controlled by the SRight and SRightf signals to output at the respective Q nodes toe data at the mQL nodes. As a result, the ^* 1)” data value stored by the shift register 810(5>and provided through the buffer 812 to the mQL nodes of theshift registers 810(0)410(4) is latched to set all of toe shi ft registers 8I0(b>-810(4) to store“0” data. The ‘XTdata value latched by toeshift registers 810(0)410(4} cause$ theconesptouting SHFT(0> SHFTX4) signals to change to“0” which results in toe shift register circuit 800 providing $HFT(0)-SHFT(9) signals thatare aM”.

[079] In embodiments of the disclosure where toe SHFT(0)-SHFT(9) signals are provided to the phase mixer circuit, one of toe docks provided to toe phase mixer circuit has no weight and the other dock has full weight (e.g., G dock has no weight (0%) aud E clock has toll weight (100%)), and iheresultittg DLLE clock has a tirnuig toat is based on the fully weighted clock (e.g., based on toe tinting of the E clock and not toe O clock).

| As illustrated by the examples of Figures lOA-100, toe shift register circutt 800 may be controlled to daft data to more than one register at a time to the left or to the right. In the particular examples, data is drifted between two groups of shift registers 810(O)-810(9) at a time. The data values are cbanged by a groap of sWft registers. As previously described, toe shift register stages 810(0)410(9) are divided into two groups of shift registers to provide toifting of data io tbe left or right to two different groups of shift registers: (!) shift registers 810(0)410(4); and (2) shift registers 810(5)410(5). In this manner, a jfme delay provided by a fine phase adjust circuit may be quickly adjusted to provide one of three different fine delays, rather than limited to being incrementally adjusted by one shift register 819 st a time, hi the example of shift register cirmt ftdO, the ftne delay may he quickly adjusted between (1) 59% weight for first and second clocks; (2) 190% for die first clock and 9% for th» second clock; and (3) 9% for the first clock and 199% for the second dock. Quickly adjusting a fine delay may provide faster locking of a clock generator circuit during initialisation compared to incremental fine delay adjustment

[081] Operation of the shift register circuit 899 according to ^ embodiment of thedisdosure will be described with reference to Figure 11. As previously described. the shift register circuit 899 may be Controlled to shift data to One register ata time to the left (e;g^ to ward shift register 819(9» or to the right (e.g _*v toward shtft register 819(0». The data values are changed by individual shift registers, The EnFineShiftF signal is a Itoy logic level to control the shift register cirtiait SOO to operate m this manner. Figure 11 illustrates an example operation to this manner for the shiftregister circuit 899 according to an embodiment of the disclosure.

[082] Figure 11 shows a condition of die shift register circuit 899 when controlled to drift data to one register at* tone to the left (e.g„ toward the shift renter 819(9» fol!owing the shift tegisters 819(9j 819#) storing data and the shift registers 819($>810(9) storing *TT data. The EnFineShiftF is at a low logic level so that tile QR and QL nodes are input to foe shift togisters 810(0)-819(9). In Figure i t , foe shift register 810(5) is contmlled by the SRi^t and SRightF sisals to output at the respective Q nodes foe data at foe QR node. As a result, the ^e t" ^! data value stored by the shift register 819(4) and provided from the left Q node to the QR node ofthe shift register 810(5) ¾s latched to set tbe shift raster 819|5) to store“l* data. The ^* T ^* data value latched by the shift register 819(5) causes the corresponding SHFT(5) signal to change to“1 ", which resu!tsin the thrift register cirowt 809 providing SHFT(9)-SHFT(5) as told SHFT(6>SHFT(9> as : ^« V.

[983] to embodiments of foe disclosure where the SHFT(0>SHFr<9) signals are provided to a phase mixer circuit, providing a SHFT signat including $HFT(0)*$HFT{S) signals having *1 * and $fiFT(6)-SHFT(9) Mvtog ^ mses the ffoase mixer circuit to weight a first clock 69% and weight a second dock 40% (e.g„ O clock weighted 60% and foe E clock 4ti%) to provide a DLLR dock having a ftne delay based more on foe timing of the first clock, m particular, 40% ofthe total range of fine delay provided by the phase mixer circuit relative to foe first dock (e.g., timing closer to the first clock: than foe second dock). Additional incremental shifting ef data one shift register at a time to foe left or right may be performed as previously described by having the EnFineShiftF signal at a low logic level and using the SRight and SRightF signals to control shift direction (e,g„ control which of the nodes at which data is applied to use for providi¼ an outpnt).

As itiustraied by Figure 11, the shiftregister circmt &OOmaybe alsoconlrolled to shift data dhe register at a time to die left dir to the right to incrementally Change the SHFT(0)- SHFT(9) signals- The data values are changed by individual shift registers. The incremental changes provide a minimum delay adjustment In the shift register circuit 800, which has 10 Shift registers lo provide 10 individual control signals, shifting the data by one shift register at _: a time tb die left car right causes a change in the fine delay in increments of ! ø% of the total tan^offinedelay. That is# the delay may beadjusted by aminimum of 10% of the total range of fine delay. By providing * shift register circuit that can shift data one shiftregisterai a time (e g., previously described with reference to Finite 11% and also shift data to more than one register at a tune (e.g., previously described with reference to Figures lOA-lQD), die fine delay provided by the fine phase adjust circuit may lie adjusted incrementally, such as during normaj operatic» following initialization, as well as being adjusted quickly, such as during initialisation ofa clock genemtorcirctiit

[085] Figure 12 is a schematic diagram of a shift register circuit 1200 according to aft embodiment of the disclosure. The shift register circuit 1200 may be included in the shift register circuit 320 of Figure 5 in some embodiments of &e disclosure;

[086] The shift register circuit 1200 includes shift registers 12IQ(0) 1210(9). the shift registers 121O(QH2I0(9) arecoupled in series,andreceive various cpntrol signalsand clocks; The shift registers 121O(0>1210(9) receive control signals SRight and SRightF that control from which node of the shift register data is received. For example, an active SRight signal (e.g., high logic level) and inactive SRightF signal control the shift register 1210 to receive data provided to input nodes QR ormQR of die shift register 1210 and provide the data to the output nodes Q (e.g,, left Q node and right Q node) responsive to shift clocks FSclkD and FScikDF. An inactive SRight signal (e.g., low logic level) and active SRightF signal control the shift register 1210 to receive data provided to input nodes QL or mQL nodes of the shift register 1210 and provide the data to the left Q node mid the right Q node responsive to the FSclkD and FScikDF clocks; The FSclkD and FSclkDF clocks are complementary.

[087] Selection of which input data (e.g., data recei ved at the QR and QL nodes or data received at the mQR and mQL nodes) to provide to die tell and right Q nodes is control ledby control signal EnFmeShiftF, For example, an active EnFineShiftF signal (e,g , low logic ievet) controlsthe shift registers 121 ø(ø}· 1210(9) to provide the data from the respective QR and QL nodes, while an inactive EnFmeShiftF signal (e.g., high logic level) controls the shift registers 1210(0)4210(9) to provide the data from the respecti ve mQR and mQL nodes.

[088] A reset signal RstF is also provided to the shift registers 1210(0)4210(9). An active RstF signal (eg., low logic level) controls the Shift Jesters 1210(0)4210(9) to reset to a known data value that is based on input data to the respective shift register 1210(0)4210(9).

The shift register 1210(0) is provided at its QR and mQRnodes an output from inverter circuit 1292. The inverter circuit 1202 has an input coupled to a low logic level power supply, causing the inverter circuit 1202 to provide a high logic level input to the QR node of the shi ft register 1210fp> and to themQR nodes of the Shift registers 1210(0) and 1210(1). The shift register 1210(1) receives at its QR node the output from die left Q node Of die shift register 121O(0); the shift register 1210(2) receives at its QR node die output from the left Q node Of the shift register 1210(1 ); the shift register 1210(3) receives at its QR node the output from the left Q node of the shift register I210(2); and ihe shift register 1210(4) receives at its QR node die output from the left Q node of theshift register 1210(3). The left Qnodeof the shift register 1210(4) providesits Output to titeQR node of the shift register 1210(5) and to the buffer 1214, The output fromtheMQnode of theshift register 1210(1) is also provided through the buffer 1211 to the mQR nodes of the shtft registers 1210(2)4210(4).

[090] Additionally, die shift register 1210(0) receives at its QL node die outpMfromihe right Q node of the shift raster 1210(1 ); the shift register 1210(1) receives atiisQLnode die output from the right Q node ofthe shift register l2 IO(2); the shift register 1210(2) receives at its QL node the output from the right Qnodeof the shift register 121q(3)ί and theshift register 1210(3) receives at its QL node the output from the right Q node of the shift register 1210(4). The output of the right Q node of the shift register 1210(2) is also provided to the mQL nodes of theshift registers 1210(1) and 1240<0)through buffer 1213. The shift register 1210(4) receives at its QL node the output from the right Q node of the shift register 12 $0(5). The output from the right Q node of the shift register 1210(5) is al so provided to the mQL nodes ofthe shift registers 12lO(2>12lW)½ way of buft¾r 1212.

[091] The shift register 1210(9) is provided at its QL and mQL nodes an output from inverter circuit 1204. The invertercircuit I204 has att input coupled to a high logic level power supply, causing the inverter circuit 1204 toprovide a low logic level input to the shift register 1210(9) and to the mQL nodes of the shift restore $210(9) and 1210(8). The shift register 1210(8) receives at its QL node the output fram the right Q node ofthe shift register 1210(9); the shift register 1210(7) receives at its QL node tbe output from the right Q node ofthe shift register $ 210(8); the shift register 1210(6) receives at its QL node the output from the right Q «ode of the shift register 1210(7); and the shift regisier l¾K)(5) receives at its QL node theoutput from the right Q node of toeshift register 1210(6) Theoutput of the rigfrtQ node ofthe shift raster 1210(8) is also provided totiiemQL nddesofsbift registefs I210(5)-1210(7) by way of buffer

1215.

[092] Additionally, the shift tester 1210(9) receives at its QR node the output from the left Q nodeof the shift register 1210(8);the shift register 1210(8) recei ves at its QR nodeihe output from the left Q node of the shift register 1210(7); the shift register 1210(7) receives at its QR node the Output from the left Q node of the shift register 1210(6); and the sliift register 1210(6) receives at its QR node the Output from die toft Q node of die shift register 1210(5) The shift roister 1210(5} receives at its QR node the output from die 16ft Q node of the shift register 1210(4). The output from the left Q node of the shift register 1210(4) is also provided to die mQR nodes of die shifti¾gislers l2lO(5)rl 2i(M7) by way of die buffer 1214, The output from die left Q node of toe shift register 1210(7) is also provided to the mQR nodes of the shift registers l210(8) and 1210(9) through buffer 1216,

[093] Each of the shift registers 121O(0H210(9) further provides an output from its respective righlQ node to a respectiveregister 1220(0> t220(9). the distils from tiie right Q nodes are stored by the resp«itive register 122<¾0)-1220(9), which eaeh provides a respective control signal SHFT(0)-SHFT(9). The SHFf (0)-SHFT(9) signals may be included in a control signal SHFT. In some embodiments of the disclosure, the StiPT(0>SHFT(9) signals are included in a StiFT signal dial msy be provided, for example, to a phase mixer to control weighting of input clocks (e&, O clock and E clock) in providing an output clock DLLR.

[094] The buffers 1211-1216 are shown in Figure 12 as including Series coupled inverter circuits. However, boilers including aliemative or additidnal cireuits may be died as well in other embodiments of the disclosure.

[095] As will be described in greater detail below, the sbift registor circuit 1200 may be controlled to shift data to more than one register at a time to the left <e.g,, toward riuft raster 1210(9» or to Outright (e,g., toward shift register 1210(0)). The data values are changed by a group of shift registers. The toift regisier circuit 1200 may a1so be controlled to shift data one register at a time to the left or to the right The data values are changed by individual shift registers, in contrast to toe shift register circuit 800 ofFigure & toe shift register drcuit 1200 has the shift register stages 1210(0)· 1210(9) divided into four groins of shift registers to provide shifting of data to the left or right for four different groups of skiff registers, instead of two different groups ofshift registers as for the shift registercircuit 880 of Figured, The four groups of shift registers of the shift register circuit 1200 ere: (1) shift registers 1210(0) and 1210(1); (2) shift registers 1210(2)4210(4); (3) shift registers 1210(5>1210(7k and (4) shift listers 1210(8) arid 1210(9), Control of the shift operation fof one register or multiple registers at a time is provided t# the EnFineShiftF signal.

[096] Operationofthe shift register eimiit 1200 according to an embodiment of the disclosure will he described with reference to Figures 13A43G, As previously described, tire shift register Circuit 1206 may be controlled to shift data to more than one register at a time to die left or to the right Thedaia values are changed byagroup of shrft registers l½ EnFmeShiftF signal is a high logic level to control the shift register drcatl lZOO to operate in this manner. Figures 13A-13G illustrate operation in this manner for die Shift registercircuit 1200 according to various embodiments of the disclosure.

[097] Figure 13A shows a condition of the shift noisier circuit 1200 following a reset by an active RstF signal. The RstF signal is strobed to a tow logic level which causes the shift registers 1210(0)- 1210(9) to reset to a known data value. When toe RstF signal returns to a high logic level, initial data values are stored by toe Shift registers 1210(0)- 1210(9) as shown in Figure 13A. For example, toe shift registers 1210(0)4210(4) are reset and store high logic data value (feg,,“P (4 g , shift registers 1210(0)4210(4) includes shift stage configured as a set type flip flop), and the shift registers 1210(5)4210(9) are res set and store tow logic data value (e:g.,“0*) (e _> g. _y shift registers 1210(5)4210(9) include a shift stage configured as a reset type flip Sep),

[098] Has, as shown by Figure 13A, following reset of the shift register circuit 1200 by an active RsE signal, the Shift registers 1210(0)4210(4) are set to a“1” and the shi ft regiSters 1210(5)4210(9) ate set of a“O” The Cones$x>ndmg SHFT signal provided by die registers 1220(0)4220(9) includes SHFT(0>SHFT(4) as“I” and SHFT(5>-SHFT(9) as‘1G.

[099] In embodiments of the disclosure where the SHFT(0)-SHFT(9) signals are provided to a phase mixer circuit <e _* g„ phase mixer circuit 510 of Figure 5), following reset of the shift register circuit 1200, clocks provided to the phase mixer circuit (e g., O clock and E dock) are equally weighted and the resulting DLLR ctock has a fine delay of one-half (50%) of toe total range of fine delay provided by the phase mixer circuit

[0100] Figure BB shows a condition of the Shift register circuit 1200 when controlled to shift data to more dm one roister at a time to the left (e g., toward the shift register 1210(9)) foltowing toe shift registers 1210(0)4210(4> storing“G data and the shift registers 1210(5> 1210(9) storing *XT data (e.g., condition shown in Figure 13A). The EnFineSbiftF is at a high logic level, and consequently. data input ftom themQRnodes are Mched by the shiftregisters 12 tO(0>12HK4) and dai&iaput from the mQL nodes are latched by the shift registers 1210(5). 1210(9), The Shift registers 12I0(5}-1210(7) are cohtrolled by die SRight and SRightF signals to Output at the respecti ve Q nodes the data at the mQR nodes. As a result* the‘Ί” data value stored by the shiftregtsler 1210(4) and provided through the buffer 1214 to the mQR nodes of the shift registers 1210(5)-12t0(7) is htched to set all ofthe shift registers 1210(5>t21d(7) to store ^* T ^* data. The shift registers 1210(8) aid 1210(9) continue to store‘TG data, however. The data value latched by the shift registers 1210(5) 1210(7) causes the corresponding SHFT(5).SHFr(7) Signals to change to“l”, which results in the shift register circuit 1200 providing SHFT(0)-SHFT(7> signals that are“l” and SHFT<¾) and SHFT(9) signals that ate

"0".

[0101] In embodiments of the disdosure where the SHFT(0>-SHFT(9) signals areprovided to a phase mixer circuit, one of the clocks provided to die phase mixer circuit has approximately 4/5 weight and the other clock has approximately 1/5 weight (e g,, 0 clock has 80% weight and E elock has 20% weight), the reselling DLLR ciock has a tinting that is based on a 80% and 20% weighting (e.g., based mostly on thetiming ofthe O dock).

[0162] Figure 13C shows a cdndilion of the shift register circuit 1200 When controlled to shift data to more than one register at a time to the lefifoUowingthe shift registers 1210(0>1210(7) storing *1 ⁿ - data and the shift registers 1210(8) and 1210(9) storing ^ data (e g,, condition shown in Figure 13B). The EnFineShiftF is at the high togk level so that the mQR and mQL nodes «eh|M to idie shift registers I210(0).1210(9). Tfc» shift registers 1210(8) and 1210(9) are controlled by the SRight and SRightF signals to output at the respective Q nodes the data at the mQR nodes: As a result, die“G date value stored by ftie shift register 1219(7) and provided through the buffer I2l6 to the mQR nodes of the shift registers 1210(8) and 1210(9) ¼ latched to set the shift registers l2lQ(8) and 1210(9) to store ^w r data. The‘T* ^> data value latched by the shift registers 1210(8) and 1210(9) causes the corresponding SHFT(8) and SRF1X9) signals to change to‘T\ which results in the shift register circuit 1200 providing SHFT(0)-SHFT(9)stgttaIs that are a!l“I”.

[0103] inembodiments ofthe disclosure where the SHFT(0)-SHFT(9) signals are provided to a phase mix®: circuit, oneof the ciocks provided to the phase mtxer circuit has fiill weight and the other clock has no weight (e.g., O clock has full weight (100%) and E dock has no weight (<)%}), and the resulting DLLR clock has a timing that & based on the fully weighted clock (e.g., based on the timmg offoe O clock and not the B dock) _*

[0164] Figure 13D shows a condition of the shift re^ster circuit 1200 w¾eneonirolled to shift data to more than one register at a time to the right (e _> g„ toward the Sift register 1210(0)) following all of foe shift registers 120(0M21b(9) storing“G data (e g., condition shown in Figure 13G). T¼ EnFineShiftF is at the high lope level so foatfoe mQR and inQL nodes are input to the shift registers 1210(<>)-1210(9). The shift registm 1210(8) and 1210(9) are controlled by foe SRight and SRi ghtF srgnals tooutput at the respective Q nodes foe data at foe mQL nodes. As a result, the“0” data value provided by the inverter 1204 andprovided to foe mQLnodes of the sh.li registers 1210(8)and 1210(9) is latched toset theshifttegisters 1210(B) and 1210(9) to store“0” data. The ^M 0” data value latched by the shift registers 1210(8) and 1210(9) causes foe corresponding $HFT(8) and SHFT(9) signals to change to“0”, which results in the shift register circuit Ϊ200 providing SHFT(0)-SHFT(7) as ^« I ^H and S»FT(8) and SHFT(9) as *0 ^w .

[0105] As previously described, in embodiments of foe disclosure where the SHFT(0>- SHFT(9) signals are provided to a phase mixer circuit, oneof foe clocks provided to foe phase mixer circuit has approximately 4/S weightand foe Other dock has approximately 1/5 weight (e g., 0 dock has 80% weight add E cl0ck has20% weight _* The resulting DLLR clock has a timing that is based cm a 80% and 20% weighlingfe.g. , based mostly on the timing ofthe O dock).

[0106] Figure 13E shows a condition of the shill registercircuit 1200 when controlled to shift data to morethan one register ata time to foe right following foe shift registers 1210(0)-1210(7) storing”!” data and foe shift registers 1210(B) and 1210(9) storing“0” data (e.g,, conditions shown fo Figures 13» arid 13D), The EnFineShiftF is at foe high logic level so that the mQR and mQL nodes are input to the shift tegisters 12MM0>12i0(9). The shift registers 1210(5)- 1210(7) are controlled by the SRight and SRightF signals to output ai foe respective Q nodes the data at foe mQL nodes. As a result, the”0* data value stored by the shift register 1210(8) aridprovided through the buffer 1215 to the mQL nodes of foe shift registers l2iti(5H210(7) is latched to Set foe shiftregistors 1210(5;)-1210(7)tostore‘ ^,i( r data. The ^* *0" data value latched by the shift rasters I210(5>*1210(7) causes the corresponding SHFT(5)-SHFT(7) signals to Change to *W, which results m the shift regisier circuit 1200 providing SBFT(0>SHFT(4) as "t* and SHFT(5)-$HFT(9) as“0”. [0107] As previously described, in embodiments of the disclosure where the SHFT(0)- SHFT(9) signals are provided to a phase mixer circuit* providing a SHFT signal including SHinr(0)-SHFT{9) signals having half ⁴ T' and the other half‘"0" causes the phase mixer circuit to equally weightihe inputclocks (e,g,, O clbckandE clock)* resulting in a DLLR clock having a fine dday of one-half (50%) of the total mnge of fine delay provided by the phase mixer circuit

[0108] Figure 13F shows a condi tion of the shift register circuit 1200 when controlled to shift date to more than one register at a time to the right (e.g., toward the shift register 1210(0)) following Ihe shift tegisters 121O(O)-1210(4) stojr»¾“P data and the shift registers 1210(5)- 12 mm storing ^” detta (e.g., conditions shown in Figures ISA and 13E). The EnFateSMftF b at the high logic level so thalthemQR and niQLnodes ateinput to the shift registers 1210(0)- 1210(9). The shiftiegisters 1210(2)- 1210(4) are controlled by the SRight andSRightF signals lootriput at die respective Q nodes the date at the mQL nodes. As a result the ^tT data value stored by the shift register 1210(5) and provided through the buffer 1212 to die mQL nodes of the shift regbters 1210(2)-12I0(4) is latcbed to set the sbift registers 1210(2)-1210(4) to store "0” data. The“0” data value latched by the shift registers 1210(2>12HK4) causes the corresponding SHFT(2)-SHFT(4) signals 10 change td‘‘ft” which results in the shift register circuit 1200 providing $HFT(0) and SHFT(l) as ^* ‘r ^v and$HFT(2)-SHFT(9) as“0’V

[0109] In embodiments of the disclosure where the SHFT(0)-SHFT(9) signals are provided to a phase mixer circuit, one of the clocks provided to the phase mixer circuit has approxnnately 1/5 weight and the other clock has approximately 4/5. weight (e.g,, Q clock has 20% weight and E clock has 86% weight. The resulting DLLR dock has a timing that is based on a 20% and 80% weighting (e.g,, based mostly on the timing of the E clock).

[0110] Figure 13G shdWs a conditidti of (he shift register dicuit 1260 when controlled to shift date to more than one register at a time to the right following the shift registers 1210(0) and 1210(1) storing“T‘ data mid the shift registers |210(2jM2lO(0) storing“0* data (e-g,, condtuons shown in Figure 13F). The EnFineSMftF is at the high logic level so that the mQR ami mQL nodes are input to the shift registers 1210(0>l210(ft). The shift registers 1210(0) and 1210(1) are controlled by tite SRight and SRightF signals to output at the respective Q nodes the data at the mQL nodes. As a result, the“0” data value stored by the shift register 1210(2) and provided through the buffer 1213 to the mQL nodes of the shift registers 1210(0) and 1210(1) is latched to set the shiftregisiers 1210(0) and 1210(1) to store“0 ^** data, The“0” date value latched by 0» shift registers 1210(0) and 1210(1) causes the corresponding SHFT(0) and$HFT(l ) signalsto change to *0", which resists in the shift register circuit 1200 providing SH3FT(0)-SHFT(9) signals that aro a!l *»*

[0111] inembodiments of the disclosure where the SHFT<0>SHFT(9 ) sipi8ls are provided to a phase mixer cfrcufti one of the clocks provided to the phase titixer circuit has no weight end the other clock has full weight (e g., O dock has no weight (6%) aid E clock has full Weight (100%», and the lesdting D1LR clock has a timing that is based on the fatly weighted clock (e.g„ based on the timmg of the E clock and not the O clock).

[0112] Asiilustrated by the examples of Figures 13A*13G. the shift register circuit 1200 may be controlled toshifldata to more than one register at a time to the left orto the right 1¾e data values are changed by s group of shift registers. In the particular examples, data ½ shifted to groups of the shift registers 121<X0> 1210(9) at a lime. As pfevious!y described, die shift register stages 1210(0>1210(9) are dividedMp four groups of shift registers to provide shifting of data to toe left or right; to four Afferent groups of shift registers: (l) shift registers 1210(0) and 1210(1); (2) shift registers 12UX2H2KX4); (3) shift registers 12i0(5>1210(7); and (4) shift registers 1210(8) and 1210(9). tnthismmmer, afinedelayprovided bya ftnephaseadjttst circuit may be quickly adjusted to provide one of five different fine delays, rather than being incrementally adjusted by one shift register 1210 at a time, hi die example Of shift register circuft 1200, the fine delay may be Quickly adjusted between (;1) 50% Weight for first and second clocks; (2) 80% and 20% for the fust and second clocks; (3 j 100% for the first clock and 0% for the second clock; (4) 20% and 80% for the first and second clocks; and (5) 0% for the first clock and 100% for the second clock. Quickly adjusting a fine delay by non-sequertfial steps of fine delay may provide foster locking of a dock generator circuit during initialization compared to incremental fine delay adjustment The shift register circuit 1200 has the additional feature of &ci|iteiihg quick adjustment of the fine delay wtth greater procision compared to the shift register circuit 800-

[0113] As previously described, the shi ft register circuit 1200 may also be controlled also shift date to oneregistertea time to the left (e.g., toward shift register 1210(9)) or to theiighl(e.g., toward shift register 1210(0)). The data values are changed by individual shift registers. The EftFareShifiF sighal is a low logic level to eontrol the shiftregisier circuit 1200 to opera¾e hi this manner. Operation of the shift register circuit 1200 to shift date one register at a time to the left or right is similartooperation ^ previously described, with rcference to Figure f 1.

[0114] The shift register circuit 1200, which has 10 shift registers to provide l O individual control signals, lifting the date by one shift register at a time to the left or right causes a change in the fme detay in increments of 10% of the total range of fine delay. That is* the delay may be adjtisted by a minimum delay of 10% of the total range offine delay. By providing a shift register circuit that can shift data one shift register at a time (e.g,, previously described with reference to Figure ! IX and alsdshift data to more than one register ala time f eg., previously described With reference to Figures 13A-13GX the fine delay provided by the fine phase adjust circuit maybeadjusted incrementally, sachas during normal operation following initialization, as weft as being adjustod quickiy, such as during initialization of a clock generator circuit

[0115] From the foregoing it will be appreciated that although specific embodiments of the disclosure have been described herein for purposes of illustration,, vartousmodifications may be made without deviating from the spirit and scope of the disclosure. Accordingly, the scope of flte di selosure should hot be limited any of the specific embodimen ts described herein.