Title:
ARRAY SUBSTRATE, DISPLAY PANEL, AND METHOD OF TESTING ARRAY SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2023/000156
Kind Code:
A1
Abstract:
An array substrate includes N number of testing signal lines, N being an integer greater than 1;N number of first control signal lines; N number of second control signal lines; M number of first switching transistors; and M number of second switching transistors. A second electrode of a m-th first switching transistor is connected to a first electrode of a m-th second switching transistor, 1 ≤ m ≤ M. A n-th testing signal line is connected to first electrodes of (kN+n) -th first switching transistors, 1 ≤ n ≤ N, 0 ≤ k < M/N. A n-th first control signal line is connected to gate electrodes of (kN2 + ( (n-1) *N) + 1) -th to (kN2 + n*N) -th first switching transistors, 0 ≤ k < M/N. A n-th second control signal line is connected to gate electrodes of the (kN+n) -th second switching transistors. A second electrode of the m-th second switching transistor is connected to a m-th array substrate signal line.
Inventors:
LU HONGTING (CN)
FENG YUHSIUNG (CN)
FENG YUHSIUNG (CN)
Application Number:
PCT/CN2021/107271
Publication Date:
January 26, 2023
Filing Date:
July 20, 2021
Export Citation:
Assignee:
BOE TECHNOLOGY GROUP CO LTD (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
International Classes:
G02F1/1362; G09G3/00
Foreign References:
| CN112270908A | 2021-01-26 | |||
| CN107728395A | 2018-02-23 | |||
| CN105676497A | 2016-06-15 | |||
| JP2003029296A | 2003-01-29 | |||
| JP2008129374A | 2008-06-05 |
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