ASYNCHRONOUS LOGIC CIRCUIT, CONGESTION AVOIDING PATH CALCULATION MODULE, SEMICONDUCTOR CIRCUIT, AND PATH CALCULATION METHOD IN ASYNCHRONOUS LOGIC CIRCUIT

WIPO Patent Application WO/2010/150654

A1

An asynchronous branching module (102) outputs transfer data which has been input in accordance with a handshake protocol to any one of the branch destinations. An asynchronous arbitration module (101) merges transfer paths of the transfer data. A congestion detection module (111) receives an arbitration result signal from the asynchronous arbitration module (101), and outputs congestion information indicating the existence/nonexistence of congestion to a merge source. A congestion avoiding path calculation module (112) receives the congestion information, and exclusively performs a process to store the information in a congestion information storing memory, and a process to control the asynchronous branching module (102) to select a transfer branch destination from branch destinations capable of reaching the goal, on the basis of the congestion information and the goal information of the transfer data, so that the branch destination which does not have congestion information showing the existence of the congestion has priority in the selection.

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TANAKA KATSUNORI (JP)

PCT/JP2010/059768

December 29, 2010

June 09, 2010

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NEC CORP (JP)
TANAKA KATSUNORI (JP)

H04L69/14; G06F13/362; G06F13/38; H03K19/20

JP2000172661A	2000-06-23
JPH08161258A	1996-06-21
JPH05151147A	1993-06-18

KIMURA MITSURU (JP)
Mitsuru Kimura (JP)

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