TECHNICAL FIELD

The invention relates to a successive approximation register analog-to-digital converter.

BACKGROUND

The increasing use of on-chip smart elements such as machine learning tasks or closed-loop control necessitate a larger digital area and power overhead, leaving the analog front end circuitry with even more demanding constraints. Especially multichannel scenarios in applications ranging from biomedical diagnostic equipment to industrial sensor arrays seek the lowest energy and area per unit channel to increase integration density.

Successive approximation (SAR) is currently the most versatile and all-round efficient analog- to-digital converter (ADC) architecture. Fastest [1], smallest [2], lowest power [3], and most energy-efficient [4] ADCs to date are all based on SAR architecture. On top of that, asynchronous SAR ADCs offer additional benefits thanks to their operation time being independent from the sampling rate. First, they can output a sample each clock cycle, contrary to the synchronous SAR where (N+l) cycles are required for N-bit resolution. Second, they consume no dynamic power after finishing a conversion until the next one, so their average power consumption scales with the sampling rate.

The generic block diagram of an asynchronous differential SAR ADC is depicted in Figure 1. A track and hold (T/H) switch stores the differential input voltage (VIN) on the capacitive digital- to-analog converter (CD AC). The comparator resolves the voltage on the DAC (VDAC), which changes after each decision (dec) based on the successive approximation program realized by the logic block (dacp9:o, dacniro). The logic block is also responsible for initiating the required asynchronous clocks for the sampling switch (f and the comparator (^ _c ), as well as registering the final output (Dico). A design challenge in SAR ADCs is to maintain area efficiency when designing for moderate to high resolutions above 8 bits because the CD AC weights are binary, meaning that the total capacitance has to be doubled for each additional bit. The most compact arrangement of the capacitor array as shown in Figure 2a is through metal-oxide-metal (MOM) finger unit capacitor [5], whose size is fundamentally limited by the minimum distance between metal traces.

Recently, a new technique to implement the CDAC has been proposed in [6] that treats the difference between two MOM capacitors, denoted as C and C° in Figure 2b. This way, the binary weight can be adjusted by changing the break point distance to center (D), without multiplying the finger structure. As a result, the size of the unit length capacitor array follows N , as opposed to 2 ^N in the conventional case. Moreover, the unit length capacitor array can be placed above the other circuitry to further increase the area benefits.

[6] employs the conventional switching scheme which has the worst energy efficiency [7] because each bit is initially set to ’ G and updated in the next stage depending on the decision, thus any Ό’ decision wastes charge. [6] argues that a more efficient switching scheme would improve overall energy efficiency marginally due to the small charge capacity of the DAC. However, it is our contention that the switching scheme affects also the logic switching energy which represents a larger part of the total energy consumption of the ADC.

Monotonic switching [8] is one of the simple energy efficient schemes [7] that does not require any additional reference generation. Figure 3 compares monotonic switching progression to conventional switching. The energy efficiency here comes from each bit being set at the time of comparison and kept in the following stages, thus no charge is wasted. Another benefit of this method is that the sampling and the first comparison phases are combined, so the conversion takes one cycle shorter compared to the conventional switching scheme.

The drawback of the monotonic switching method is that the common-mode voltage at the input of the comparator gradually decreases down to ground during conversion. Although [8] states that this is beneficial for settling speed, it is detrimental to the comparator’s input-referred noise and offset because the input pair biasing condition is disrupted. An improvement proposed in [9] uses a complementary DAC that switches towards the opposite direction which in the end provides the constant common mode for the comparator.

The present invention builds on the area efficiency of [6] by incorporating a combination of the aforementioned energy efficient techniques to make it suitable for applications with stringent area and power constraints. This architecture outperforms the state-of-the-art. The following sections describe each building block in detail.

SUMMARY OF THE INVENTION in a first aspect, the invention provides a Successive Approximation Register Analog-to- Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) operatively connected to the track-and-hold switch and configured to receive the sampled input voltage from the track-and-hold switch, redistribute the sampled charge based on a digital code received from an asynchronous successive approximation logic circuit, and output the voltage corresponding to the manipulated sampled charge; a comparator configured to resolve the sign of the voltage on the capacitive digital-to-analog converter and output a decision. The asynchronous successive approximation logic circuit is operatively connected to the comparator and configured to implement the successive approximation algorithm by supplying the digital code to the capacitive digital-to-analog converter for redistributing the sampled charge depending on the decision from the comparator. The capacitive digital-to-analog converter comprises a constant common-mode switching logic.

In a preferred embodiment, the asynchronous logic circuit is configured to implement the successive approximation algorithm with a constant common mode switching scheme and driving a unit-length capacitor array CD AC.

In a further preferred embodiment, the track-and-hold switch comprises a Metal-Oxide- Silicon (MOS) transistor configured as a capacitor as a storage element. In a further preferred embodiment, the unit length capacitors are configured to realize binary weights.

In a further preferred embodiment, the energy efficiency is maximized by using the monotonic switching scheme for a better charge preservation, while keeping noise performance high using the constant common mode technique.

In a second aspect, the invention provides a use of the successive approximation register analog-to-digital converter as described in the preceding paragraphs, for applications with stringent area and power constraints, such as multichannel sensors and digital intensive system- on- chips.

The invention provides a comparatively small and low-power successive approximation register analog-to-digital converter (SAR ADC) architecture as described in the present document, more particularly one that is based on unit length capacitors, monotonic switching, and constant common mode techniques. The footprint of the circuit is comparatively very small thanks to realizing binary weights using unit length capacitors, and the energy efficiency may be maximized by using the monotonic switching scheme for better charge preservation, while keeping noise performance high using the constant common mode technique. This ADC may be useful for applications with stringent area and power constraints, such as multichannel sensors and digital intensive system-on-chips.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be understood better in light of the detailed description of preferred embodiments of the invention and in reference to the drawings, wherein figure 1 represents an ADC block diagram according to prior art; figure 2 (a) shows a 3 -bit CD AC implementation using conventional binary weighted capacitors according to prior art - source: [6]; figure 2 (b) shows a 3-bit CD AC implementation using unit-length capacitors according to prior art - source: [6]; figure 3 shows CD AC state progressions using a) conventional b) monotonic switching schemes according to prior art - source: [8]; figure 4 illustrates a use of complementary DAC for keeping common mode constant according to prior art-source: [9]; figure 5 shows ADC logic blocks; figure 6 shows flowcharts illustrating ADC theory of operation with a) monotonic switching b) conventional switching; figure 7 illustrates a) Standby logic, b) comparator clock generator, c) unit logic stage; figure 8 illustrates a) a CD AC schematic, and b) a layout of the capacitor array; figure 9 shows a dynamic double-tail comparator; and figure 10 shows a bootstrapped switch.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

Overview of the Architecture

The overall block diagram of the system is presented in Figure 1. The track and hold (T/H) switch stores the differential input voltage (VIN) on the capacitive digital-to- analog converter (CD AC). The comparator resolves the voltage on the DAC (VDAC), which changes after each decision (dec) based on the successive approximation program realized by the logic block (dacp9 _: o, dacn9:o). The logic block is also responsible for initiating the required asynchronous clocks for the sampling switch (f ) and the comparator (^ _c ), as well as registering the final output (D9:o).

Asynchronous dynamic logic

The asynchronous logic produces the internal clocks, adjusts CD AC, and registers the comparator decisions. The block diagram in Figure 5 denotes four main components: standby control, comparator clock, 10 conversion stages representing 10 bits, and register. The circuit is a hybrid implementation of dynamic and static CMOS techniques to achieve low-power and robustness. Figure 6a explains the theory of operation. The ADC starts at the standby mode where it tracks the input voltage, which is controlled by the circuit shown in Figure 7a. Upon a rising clock edge, the ADC samples the input voltage (r/> _s ), leaves the standby mode, and executes the chain of 10-unit stages. Each unit stage is realized by the circuit shown in Figure 7c. When a stage is enabled (em), a comparison request (reqi) is asserted. The comparator is clocked (f whenever a request is asserted as realized by the OR gate shown in Figure 7b. When the comparator decision (dec) is ready (rdy), the appropriate CD AC plate (dacpi or dacm) is set. This activates the next stage (em-i) when comparator decides ’O’. As each transition requires charge to be drawn from the power supply, monotonic switching provides significant energy savings at the logic side.

Capacitive DAC

The capacitive digital-to-analog-converter (CDAC) manipulates the sampled input voltage in order to compare it to different fractions of the full-scale voltage. The CDAC structure is similar to the one presented in [6] The main idea is to use the two capacitors, C and C, driven by complementary signals as illustrated in Figure 2b. If both capacitors deviate from a nominal capacitance Cm by the same amount C \ but with opposite polarities, the net charge redistribution on this capacitor pair yields an effective capacitance of Ceff = C - C - 2C \.

The effective capacitance can be weighted by modifying the distance D between the break point and the center point. A capacitor array can be built by using single unit length capacitors with different break points, rather than using multiples of a unit capacitor as in Figure 2a. This means that the area of the overall N-bit CD AC does not grow exponentially with 2 ^N , but linearly with N. In a good matching process, the effective capacitance can be made as small as in the order of 0.1 fF.

Mismatch variance of the unit length capacitor is higher than a unit capacitor because of the subtraction. To improve matching, some of the weights can be built using multiples of a unit length capacitor in a unary fashion. This causes total capacitance Ctotai to increase for the same Ceff. The input full scale voltage follows the relation VFS Ceff/Ctotai, meaning that the maximum applicable input voltage reduces as more unary capacitors are used to improve matching. The detailed analysis this effect of the number of binary differential capacitors on the ADC performance can be found in [6]

In this work, we use the constant common-mode unit length CD AC depicted in Figure 8a for a 10-bit implementation, but it can be adapted to any number of bits. Four single- ended unit-length capacitor arrays are used to achieve differential and constant common mode operation, indicated as DACP+, DACN-, DACN+, DACP-. DACP- switches complementary to DACP+, and DACN- switches complementary to DACN+, such that an increase in VDAC+ is countered by a decrease in VDAC-, and vice versa, to maintain the common mode voltage constant. Figure 8b illustrates the example layout. 5 least significant bits are built using binary unit length capacitors, and 3 most significant bits (MSB) are built using unary unit length capacitors. This is to maintain sufficient input range while keeping mismatch under control as explained in [6] The remaining two bits are implicit as the first comparison is performed on the sampled input, and the last two bits are implemented single-ended. In a preferred embodiment, the nominal length of 2 pm and the unit difference of 200 nm provides 2 fF Cnom and 0. IfF Ceff . The DAC drivers are basic CMOS inverters (INVERTER in Figure 8a) and buffers (BUFFER in Figure 8a).

Dynamic double-tail comparator

The comparator employs the well-known dynamic double-tail architecture [10], [11] and is shown in Figure 9. The input transistors and the tail switch of the first stage are sized to be in the weak inversion regime for keeping input noise level low. Simulations shows a gain of 12 for the first stage. The second stage uses high-Vt PMOS and low- Vt NMOS transistors for a low switching threshold for the cross-coupled latch. This provides enough latency for the first stage output difference to settle. The output of the latch is buffered, and a ready signal is issued after each decision. The two latch outputs are at high state during pre-charge, therefore a simple OR gate is able to produce the ready signal.

Track and hold switch

The most straightforward approach for the sampling switch is to use the simple CMOS transmission gate. However, the MOS transistor ’on’ resistance curve is nonlinear hence produces harmonics. The problem is exacerbated by PVT variations. An obvious solution is to increase the switch sizes to reduce the resistance. However, this has an adverse effect of increasing the charge injection and the clock feed-through effects. Therefore, the linearity of the simple CMOS switch is sufficient only for resolutions up to 8 bits.

The most common solution for the switch nonlinearity in higher resolution ADCs is to employ a bootstrapped switch [14] In this architecture, the overdrive voltage of the pass transistor is kept constant thanks its gate driven by a pre-charged capacitor in series with the input voltage. This allows the resistance to be relatively constant over the full input range, and thus the switch size can be kept as small as the bandwidth requirement permits.

The bootstrapped switch used in this work is shown in Figure 10. All transistors M0- M6 are high-voltage type in order to withstand internal voltages exceeding the nominal supply value. A PMOS transistor (M3) is used as the pre-charge capacitor for reducing the silicon footprint as it has superior capacitance density compared to other available passive devices. The resulting linearity is above 15 bits across PVT corners and mismatch. REFERENCES

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