AUDIO AMPLIFICATION SYSTEMS, DEVICES AND METHODS CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This application claims priority to U.S. Application Nos. 17/955,000 filed September 28, 2022, entitled GAIN CALIBRATION FOR AUDIO AMPLIFIERS, 17/955,034 filed September 28, 2022, entitled DIGITAL-TO-ANALOG CONVERTER CALIBRATION FOR AUDIO AMPLIFIERS, 17/955,058 filed September 28, 2022, entitled WINDOW CIRCUITS, DEVICES AND METHODS FOR AUDIO AMPLIFIERS, 17/955,080 filed September 28, 2022, entitled MULTI-LEVEL OUTPUT DRIVER WITH HIGH-VOLTAGE OUTPUT PROTECTION FOR AUDIO AMPLIFIERS, 17/955,107 filed September 28, 2022, entitled OUTPUT CAPACITANCE DISTORTION CORRECTION FOR AUDIO AMPLIFIERS, 17/955,191 filed September 28, 2022, entitled PULSE- WIDTH MODULATION AUDIO AMPLIFIER HAVING FEED FORWARD LOOP, 17/955,219 filed September 28, 2022, entitled PULSE-WIDTH MODULATION AUDIO AMPLIFIER HAVING COMPENSATED REGULATION LOOP, 17/955,244 filed September 28, 2022, entitled REFERENCE STARTUP CIRCUIT FOR AUDIO AMPLIFIERS, 17/955,271 filed September 28, 2022, entitled LOW VOLTAGE SYSTEM FOR AUDIO AMPLIFIERS, and 17/955,292 filed September 28, 2022, entitled DIGITAL-TO-ANALOG CONVERTER ARCHITECTURE FOR AUDIO AMPLIFIERS, the disclosure of each of which is hereby expressly incorporated by reference herein in its respective entirety. BACKGROUND Field [0002] The present disclosure relates to audio amplifier circuits for wearable audio devices such as earbuds or headphones. Description of the Related Art [0003] A wearable audio device can be worn by a user to allow the user to enjoy listening of an audio content stream being played by a mobile device. Such an audio content stream may be provided from the mobile device to the wearable audio device through, for example, a short-range wireless link. Once received by the wearable audio device, the audio content stream can be processed by one or more circuits to generate an output that drives a speaker to generate sound waves representative of the audio content stream. [0004] It is desirable to have the foregoing sound waves provide reproduction of the audio content stream with high-fidelity. It is also desirable for the wearable audio device to operate in a power-efficient manner, since such devices are commonly powered by batteries having limited capacities. SUMMARY [0005] In accordance with a number of implementations, the present disclosure relates to an audio amplification system that includes a digital audio path configured to provide a digital signal, and an audio amplifier configured to receive the digital signal as an input signal and generate an output signal. The audio amplification system further includes one or more features configured to support operation of the audio amplification system and selected from a first feature, a second feature, a third feature, a fourth feature, a fifth feature, a sixth feature, a seventh feature, an eighth feature, a ninth feature and a tenth feature. [0006] In some embodiments, the first feature includes a calibration circuit including a tone generator configured to inject a tone having a frequency to the digital audio path, such that the input signal includes the tone. The calibration circuit further includes a first sampling circuit configured to sample the output signal at an output node of the audio amplifier, and a second sampling circuit configured to sample the input signal at an input node of the audio amplifier. The calibration circuit further includes a gain adjustment circuit configured to generate a correction signal based on the sampled output signal and the sampled input signal to correct for a gain variation of the audio amplifier. [0007] In some embodiments, the second feature includes a tone generator configured to generate a windowed tone for calibration. The tone generator includes a window circuit having a pulse train generator configured to generate a train of rectangular pulses having M amplitude values, with the quantity M being an integer greater than 1. The window circuit further includes M-1 accumulators arranged in series to transform the train of rectangular pulses into an output that is representative of an M- th order window for the windowed tone. [0008] In some embodiments, the third feature includes a digital-to-analog converter having a conversion circuit configured to receive a digital signal and generate an analog signal representative of the digital signal. The conversion circuit includes a plurality of bit cells each configured to receive a voltage. The digital-to-analog converter further includes a calibration circuit configured to provide the voltage to each of the bit cells of the conversion circuit. The calibration circuit includes a first circuit configured to generate a first output voltage based on a first reference voltage, and a second circuit configured to compare the first output voltage and a second reference voltage. The calibration circuit further includes a calibration block configured to provide an adjustment to the first circuit based on the comparison of the first output voltage and the second reference voltage, such that the voltage provided to each of the bit cells of the conversion circuit is compensated for a change in the first reference voltage. [0009] In some embodiments, the fourth feature includes an output driver that includes a first driver circuit configured to operate with a first supply voltage and generate an output signal having an amplitude in a first range, a second driver circuit configured to operate with a second supply voltage and generate an output signal having an amplitude in a second range, a controller configured to operate any one of the first and second driver circuits, such that an output signal of the output driver has an amplitude in an overall range that includes the first and second ranges, and a switch circuit implemented to isolate one driver circuit from another driver circuit when the driver circuit is inactive and the other driver circuit is active. [0010] In some embodiments, the fifth feature includes an audio driver that includes an audio amplifier configured to operate in a high output resistance (HOR) mode with an HOR driver or a zero output resistance (ZOR) mode with a ZOR driver. The audio amplifier includes an output node coupled to both of the HOR driver and the ZOR driver, such that the output node is subject to an effect of the ZOR driver in a disabled state when the audio amplifier is operating in the HOR mode. The audio driver further includes a control system configured to correct for the effect of the disabled ZOR driver by adjusting an input signal. [0011] In some embodiments, the sixth feature includes an audio amplifier configured to amplify a digital signal and including an input node for receiving the digital signal, a controller coupled to the input node through a feed-forward path, with the controller configured to generate a driving signal based on the digital signal, and a driver configured to provide an amplified signal at an output node based on the driving signal. The audio amplifier further includes a feedback circuit that couples the output node of the driver to the controller. The feedback circuit is configured to provide a feedback signal for comparison with a reference signal representative of the digital signal to generate an error signal, such that the feedback circuit provides a form of the error signal to the controller for adjustment of the digital signal. [0012] In some embodiments, the seventh feature includes an audio amplifier that includes an input for receiving a signal to be amplified, an amplification stage configured to amplify the signal based on pulse width modulation and provide the amplified signal at an output node, and a feedback circuit implemented between the output node and the input node. The feedback circuit includes a series arrangement of a high bandwidth input common mode loop and a low bandwidth output common mode loop. The low bandwidth output common mode loop is configured to provide a desired phase change for the high bandwidth input common mode loop. [0013] In some embodiments, the eighth feature includes a reference source configured to generate a reference voltage and including a bandgap core and a startup circuit. The startup circuit includes a first transistor coupled to a supply source and configured to provide a current to a reference resistance when the reference source is turned on, to thereby provide a reference voltage at a first node between the first transistor and the reference resistance. The startup circuit further includes a second transistor coupled to the supply source to provide a second node therebetween, with the second transistor having a gate coupled to the first node, such that the second transistor is off and a startup voltage at the second node is up when the reference voltage is at or below a threshold voltage, and the second transistor is on and the startup voltage at the second node is down when the reference voltage exceeds the threshold voltage. The startup circuit further includes a third transistor implemented between the supply source and a startup node of the bandgap core, with the third transistor having a gate coupled to the second node such that the third transistor turns on to inject a startup current to the startup node when the startup voltage is up, and turns off when the startup voltage is down. [0014] In some embodiments, the ninth feature includes a low voltage system that includes a capacitor between an output node of an amplifier and ground, with the output node connectable to a load. The amplifier is configured to operate with a series of pulses. The low voltage system further includes a monitoring circuit configured to monitor a voltage at the capacitor against a desired low voltage value. The low voltage system further includes a control system configured to generate the series of pulses for the amplifier, and to control charging and discharging of the capacitor based on an output of the monitoring circuit to regulate the voltage at the output node at approximately the desired low voltage value. [0015] In some embodiments, the tenth feature includes a digital-to-analog converter (DAC) system that includes an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells, with the selected number being variable, such that the array consumes a quiescent current that depends on the selected number. The control system is further configured to change the selected number when a signal condition exceeds a threshold duration. [0016] In some embodiments, the audio amplification system can include at least two of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0017] In some embodiments, the audio amplification system can include at least three of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0018] In some embodiments, the audio amplification system can include at least four of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0019] In some embodiments, the audio amplification system can include at least five of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0020] In some embodiments, the audio amplification system can include at least six of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0021] In some embodiments, the audio amplification system can include at least seven of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0022] In some embodiments, the audio amplification system can include at least eight of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0023] In some embodiments, the audio amplification system can include at least nine of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0024] In some embodiments, the audio amplification system can include all of the foregoing first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth features. [0025] In some embodiments, any of the foregoing audio amplification systems can be implemented in a wireless audio device such as a wireless headphone or a wireless earphone. [0026] For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS [0027] Figure 1 depicts a system that includes a wearable audio device in communication with a host device, where the wearable audio device includes an audio amplifier circuit. [0028] Figure 2 shows that the wearable audio device of Figure 1 can be implemented as a device configured to be worn at least partially in an ear canal of a user. [0029] Figure 3 shows that the wearable audio device of Figure 1 can be implemented as part of a headphone configured to be worn on the head of a user, such that the audio device is positioned on or over a corresponding ear of the user. [0030] Figure 4 shows that in some embodiments, the audio amplifier circuit of Figure 1 can include a number of functional blocks. [0031] Figure 5 shows a block diagram of an audio amplifier circuit that is a more specific example of the audio amplifier circuit of Figure 4. [0032] Figure 6 shows a block diagram that includes a digital audio path block that is a more specific example of the digital audio path block of Figure 5. [0033] Figure 7 shows a block diagram of an amplifier block that is a more specific example of the amplifier block of Figure 5. [0034] Figure 8 shows a block diagram of a digital logic circuit block that is a more specific example of the digital logic circuit block of Figure 5. [0035] Figure 9 shows a gain compute block that is a more specific example of the gain compute block of Figure 8. [0036] Figure 10 shows various functional blocks of the audio amplifier circuit of Figure 5 configured to provide a gain calibration sub-system. [0037] Figure 11 shows a more detailed example of the gain calibration block of Figure 10. [0038] Figure 12 shows a block diagram of a gain calibration architecture that is similar to the examples of Figures 10 and 11. [0039] Figure 13 shows a gain calibration architecture that can be implemented as a more specific example architecture of Figure 12. [0040] Figures 14A to 14C show examples of how discrete Fourier transform computation can be achieved to provide a desired effect. [0041] Figure 15 shows an example of a windowing process that can be applied to a calibration tone signal. [0042] Figure 16 shows a block diagram of a window circuit that can provide windowing functionality, including sinc function based windowing functionality. [0043] Figure 17 shows an example of a 4-th order window generated by the window circuit of Figure 16 configured as a sinc4 window generator. [0044] Figures 18A and 18B show an example of a 4th order window in time domain and in frequency domain, generated by the window circuit of Figures 16 and 17. [0045] Figure 19 shows a DAC configured to convert a digital input signal into a corresponding analog output signal. [0046] Figure 20 shows that in some embodiments, the DAC of Figure 19 can be implemented as the DAC as described herein in reference to Figures 5, 7 and 8. [0047] Figure 21 depicts a portion of a DAC calibration circuit configured to set a DAC bit cell current. [0048] Figure 22 depicts a DAC calibration circuit configured to set a DAC bit cell current. [0049] Figure 23 shows a DAC calibration circuit that can be a more specific example of the DAC calibration circuit of Figure 22. [0050] Figure 23 shows an example of a multi-level output driver configured to generate output pulses having an amplitude that ranges from approximately 0 to a maximum value based on a supply voltage. [0051] Figure 25 shows that in some embodiments, a multi-level output driver can include a plurality of driver groups where each driver group is configured to receive an input signal and generate an output signal having pulses with an amplitude in a range based on a respective supply voltage value. [0052] Figure 26 shows an example where a multi-level output driver includes three driver groups and a switch assembly that are implemented to provide an output having pulses with amplitude in a range of approximately 0 to approximately battery voltage. [0053] Figure 27 shows an output portion of an H-bridge driver configured to operate in such a HOR mode or ZOR mode. [0054] Figure 28 depicts various currents that may be present during a HOR mode operation. [0055] Figure 29 shows a portion of a digital audio path having parts that are described in greater detail in reference to Figures 5 and 6. [0056] Figure 30 depicts an audio amplifier such as a PWM amplifier. [0057] Figure 31 shows an example of the feedback path and control loop circuit of Figure 12. [0058] Figure 32 shows that in some embodiments, an audio amplifier such as a PWM amplifier can include a feed-forward circuit for a digital input signal, such that the digital input signal is provided to a PWM controller from an input node. [0059] Figure 33 shows an example of an architecture of an audio amplifier that can be implemented to provide the feed-forward functionality of Figure 32. [0060] Figure 34 depicts an audio circuit that includes an audio amplifier that can be similar to the PWM amplifier of Figures 5 and 7. [0061] Figure 35 shows a feedback circuit that can be a more specific example of the feedback circuit of Figure 34. [0062] Figure 36 shows an example of a conventional bandgap reference circuit having a startup circuit. [0063] Figure 37 shows a bandgap reference circuit having a startup circuit with one or more features as described herein. [0064] Figure 38 shows a circuit diagram of a low voltage system that can be utilized in an audio amplifier having one or more features as described herein. [0065] Figure 39 shows the low voltage system of Figure 38 being operated with specific example settings. [0066] Figure 40 shows examples of various signal traces during the operation of the low voltage system of Figure 39. [0067] Figure 41A depicts a digital-to-analog converter (DAC) having N-bit resolution, where N is a positive integer. [0068] Figure 41B depicts the DAC of Figure 41A in a block form. [0069] Figure 42A depicts a DAC that can be a more specific example of the DAC of Figure 41A. [0070] Figure 42B depicts the DAC of Figure 42A in a block form. [0071] Figure 43 shows that in some embodiments, a DAC can include a variable bit cell array size. DETAILED DESCRIPTION OF SOME EMBODIMENTS [0072] The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. [0073] Figure 1 depicts a system 1010 that includes a wearable audio device 1002 in communication with a host device 1008. Such communication, depicted as 1007 in Figure 1, can be supported by, for example, a wireless link such as a short- range wireless link in accordance with a common industry standard, a standard specific for the system 1010, or some combination thereof. In some embodiments, the wireless link 1007 includes digital format of information being transferred from one device to the other (e.g., from the host device 1008 to the wearable audio device 1002). [0074] In Figure 1, the wearable device 1002 is shown to include an audio amplifier circuit 1000 that provides an electrical audio signal to a speaker 1004 based on a digital signal received from the host device 1008. Such an electrical audio signal can drive the speaker 1004 and generate sound representative of a content provided in the digital signal, for a user wearing the wearable device 1002. [0075] In Figure 1, the wearable device 1002 is a wireless device; and thus typically includes its own power supply 1006 including a battery. Such a power supply can be configured to provide electrical power for the audio device 1002, including power for operation of the audio amplifier circuit 1000. It is noted that since many wearable audio devices have small sizes for user-convenience, such small sizes places constraints on power capacity provided by batteries within the wearable audio devices. [0076] In some embodiments, the host device 1008 can be a portable wireless device such as, for example, a smartphone, a tablet, an audio player, etc. It will be understood that such a portable wireless device may or may not include phone functionality such as cellular functionality. In such an example context of a portable wireless device being a host device, Figures 2 and 3 show more specific examples of wearable audio devices 1002 of Figure 1. [0077] For example, Figure 2 shows that the wearable audio device 1002 of Figure 1 can be implemented as a device (1002a or 1002b) configured to be worn at least partially in an ear canal of a user. Such a device, commonly referred to as an earbud, is typically desirable for the user due to compact size and light weight. [0078] In the example of Figure 2, a pair of earbuds (1002a and 1002b) can be provided – one for each of the two ears of the user – and each earbud can include its own components (e.g., audio amplifier circuit, speaker and power supply) described above in reference to Figure 1. In some embodiments, such a pair of earbuds can be operated to provide, for example, stereo functionality for left (L) and right (R) ears. [0079] In another example, Figure 3 shows that the wearable audio device 1002 of Figure 1 can be implemented as part of a headphone 1003 configured to be worn on the head of a user, such that the audio device (1002a or 1002b) is positioned on or over a corresponding ear of the user. Such a headphone is typically desirable for the user due to audio performance. [0080] In the example of Figure 3, a pair of audio devices (1002a and 1002b) can be provided – one for each of the two ears of the user. In some embodiments, each audio device (1002a or 1002b) can include its own components (e.g., audio amplifier circuit, speaker and power supply) described above in reference to Figure 1. In some embodiments, one audio device (1002a or 1002b) can include an audio amplifier circuit that provides outputs for the speakers of both audio devices. In some embodiments, the pair of audio devices 1002a, 1002b of the headphone 1003 can be operated to provide, for example, stereo functionality for left (L) and right (R) ears. [0081] Figure 4 shows that in some embodiments, the audio amplifier circuit 1000 of Figure 1 can include a number of functional blocks. More particularly, in Figure 4, an audio amplifier circuit 1000 is shown to include a digital logic circuit block 1020, an amplifier block 1022, a power management block 1024, and an ancillary block 1026. Examples related to such blocks are described herein in greater detail. [0082] In Figure 4, the audio amplifier circuit 1000 is shown to further include various interfaces to allow the audio amplifier circuit 1000 to interact with other devices external to the audio amplifier circuit 1000. More particularly, an interface indicated as 1030 can be configured to support input/output (I/O) functionality with respect to a host device (e.g., 1008 in Figure 1). An interface indicated as 1034 can be configured to support providing of electrical audio signals to a speaker (e.g., 1004 in Figure 1). An interface indicated as 1032 can be configured to support providing of electrical power to various parts of the audio amplifier circuit 1000. One or more ground pins collectively indicated as 1036 (GND) can be configured to provide a grounding connection for the audio amplifier circuit 1000 relative to, for example, the audio device 1002 of Figure 1. [0083] Figure 5 shows a block diagram of an audio amplifier circuit 1000 that is a more specific example of the audio amplifier circuit 1000 of Figure 4. In Figure 5, a digital logic circuit block, generally indicated as 1020, can include a number of more specific functional blocks; an amplifier block, generally indicated as 1022, can include a number of more specific functional blocks; a power management block, generally indicated as 1024, can include a number of more specific functional blocks; and an ancillary block, generally indicated as 1026, can include a number of more specific functional blocks. Similarly, an interface indicated as 1030 can include a number of pins to support input/output (I/O) functionality with respect to a host device; an interface indicated as 1034 can include a number of pins to support providing of electrical audio signals to a speaker; an interface indicated as 1032 can include a number of pins to support providing of electrical power to various parts of the audio amplifier circuit 1000; and one or more ground pins collectively indicated as 1036 (GND) can be implemented to provide a grounding connection for the audio amplifier circuit 1000. [0084] Referring to the example of Figure 5, the digital logic circuit block 1020 can include a receiver (Rx) block 1040 configured to receive, for example, a pulse- density modulation (PDM) signal through a DATA pin of the interface 1030. The PDM Rx block 1040 is shown to also receive a clock signal through a CLK pin of the interface 1030. The PDM Rx block 1040 is shown to provide an output based on the input PDM signal. [0085] It will be understood that while various examples are described herein in the context of pulse-density modulation of signals, one or more features of the present disclosure can also be implemented utilizing other types of modulations including other types of pulse modulations. [0086] In Figure 5, the digital logic circuit block 1020 can further include a digital audio path block 1042. Such a block is shown to receive the output of the PDM Rx block 1040 and route the received signal to the amplifier block 1022. Additional examples related to the digital audio path block 1042 are described herein in greater detail. [0087] As shown in Figure 5, the digital logic circuit block 1020 can also include various blocks for providing control and calibration functionalities. For example, amplifier controller 1090, resistance network control block 1064, amplifier operating mode (e.g., HOR/ZOR mode) control block 1062, inter-integrated circuit (I2C) auxiliary block 1092, registers block 1094, PDM detect block 1060 and loudness protection block 1066 can provide and/or support various control functionalities described herein. In another example, current ratio measurement calibration block 1068 and gain calibration block 1070 can provide calibration functionalities described herein. More particularly, the current ratio measurement calibration block 1068 can support generation of a reference signal for a loop circuit as described herein, and the gain calibration block 1070 can provide various functionalities for gain calibration as described herein. [0088] Referring to the example of Figure 5, the amplifier block 1022 is shown to include a pulse-width modulation (PWM) controller 1050 configured to receive a feedforward digital signal from the digital audio path block 1042 of the digital logic circuit block 1020 (through a path indicated as 1043) and generate control signals for an H- bridge driver 1052. The H-bridge driver 1052 provides analog electrical audio signals HPN, HPP as outputs. Such electrical audio signals can be provided to a speaker through respective pins of the interface 1034. [0089] In the example of Figure 5, the amplifier block 1022 is configured as a digital PWM Class D amplifier. In addition to the H-bridge driver 1052 being pulse-width modulated by the PWM controller 1050 based on the feedforward digital signal from the digital audio path block 1042, a closed-loop architecture is provided. Such a closed loop is shown to include an input resistance network 1080 coupled to the HPN and HPP outputs of the H-bridge driver 1052, with the input resistance network 1080 being coupled to a loop filter 1046 through summing nodes 1081, 1083. An analog output from the loop filter 1046 is shown to be converted into a digital signal by an analog-to- digital converter (ADC) 1048 such as a successive approximation register (SAR) ADC. The digital signal from the SAR ADC 1048 is provided to the PWM controller 1050. [0090] In the example of Figure 5, the amplifier block 1022 is configured to provide a reference analog signal for the foregoing closed-loop circuit. More particularly, a digital signal from the digital audio path block 1042 is shown to be provided to a digital-to-analog converter (DAC) 1044 (through a path indicated as 1045), and the resulting analog signal is provided to the summing nodes 1081, 1083. The summing nodes 1081, 1083 are also shown to be provided with respective signals from a common-mode-limit (CML) amplifier 1082. [0091] In the example of Figure 5, the audio amplifier circuit 1000 is shown to include a gain calibration feature. Such a feature is shown to include a calibration ADC 1084 coupled to the HPN and HPP outputs of the H-bridge driver 1052 to provide a digital signal representative of the analog output signals of the H-bridge driver 1052. The digital signal from the calibration ADC 1084 is shown to be provided to the gain calibration block 1070 of the digital logic circuit block 1020. [0092] In the example of Figure 5, the H-bridge driver 1052 shown to be provided with multiple levels of supply voltages (e.g., VBAT, VDD_A, VDD_B, VDD_D, VDD_E). Such multiple voltage levels can allow the H-bridge driver 1052 to operate with improved power efficiency. [0093] Additional examples concerning the amplifier block 1022 are described herein in greater detail. [0094] In Figure 5, the power management block 1024 can include a number of functional blocks configured to provide and/or support providing of power to various parts of the audio amplifier circuit 1000. For example, the power management block 1024 can be configured to provide routing of multiple supply voltage levels (e.g., VBAT, VDD_A, VDD_B, VDD_D, VDD_E) to the H-bridge driver 1052 of the amplifier block 1022. For the example supply voltage levels, VBAT > VDD_A > VDD_B > VDD_D > VDD_E. [0095] Such supply voltages can be provided from source(s) external to the audio amplifier circuit 1000, from internal source(s), or some combination thereof. In the example of Figure 5, supply voltages VBAT, VDD_A and VDD_B are provided from external source(s); VDD_D may be provided from an external source or from an internal source implemented as a low drop out (LDO) regulator 1130; and VDD_E is provided from an internal source implemented as a low voltage monitor (LVM) supply 1132. [0096] Some or all of the foregoing voltages can be monitored by one or more voltage monitors. For example, a supply voltage monitor (SVM) 1120 is shown to monitor the voltages VBAT, VDD_A, VDD_B and VDD_D. Such an SVM can include low power low resolution ADCs that monitor the supply voltages and produce respective digital outputs representative of the supply voltages; and such monitored digital outputs can be utilized by other digital circuitry to control various functionalities of the audio amplifier circuit 1000. In another example, the voltage VDD_E is shown to be self- monitored by the LVM supply 1132. [0097] Referring to the example of Figure 5, the power management block 1024 is shown to further include a reference (Ref) block 1110. Such a reference block can be implemented as a low voltage, low power bandgap reference circuit configured to operate with a supply voltage (e.g., VDD_B) to produce a low reference voltage as an output. Such a reference voltage can be utilized for operation of an analog LDO regulator 1112 and a digital LDO regulator 1114, as well as other functional blocks of the audio amplifier circuit 1000. The analog LDO regulator 1112 can be implemented as a lower power linear regulator configured to provide a desired voltage for a number of circuits of the audio amplifier circuit 1000. The digital LDO regulator 1114 can be implemented as a low power linear regulator configured to provide a desired voltage for various digital logic and digital core circuits of the audio amplifier circuit 1000. [0098] Referring to the example of Figure 5, the power management block 1024 is shown to further include a low power oscillator (LPO) 1118. Such an LPO can be configured to support operation of the audio amplifier circuit 1000. The power management block 1024 is shown to further include a sensor block 1116 such as a temperature sensor. Such a sensor can be configured to detect operating condition(s) (e.g., temperature) of some or all of the audio amplifier circuit 1000; and such sensed condition(s) can be utilized to support one or more functionalities (e.g., fault protection) for the audio amplifier circuit 1000. [0099] In Figure 5, the ancillary block 1026 is shown to include a power-on-reset (POR) block 1100. Such a POR block can be implemented to provide a number of functionalities. For example, power-on reset functionality can be provided by the POR block 1100, where the POR block 1100 monitors the RESET_B pin and supply voltage conditions to control and/or support power-on sequencing of various regulators, clock system and wall level shifters utilizing respective control signals (Pups). Once such power-on sequencing is achieved and the controlled components are operating in a stable manner, a release signal (Dig_reset_B) is provided to allow operation of various digital blocks. [0100] The POR block 1100 can also control and/or support a power-down sequence. Such a power-down sequence can be achieved in response to a control signal from a host device (e.g., setting RESET_B to a initiate power-down), or based on detection of one or more conditions. Such conditions can include, for example, a brownout detection and various fault detections. [0101] In Figure 5, the ancillary block 1026 is shown to include a one-time programmable memory (OTP) 1102 and a block 1104 providing control and register functionalities for the OTP block 1102. Such functionalities can include issuing of a control signal (I2C address) to the I2C block 1092 to load appropriate registers of the Registers block 1094 during a boot process. [0102] Figure 6 shows a block diagram that includes a digital audio path block 1042 that is a more specific example of the digital audio path block 1042 of Figure 5. In Figure 6, a pulse-density modulation (PDM) receiver (Rx) block 1040 is shown to receive a PDM signal DATA and a clock signal CLK, and provide a PDM digital signal to the digital audio path block 1042. [0103] More particularly, the PDM digital signal from the PDM Rx block 1040 is shown to be provided to a digital low-pass filter (PDM LPF) 1140. Such a filter block can be configured to, for example, attenuate out-of-band noise in the received PDM digital signal (e.g., noise resulting from a transmit (Tx) modulation in a host device). The PDM LPF block 1140 of Figure 6 can also be configured to convert the PDM input signal into an output digital signal having pulse-code modulation (PCM). [0104] In Figure 6, the filtered PCM signal from the PDM LPF block 1140 is shown to be provided to an equalizer (EQ) block 1142. Such an EQ block can be configured to support gain and mute functionalities, as well as high-output resistance (HOR) and/or zero-output resistance (ZOR) operating modes. The EQ block 1142 provides an output PCM signal to a calibration tone mixer 1144. Additional details concerning the EQ block 1142 are provided herein. [0105] Referring to Figure 6, the calibration tone mixer 1144 is shown to mix a calibration tone signal from a gain calibration block 1070 with the output PCM signal from the EQ block 1142. Such mixing functionality can be provided during a calibration process such as an HOR/ZOR gain calibration process. Additional details concerning the HOR/ZOR gain calibration process are provided herein. [0106] In Figure 6, the output of the calibration tone mixer 1144 is also shown to be processed through a number of blocks before being provided a digital-to-analog converter (DAC) 1044 (also 1044 in Figure 5) through a path 1045 for a closed-loop circuit as described herein. More particularly, the output (PCM signal) of the calibration tone mixer 1144 is shown to be provided to a signal limiter block 1146. Such a signal limiter can be configured to maintain a threshold limit for a DAC modulator (e.g., delta sigma modulator (DSM)) 1148 and also improve handling of low supply voltage operating conditions (e.g., when a HOR mode load reactance causes supply voltage requirements of an H-bridge drive to increase beyond a pure resistive load condition). [0107] Referring to Figure 6, it is noted that for the foregoing low voltage operating conditions, a SAR ADC (e.g., 1048 in Figure 5) in the closed-loop circuit can be driven into saturation if the power supply is insufficient to provide the required peak voltage for the H-bridge driver (1052 in Figure 5) needed to develop an output voltage at the load. If such a SAR ADC is saturated, the corresponding loop filter (1046 in Figure 5) is saturated and is slow to recover from such overload conditions, resulting in undesirable audio artifacts. Thus, it is desirable to have the SAR ADC and loop filter prevented from entering saturation. Such saturation-prevention can be accomplished by limiting the digital audio signal in digital path of the closed-loop circuit to prevent the closed-loop circuit from trying to generate an unachievable output voltage and thereby push the SAR ADC and loop filter into saturation. [0108] Referring to Figure 6, the signal limiter 1146 can be configured to prevent the SAR ADC and loop filter from being in saturation due to insufficient supply voltage while trying to produce an output voltage from the corresponding digital input signal. The signal limiter 1146 can limit (e.g., by clipping the digital audio signal to a clip level) based on either or both of loop filter saturation detection signal (LF Sar. Det.) and SAR ADC output level (SAR ADC out) to keep the SAR ADC and the loop filter from overloading. It is noted that the SAR ADC output level can be monitored to have the signal limiter to clip the digital audio signal when the SAR ADC output level is close to saturation. [0109] In Figure 6, the signal limiter block 1146 is shown to provide an output signal to a DAC modulator (e.g., delta sigma modulator (DSM)) 1148. As described above, such an output of the signal limiter block 1146 can be clipped to avoid the SAR ADC and loop filter from being in saturation. The output of the signal limiter block 1146 can also prevent the DAC DSM 1148 from overloading. [0110] In the example of Figure 6, the DAC DSM block 1148 can be configured to re-modulate a higher-bit input signal (e.g., 24-bit signal), through delta-sigma modulation, into a lower-bit signal (e.g., 9-bit signal) that is appropriate for a dynamic element matching (DEM) block 1150. Accordingly, the example 9-bit DSM output signal drives the DEM block 1150 which can be implemented as a digital block configured to, for example, randomize a pattern of 512-bit cell drive to the DAC 1044 in a manner to linearize the DAC’s response for use as a multi-bit delta-sigma DAC. Such a configuration can provide a desirable reference audio signal for the closed-loop circuit described herein. [0111] In Figure 6, a feedforward signal is shown to be provided to a PWM controller (1050 in Figure 5) from an output of the signal limiter 1146 through a path 1043. As described herein, such a feedforward signal may or may not include a calibration tone signal mixed therein, depending on operating status of the gain calibration process. [0112] In addition to the PDM LPF block 1140, EQ block 1142, mixer 1144, signal limiter block 1146, DSM block 1148 and DEM block 1150 that can be generally referred to as the digital audio path block 1042, Figure 6 also shows a number of blocks that support various functionalities of the audio amplifier circuit (1000 in Figure 5). For example, a PDM detection block 1060 (also 1060 in Figure 5) is shown to be coupled to the PDM Rx block 1040. The PDM detection block 1060 can be configured to detect one or more states of PDM digital audio interface, including one or more fault conditions, to support operation and control of the audio amplifier circuit 1000. [0113] In another example, a loudness protection block 1066 (also 1066 in Figure 5) is shown to be coupled to the PDM Rx block 1040. The loudness protection block 1066 can be configured to monitor both of two output channels (main channel and auxiliary channel) of the PDM Rx block 1040. Upon loudness detection (e.g., digital audio signal exceeding a threshold), the loudness protection block 1066 can issue a fault signal to provide a muting or fault condition functionality. [0114] In Figure 6, the loudness protection block 1066 can include a pair of filter stages for the two output channels of the PDM Rx block 1040. Each filter stage can include a cascaded low-pass filter and high-pass filter structure configured to approximate a frequency response such as an A-weighted frequency response. The filtered outputs can be provided to respective absolute value circuits, and outputs thereof can then be provided to comparator circuits and compared against a programmed threshold for each of the main channel, auxiliary channel and main-minus- auxiliary values. Logic outputs of the comparators can be sent to a multiplexer that can trigger a fault signal depending on a combination of the three comparator outputs. [0115] In Figure 6, a number of functional blocks are shown to be coupled to and/or be related to one or more functional blocks of the digital audio path block 1042. For example, a digital-to-analog converter (DAC) 1044 is shown to be coupled to an output of the DEM block 1150. Such a DAC can be utilized to provide a reference signal for a closed-loop architecture of the audio amplifier circuit (1000 in Figure 5). Additional details concerning the closed-loop architecture are described herein. [0116] In another example, a HOR/ZOR state control block 1062 is shown to be coupled to the EQ block 1142. Such a control block, along with a resistance control (Rout ctrl) block 1064 and a resistance network 1080, can be utilized to provide various functionalities associated with high-output resistance (HOR) and zero-output resistance (ZOR) operating modes. Additional details concerning such operating modes are described herein. [0117] In yet another example, a gain calibration block 1070 is shown to provide a calibration tone to the mixer 1144 based on inputs from signal limiter 1146 and a calibration ADC 1084. Additional details concerning gain calibration of the audio amplifier circuit (1000 in Figure 5) are described herein. [0118] In Figure 6, operations of various functional blocks are shown to be supported by audio path registers 1094. Such registers can be a part of or associated with the registers block 1094 of Figure 5 and be configured in a similar manner. [0119] Figure 7 shows a block diagram of an amplifier block 1022 that is a more specific example of the amplifier block 1022 of Figure 5. The amplifier block 1022 of Figure 7 includes a digital PWM synthesis class D amplifier architecture. It is noted that unlike a purely analog class D amplifier architecture where pulse-width modulation (PWM) is analog, the amplifier architecture of the amplifier block 1022 includes pulse width modulation of H-bridge drivers being developed via digital pulse-width modulation by a digital PWM controller 1050. The amplifier architecture of the amplifier block 1022 also includes a closed-loop control feature having a high loop gain error amplifier and an ADC digitizer. [0120] As described in reference to Figure 6, a feedforward digital signal is provided to the PWM controller 1050 from the digital audio path 1042 of the digital logic circuit 1020. More particularly, the feedforward digital signal is provided to the PWM controller 1050 from an output of the signal limiter block 1146, through a signal path 1043. In Figure 7, such a signal path is also indicated as 1043. [0121] As also described in reference to Figure 6, the digital signal from the output of the signal limiter block 1146 is also provided to the DAC 1044 through the DSM block 1148 and the DEM block 1150. An analog signal from the output of the DAC 1044 is utilized as a reference audio signal for the above-referenced closed-loop of the amplifier block 1022 of Figure 7. [0122] Referring to Figure 7, it is noted that the feedforward digital audio signal that is provided to the PWM controller 1050 (through the path 1043) is utilized to create most of a signal that determines pulse modulation for the H-bridge driver 1052. More particularly, the PWM controller 1050 is shown to include a pulse generator 1166 that generates control signals HPP_ctrl, HOR_ctrl, HPN_ctrl based mostly on the feedforward digital audio signal provided through the path 1043 and a mixer 1164. The control signal HPP_ctrl is provided to a ZOR HPP driver 1170 to generate an analog audio signal HPP when in a ZOR mode; the control signal HOR_ctrl is provided to an HOR driver 1172 to generate an analog audio signal HPP when in an HOR mode; and the control signal HPN_ctrl is provided to a ZOR/HOR HPN driver 1174 to generate an analog audio signal HPN when in either of the ZOR and HOR modes. The analog signals HPP and HPN are shown to drive a speaker 1004 to generate sound. [0123] Referring to Figure 7, it is also noted that an error signal generated by the closed-loop is utilized to develop the remainder of the signal that determines pulse modulation for the H-bridge driver 1052. Such an error signal is shown to be provided to the pulse generator 1166 from a successive approximation register (SAR) ADC 1048 through a digital loop filter (DLF) 1162 and the mixer 1164. Such an error signal resulting from the closed-loop provides improved audio performance of the amplifier circuit. Examples related to such a closed-loop are described herein in greater detail. [0124] In the example of Figure 7, the H-bridge driver 1052 is shown to include a ZOR HPP driver 1170, an HOR driver 1172 and a ZOR/HOR HPN driver 1174, and a resistance network 1080 (also 1080 in Figure 6) is shown to include a sense resistance (Rs), HOR feedback resistances (Rh1, Rh2) and ZOR feedback resistances (Rz_p, Rz_n). With such drivers, a ZOR mode can be implemented so that the ZOR HPP (1170) and ZOR/HOR HPN (1174) drivers directly drive the speaker 1004 (with signals through HPP and HPN nodes), and the ZOR feedback resistances (Rz_p, Rz_n) of the resistance network 1080 directly sense the voltage across the speaker load (HPP and HPN). Accordingly, the ZOR HPP (1170) and ZOR/HOR HPN (1174) drivers are directly connected to the HPP and HPN nodes, and thus the speaker load, during the ZOR mode. [0125] Referring to Figure 7, an HOR mode can be implemented so that the HOR feedback resistances (Rh1, Rh2) sense a voltage across the sense resistance Rs (e.g., an on-chip current sense resistor), where Rs can be adjusted to be same or close to the resistance (RL) of the speaker load. With such a configuration, the closed-loop operation can force the voltage signal across the sense resistance Rs to be representative of the input signal provided to the H-bridge driver 1052. Accordingly, the resulting current through the speaker load causes an output voltage of the H-bridge driver 1052 to be equal to or representative of the input signal provided to the H-bridge driver 1052 times the speaker impedance. [0126] It is noted that during the foregoing HOR mode operation, the ZOR HPP driver 1170 is turned off. It is also noted that the resistance Rs is in series with the HOR driver 1172 and the HPP node. Accordingly, the speaker load is driven through the high impedance of the HPP node. The ZOR/HOR HPN driver 1174 drives the other side of the speaker load. [0127] It is noted that the foregoing HOR mode can be utilized to address a low- level electromagnetic-coupled noise problem. For example, the high output resistance mode can attenuate the noise at the speaker load. More particularly, in the HOR mode, the speaker load is driven in a high-output-impedance mode as a current source mode output instead of a voltage source mode output. Accordingly, the H-bridge driver 1052 forces a high-fidelity audio current waveform into the speaker load, regardless of load impedance, nonlinearities and/or noise injections. [0128] The foregoing HOR mode can be calibrated an adjustment of the sense resistance Rs and a digital HOR calibration gain factor applied in one or more calibration blocks. In some embodiments, such gain calibration can be achieved periodically to equal the gain in the ZOR mode. Examples related to such gain calibration are described herein in greater detail. [0129] In the example of Figure 7, the PWM amplifier 1022 utilizes modulation frequency and supply voltage scheme to provide high performance and efficient operation of the H-bridge driver 1052. The modulation frequency can have a value of several MHz for a pulse width update rate to provide an update period. Such an update period is divided into N ticks utilizing a clock signal. An output pulse width can range from 1 to M times the tick width. Accordingly, the output pulse width can have a minimum value of 1 x (tick width) and a maximum value of M x (tick width). [0130] Referring to Figure 7, the foregoing supply voltage scheme can include utilization of multiple supply voltages for the output pulses. For example, voltages VBAT > VDD_A > VDD_B > VDD_D > VDD_E can be provided to an H-bridge driver supply circuit 1160 for the output voltages. Such multiple voltages provided to the output pulses can provide improved efficiency during operations at different signal levels. For example, for lower level signals, lower voltages can be utilized; and for higher level signals, higher voltages can be utilized. To achieve such functionality, the H-bridge driver 1052 can include multiple driver transistors configured to allow dynamic switching of voltages to any of the multiple values based on encoded control signals from the PWM controller 1050. [0131] For example, and referring to Figure 7, the ZOR HPP and ZOR/HOR HPN drivers (1170, 1174) are utilized for ZOR mode, and the HOR and ZOR/HOR HPN drivers (1172, 1174) are utilized for HOR mode. Depending on the mode of operation (ZOR or HOR), amplitude of input signal and PWM encoding rules, the PWM controller 1050 connects the respective drivers to one of the available supplies provided through the H-bridge driver supply circuit 1160 to create a zero, positive or negative differential drive across the output load nodes HPP and HPN. [0132] As described above, the PWM amplifier 1022 utilizes modulation frequency such that a pulse width update is provided during a corresponding period. Thus, the PWM controller 1050 can select the supply voltages and pulse width for the respective drivers. For example, the PWM controller 1050 can select the largest pulse width and lowest supply possible during each update period. Such selections of pulse width and supply voltage level can result in the lowest or reduced PWM quantization error and best or improved power efficiency. [0133] Configured in the foregoing manner, the output of the H-bridge driver 1052 can be taken from the differential voltage on the HPP and HPN nodes and directly drive the speaker 1004. It is noted that such an output differs from traditional class D amplifiers in that the foregoing output appears as high frequency, multi-voltage-level stepping/switching activity. Such voltage stepping activity is a notable property of the architecture of the PWM amplifier 1022. For the ZOR mode of operation and for audio signals such as sine waves, the voltage level stepping can follow the envelope of the audio signal. In the HOR mode of operation, the HPP and HPN single-ended output switching appears different than in the ZOR mode. The behavior of the signal on the HPP and HPN nodes can depend on the polarity of the output signal. When measuring the HPP and HPN nodes single-ended to ground, during parts of the output signal cycle, the HPP and HPN waveforms may not resemble the audio envelope in the same way as in the ZOR mode. Such a difference can result from the HOR mode’s selection of HPP node voltage that forces the PWM controller 1050 to produce switching behavior that holds the HPP node high. Therefore, the HPP node is held high for a significant part of the waveform cycle while the HPN node is switching. [0134] In the PWM amplifier 1022 of Figure 7, the closed-loop can be configured and operated as follows. As described herein, such a closed-loop can provide an error signal that is utilized for development of a signal that determines pulse modulation for the H-bridge driver 1052, thereby providing improved audio performance of the amplifier circuit. [0135] Referring to Figure 7, the outputs HPP and HPN of the H-bridge driver 1052 can be fed back to the summing nodes 1081, 1083 through the resistance network 1080. More particularly, the output node HPP is shown to be coupled to the summing node 1081 through a resistance Rz_p and a respective mixer also being provided with a ZOR mode signal as an input. Thus, the output of the mixer is shown to be added with a respective reference output of the DAC 1044 at the summing node 1081; and the summed signal is shown to be provided to the loop filter 1046. Similarly, the output node HPN is shown to be coupled to the summing node 1083 through a resistance Rz_n and a respective mixer also being provided with a ZOR mode signal as an input, such that the output of the mixer is shown to be added with a respective reference output of the DAC 1044 at the summing node 1083; and the summed signal is shown to be provided to the loop filter 1046. [0136] Configured in the foregoing manner, the loop filter 1046 is provided with a signal representative of a differential error between the outputs (HPP, HPN) of the H- bridge driver 1052 and the reference signal provided by the DAC 1044. In the example of Figure 7, the each of the summing nodes 1081, 1083 is shown to be provided with a signal from the common-mode limiting (CML) amplifier 1082. Such signals from the CML amplifier 1082 can be utilized to limit the input common-mode voltage of the loop filter 1046. [0137] In the example of Figure 7, the loop filter 1046 can include a 5th order high gain loop filter to provide an output to a low-power, high-speed SAR ADC 1048 to digitize the loop filter output. The digitized output of the SAR ADC 1048 is shown to be provided to the PWM controller 1050, where it is utilized by the PWM controller 1050 along with the feedforward signal (provided through the path 1043) to generate PWM control signals for the H-bridge driver 1052. [0138] Referring to Figure 7, it is noted that in the foregoing closed-loop, without any compensation, an inductance of the speaker’s driver element can lead to significant differences in the open-loop frequency response at high frequencies (e.g., greater than 100 KHz) between the HOR and ZOR modes. Such an effect is due to the current- mode drive of the sense resistance working into the frequency dependent impedance of the speaker inductance during the HOR mode of operation. [0139] In the closed-loop circuit of Figure 7, the loop includes the loop filter 1046, SAR ADC 1048, PWM controller 1050, H-bridge driver 1052 and resistance network 1080. In addition to such components, a digital loop filter (DLF) 1162 can be provided to provide compensation for loop stability in situations where processing delays are present. In some embodiments, such a DLF can be configured to provide compensation by insertion of a programmable digital filter that includes parallel arrangement of finite impulse response (FIR) and infinite impulse response (IIR) sections, between the SAR ADC 1048 and the normal input location (mixer 1164 in Figure 7). Such a DLF can be configured to provide a response that includes phase compensation in response to the effect of the inductor in the HOR mode, as well as shaping of one or more characteristics of the closed-loop. [0140] As described herein, when the PWM amplifier 1022 of Figure 7 is in ZOR mode, the gain is determined by the resistances of the resistance network 1080 working against the DAC (1044) output current. The feedback resistances (Rz_p, Rz_n) sense the voltage across the HPP and HPN nodes, and provides feedback to the loop filter inputs. The closed-loop with such a feedback can force the output of the PWM amplifier 1022 to be adjusted to equal or approximately equal the digital input with a net gain (e.g., G = 1 such that a 0 dBFS input produces a 0 dBv output). [0141] In HOR mode, however, the gain is determined differently, since the HOR mode utilizes a current-mode output where the signal current is produced across the sense resistance (Rs) and forced through the load resistance (Rload) of the speaker (1004 in Figure 7). The HOR feedback resistances (Rh1, Rh2) sense the voltage across the sense resistance Rs, and such a sensed voltage works against the DAC output current. The closed-loop with such a feedback can force the output current gain of the PWM amplifier 1022 to be adjusted to be G = 1/Rs. If there is no further adjustment, then the net end-to-end gain in the HOR mode would be G = Rload/Rs. If Rs and Rload are not equal to each other, then the HOR gain will not be equal to the gain in ZOR mode (G = 1). To address such an effect, an audio amplifier circuit as described herein can configured to include an HOR gain calibration functionality utilizing, for example, adjustment of the sense resistance and a digital gain term to make the gain in HOR mode equal to or approximately equal to the gain in the ZOR mode. Examples related to such a gain calibration functionality are described herein in greater detail. [0142] Figure 8 shows a block diagram of a digital logic circuit block 1020 that is a more specific example of the digital logic circuit block 1022 of Figure 5, implemented to operate with the H-bridge driver 1052 of Figure 7 to provide functionalities including mode switching between HOR and ZOR modes. Such mode switching can be achieved as follows. [0143] It is noted that the audio amplifier circuit as described herein can provide dynamic switching between HOR and ZOR modes. Such mode-switching operation can include switching of the feedback resistance configurations of the resistance network (1080 in Figure 8) between the output nodes (HPP, HPN) to the loop filter block (1046). Such mode-switching operation can be achieved in a dynamic manner with low audio artifacts. However, when switching between modes, because of the complex impedance of the speaker driver element and the current-mode operation in the HOR mode, the end-to-end frequency response of the system may change. If such a difference in frequency response is not compensated, the change may result in audible artifacts. To compensate for the change in frequency response, the audio amplifier circuit as described herein can include a digital EQ filter to allow compensation of the frequency response difference between the two modes. [0144] In addition, to minimize the audible artifacts during HOR/ZOR transitions, the audio amplifier circuit as described herein can include a number of features. For example, the resistance network 1080 can be controlled to provide stepped output resistance Rout. In another example, a HOR/ZOR EQ block 1142 can be configured to operate with the stepped Rout values. In yet another example, a HOR/ZOR state control block 1062 can be provided and configured to control the HOR/ZOR transitions. [0145] It is noted that an abrupt transition in the output resistance Rout seen by the speaker driver during HOR/ZOR transitions can cause a sufficiently large phase shift to be audible. To reduce or eliminate such audible artifacts, an amplifier equivalent Rout can be made to transition more gradually by moving through a series of Rout steps (e.g., six Rout steps) during a transition between HOR and ZOR modes. A set of particular Rout step values can be selected by selected values of feedback resistances Rh and Rz of the resistance network 1080. Such Rout step values can be selected to produce approximately equal phase artifacts error per step. Further, time duration per step can be programmable over a modest range. Given a non-linear relationship between phase error and step size, Rout stepping as described herein can provide a significant impact on the reduction in the audibility of the artifacts. [0146] As described in reference to Figure 6, an HOR/ZOR EQ block 1142 can be provided as part of the digital audio path 1042. Figure 8 shows that such an HOR/ZOR EQ block (also 1142) can be implemented to operate with the foregoing Rout stepping functionality. [0147] Referring to Figure 8, the HOR/ZOR EQ block 1142 is shown to be driven by the output of the PDM LPF block 1140. The HOR/ZOR EQ block 1142 can be configured to provide filtering to compensate for the difference between the HOR and ZOR mode frequency responses driving the speaker transducer. The HOR/ZOR EQ block 1142 is shown to include an EQ filter bank, gain compute block and cross-fading functionality. [0148] More particularly, the EQ filter bank is shown to include three parallel filter sections 1200 (Spare BQ), 1202 (Shelving) and 1204 (Bandpass) configured to compensate the frequency response in the speaker transducer. The filter section 1200 (Spare BQ) can be implemented as a low frequency 2nd order (biquad) bandpass filter section (e.g., up to 1 KHz). The filter section 1202 (Shelving) can be implemented as a 4th order finite impulse response (FIR) shelving filter. The filter 1204 (Bandpass) can be implemented as a 2nd order general purpose biquad filter. [0149] Referring to Figure 8, the EQ block 1142 can be configured to optionally provide filtering to compensate for the difference between the HOR and ZOR mode frequency responses driving the speaker transducer. In addition to the foregoing EQ filter bank and the cross-fading functionality, the EQ block 1142 can also include a gain compute block 1212. Figure 9 shows a more specific configuration of such a gain compute block. [0150] Referring to Figures 8 and 9, the EQ block 1142 is shown to provide tapered in and out via a crossfading mixing structure of gains G1 and G2 (through mixers 1208, 1210) and an output adder 1214. [0151] More particularly, gain G1 is shown to be associated with mixing of an unfiltered output of the PDM LPF block 1140 with a non-EQ gain signal from the gain compute block 1212 at the mixer 1208, and gain G2 is shown to be associated with mixing of a summed filtered signal with an EQ gain signal from the gain compute block 1212 at the mixer 1210. The foregoing summed filtered signal is shown to be obtained by outputs of the filter sections 1200, 1202, 1204 being added by an adder 1206. The input to each of the filter sections 1200 (Spare BQ) and the filter section 1202 (Shelving) is shown to be provided from the output of the PDM LPF block 1140, and the input to the filter section 1204 (Bandpass) is shown to be provided from the input of the PDM LPF block 1140. [0152] Referring to Figures 8 and 9, the gain value G1 is associated with a non- filtered signal, and the gain value G2 is associated with a filtered signal. The gains G1 and G2 can be values ranging from 0 to 1, where G1 + G2 = 1, and in the example context of Rout having six steps, each of G1 and G2 can have six discrete step values of 0, 0.2, 0.4, 0.6, 0.8 and 1. As described herein, such gain values can be stepped with the Rout stepping of the audio amplifier circuit. [0153] Referring to Figure 9, the gain compute block 1212 is shown to be configured to generate the non-EQ gain signal (to the mixer 1208 in Figure 8) and the EQ gain signal (to the mixer 1210) based on a number of inputs. For example, the gain compute block 1212 can handle slowly changing gain parameters such as HOR/ZOR gain, user gain, HOR calibration gain, and EQ biquad gain. Based on some or all of such inputs, and depending on the operating mode (ZOR or HOR), the gain compute block 1212 can compute net EQ path gain and non-EQ path gain values and provide such gain values as outputs. [0154] More particularly, the user gain is shown to be processed through a gain ramp 1220 and provided to a mode gain multiplexer 1222 that also receives a HOR mode signal. The mode gain multiplexer 1222 is shown to generate ZOR gain and HOR gain and provide such outputs to a multiplexer 1226, with the latter being mixed with a HOR calibration gain value by a mixer 1224. The multiplexer 1226 is shown to provide the non-EQ gain and EQ gain values based on the ZOR gain and HOR gain values, along with an EQ select input. The EQ gain value is shown to result from mixing of the respective output of the multiplexer 1226 with the EQ biquad gain by a mixer 1228. [0155] Configured in the foregoing manner, the gain compute block 1212 can provide some or all of the following functionalities: provide a gain stage for digital audio gain adjustment, provide an amplifier state initiated gain ramp-up after start of audio, provide an amplifier initiated gain ramp-down before shutdown of audio, provide a gain stage for HOR/ZOR fine gain calibration (e.g., HOR calibration gain) where the fine gain calibration can be applied in all HOR modes (full and partial), provide gain control for a programmable ramp time, and provide a test mode programmable volume gain register to mute gain block with a variable attenuation step size to provide a desired dynamic range. [0156] Configured as described above in reference to Figures 8 and 9, the HOR/ZOR EQ block 1142 can provide some or all of the following functionalities: enabling or bypassing of EQ functionality, compensating for transducer impedance vs frequency with a multi-section filter, switching in and out of the audio path with minimal or reduced audio artifacts, tracking of output resistance Rout, programmable filter coefficients, minimized or reduced latency, and provide EQ filtering active for HOR or ZOR mode and off for the other. [0157] Figure 8 also shows an HOR/ZOR state control block 1062 that can be a more specific example of the HOR/ZOR state control block 1062 of Figures 5 and 6. In the example of Figure 8, the HOR/ZOR state control block 1062 can determine when to switch between HOR and ZOR modes by observing the audio signal path. Such a switching can be controlled so that audible artifacts due to switching are minimized or reduced. In some embodiments, HOR/ZOR switching can be configured to maximize or increase time in the ZOR mode for efficiency, but prioritize HOR mode when audio signal is low in order to minimize or reduce injected interference. The HOR/ZOR state control block 1062 can include an HOR/ZOR Rout mode control block 1190 that utilizes, for example, psychoacoustic principles, to mask or reduce transient artifacts during mode switching operations. [0158] Referring to Figure 8, the HOR/ZOR state control block 1062 can provide some or all of the following functionalities. First, the audio amplifier circuit can be placed in HOR mode when amplitude of the digital audio signal (e.g., obtained from the input side of the PDM LPF 1140) is low in order to minimize or reduce injected interference. Second, the audio amplifier circuit can be placed in ZOR mode when amplitude of the digital audio signal is high in order to improve efficiency. Third, transition time from ZOR to HOR mode can be made to be within a selected time duration. Fourth, Rout transitions can be made without or reduced audible artifacts. Fifth, HOR/ZOR target mode can be determined by an average audio level. Sixth, HOR/ZOR switching time can be set to be when the transition will be inaudible as determined by a combination of configurable factors such as crest factor, audio signal level being below a threshold value, and time from the last Rout change. Seventh, HOR/ZOR output impedance can have multiple (e.g., 6) steps corresponding to the Rout modes (e.g., Rour0, Rout1, Rout2, Rout3, Rout4, Rout5). Eighth, HOR/ZOR impedance steps can be controlled by moving from current impedance step toward the target impedance step when transitions are determined to be inaudible. Ninth, HOR/ZOR transitions can be programmable to step through discrete output impedances in order to minimize or reduce switching transients (e.g., output impedance step controls being implemented to correspond to output impedance steps of the audio amplifier). Tenth, HOR/ZOR transitions can be independently configured to occur with a minimum or reduced time between switching. Eleventh, HOR/ZOR mode can have a manual override configured by resister access, and such an override can be configured to allow setting of all mode and/or Rout settings. [0159] In the example of Figure 8, switching between HOR and ZOR modes can be achieved as follows. Switching between HOR and ZOR modes can include operations of the resistance network 1080, the HOR/ZOR EQ block 1142, and the HOR/ZOR state control block 1062. [0160] Referring to Figure 8 and the foregoing HOR/ZOR switching functionality, the resistance network 108 can be utilized to provide an Rout stepping functionality as described herein. It is noted that an abrupt transition in Rout seen by the speaker driver during HOR/ZOR transitions can cause a sufficiently large phase shift to be audible. To reduce such audible artifacts, an amplifier equivalent Rout can be made to transition more gradually be moving through a number of Rout steps (e.g., 6 steps) during a transition between HOR and ZOR modes. Such stepped Rout values can be achieved through selection of resistance values for Rh and Rz implemented as, for example, variable resistors. The equivalent Rout steps can be selected to produce approximately equal phase artifact error per step, and the time per step can be programmed over a selected range. Given the non-linear relationship between phase error and step size, Rout stepping functionality can provide a significant impact on the reduction in the audibility of the artifacts during HOR/ZOR transitions. [0161] Referring to Figure 8 and the foregoing HOR/ZOR switching functionality, the HOR/ZOR EQ block 1142 can be configured to provide EQ filtering functionality including EQ filtering functionality for compensation of the difference in frequency responses between HOR and ZOR modes as described herein. The HOR/ZOR EQ block 1142 can be configured to operate with such EQ filtering functionality during the HOR or ZOR mode. In some embodiments, some or all of the EQ block 1142 can be disabled in the HOR mode to save power, and be enable during the ZOR mode if desired or needed. It is noted that if the foregoing Rout stepping functionality is utilized, the EQ filter response can be synchronized to be gradually stepped with a corresponding change in the Rout. [0162] Referring to Figure 8 and the foregoing HOR/ZOR switching functionality, the HOR/ZOR state control block 1062 can be configured to decide when to switch between HOR and ZOR modes by monitoring the audio signal path. For example, audio signal path before and after the PDM LPF block 1140 can be monitored. [0163] Referring to Figure 8, the node on the input side of the PDM LPF block 1140 is shown to be coupled to a decimation circuit 1180 configured decimate the sampled signal by N (e.g., N = 128). The decimated signal is then shown to be provided to a block 1182 for low audio detection, a block 1184 for generating a target mode, and a block 1186 for selecting an Rout step. Outputs of the blocks 1182, 1184, 1186 are shown to be provided to a HOR/ZOR Rout mode control block 1190. Referring to Figure 8, the node on the output side of the PDM LPF block 1140 is shown to be coupled to an audio switch block 1188 that provides its output to the HOR/ZOR Rout mode control block 1190. [0164] Configured in the foregoing manner, the HOR/ZOR state control block 1062 can determine when to switch between HOR and ZOR modes. Such determination can be based on some or all of a number of conditions. For example, an average of the sampled input signal can be obtained and compared to a threshold value. More particularly, a determination of whether the average of the sampled signal is greater than a HOR-to-ZOR threshold value can be made when in HOR mode, or whether the average of the sampled signal is less than a ZOR-to-HOR threshold value can be made when in ZOR mode. In another example, a determination of whether the input signal has a very low level can be made. In yet another example, the input signal can be passed through a high-pass filter, and a peak in such a filtered signal can be compared to a product of an average of the filtered signal and a crest factor. If the peak value is greater than the product, and if the input signal is at or near a zero crossing, a determination can be made to perform a mode-switching operation. [0165] It is noted that the foregoing HOR-to-ZOR threshold value and ZOR-to- HOR threshold value may or may not be different. [0166] For a HOR-to-ZOR transition, determination can be made as to whether the input signal level has crossed a respective threshold level, and whether a favorable transition condition (e.g., high crest factor, higher frequency masking event and a subsequent zero crossing). If so, the HOR-to-ZOR transition can be made to proceed. For a ZOR-to-HOR transition, determination can be made as to whether the input signal level has crossed a respective threshold level or has become sufficiently small, and whether a favorable transition condition (e.g., high crest factor, higher frequency masking event and a subsequent zero crossing). If so, the ZOR-to-HOR transition can be made to proceed. The foregoing transition techniques allow the audio amplifier to operate to deliver full output power in either HOR or ZOR modes, thus enabling the audio amplifier to remain in either mode until a favorable transition condition is present to thereby avoid audible artifacts. [0167] As described herein, HOR mode gain is determined differently than ZOR mode gain. However, it is desirable to operate an audio amplifier circuit as described herein so that a net gain in the HOR mode is equivalent to a net gain in the ZOR mode. In some embodiments, HOR gain can be adjusted so to be equivalent to ZOR gain. In various examples described herein, such a ZOR gain can be considered to have a gain G = 1; thus, HOR gain can be calibrated to also provide a gain G = 1. Such a HOR gain calibration can be achieved as follows. [0168] Figure 10 shows various functional blocks of the audio amplifier circuit 1000 of Figure 5, where such blocks can form an HOR gain calibration sub-system. More particularly, such a sub-system can include a gain calibration block 1070, a gain calibration ADC 1084, an Rout controller 1064, a resistance network 1080, and an HOR/ZOR EQ block 1142. Figure 11 shows a more detailed example of the gain calibration block 1070 of Figure 10. [0169] Referring to Figures 10 and 11, the gain calibration block 1070 can be implemented as a digital block that includes a gain calibration processor 1230 and a gain calibration controller 1238. The gain calibration processor 1230 can be configured to perform gain estimation computation for HOR mode, and based on such gain estimation, desired sense resistance (Rs in Figures 7 and 8) value and digital gain correction value can be determined. The gain calibration controller 1238 can handle overall management of the gain calibration sub-system, including determining when to calibrate and/or determining conditions for a valid calibration. [0170] Referring to Figures 10 and 11, the gain calibration ADC 1084 can be implemented as an analog block that digitizes the differential amplifier output HPP-HPN during a calibration cycle to use by the foregoing gain calibration processor 1230. The gain calibration ADC 1084 can be configured (e.g., with delta-sigma modulation) to handle large audio signals at the output (HPP, HPN) and have a sufficiently large dynamic range to detect the relatively lower amplitude calibration tone signal. [0171] Referring to Figure 11, the gain calibration processor 1230 is shown to include a calibration tone generator 1232 configured to generate an ultrasonic calibration tone (Cal. tone) which is mixed into the digital audio stream with the mixer 1144 before the signal limiter block 1146. The tone generator 1232 can also be configured to provide programmable frequency and amplitude functionalities. In some embodiments, the tone generator 1232 can produce a sinusoidal output modulated with, for example, a 2nd order cascaded integrator-comb (CIC) filtered pulse to prevent audible energy during turning on and off of the tone generator 1232. [0172] Referring to Figures 10 and 11, the Rout controller 1064 can be implemented as a digital block that performs computations to determine and control the sense resistance (Rs) setting in the analog resistance network 1080. The Rout controller 1064 can also perform computations to determine a digital fine gain value that is provided to the HOR/ZOR EQ block 1142 for use in a fine gain adjustment. [0173] Referring to Figures 10 and 8, the resistance network 1080 can be implemented as an analog block that includes a programmable sense resistance (Rs) network, and programmable ZOR and HOR Rout mode feedback resistances (Rz and Rh). Such a resistance network is shown to be controlled by the Rout controller 1064. [0174] Referring to Figures 10 and 11, and as described above, the HOR/ZOR EQ block 1142 and its gain compute block (1212 in Figures 8 and 9) can provide a gain multiplier functionality where HOR digital calibration gain is applied. Such an application of the HOR digital calibration gain can be based on a control signal (HOR Cal fine gain) provided by the Rout controller 1064. [0175] Configured in the foregoing manner, the gain calibration processor 1230 can compute a gain mismatch between HOR and ZOR modes by introducing a calibration tone (e.g., an ultrasonic tone at ~25 KHz) into the digital audio stream at the mixer 1144 before the signal limiter block 1146. The digital audio stream with the calibration tone mixed therein is passed through the signal limiter block 1146. At the output of the signal limiter block 1146, the digital audio stream is routed through path 1043 to the PWM controller (1050 in Figure 8) to be processed and amplified by the H- bridge driver 1052 to provide an output at HPP and HPN. Also at the output of the signal limiter block 1146, the digital audio stream is obtained for the gain calibration processor 1230 as a reference signal. Thus, the magnitude and phase of the output signal at the output (HPP, HPN) can be compared relative to the magnitude and phase of the reference signal. [0176] To achieve the foregoing comparison of the output signal (analog signal) with the reference signal (digital signal), the gain calibration ADC 1084 can sample the output voltage across the load (HPP-HPN) and provide a delta-sigma ADC output to the gain calibration processor 1230. Measurement and computation of the HOR and ZOR gains can be performed by the gain calibration processor 1230 (e.g., with a gain compute block 1236) utilizing an estimation algorithm where the reference signal X and the digitized output signal Y are downconverted with a tone at the same frequency as the calibration tone (e.g., 25 KHz). The downconverted signals X and Y can be filtered (e.g., single-bin fast Fourier transform (FFT) with a discrete Fourier transform (DFT) block 1234) to provide respective complex downconverted values x and y. A ratio of the two complex downconverted values can be obtained, where Ratio = y/x. It is noted that complex values can be utilized so that the load inductance does not significantly affect the gain calculation; however, the real component of the Ratio is utilized. [0177] The foregoing Ratio = y/x is an expression of a transfer function gain from the digital input to the amplifier output, and can be designed to be tolerant to out- of-band interference. Ratio can be computed for each of the HOR and ZOR modes, such that Ratio(HOR) = y/x in the HOR mode, and Ratio(ZOR) = y/x in the ZOR mode. [0178] The calibration processor 1230 can then compute another ratio Relative_HOR_gain = Ratio(HOR)/Ratio(ZOR) which is representative of the HOR gain relative to the ZOR gain. Ideally, this ratio Relative_HOR_gain has a value of 1. [0179] Referring to Figure 11, the computed Relative_HOR_gain value is shown to be provided to the Rout control block 1064 by the gain calibration controller 1238. Based on such a computed Relative_HOR_gain value, the Rout control block 1064 can determine an adjustment to the sense resistance (Rs) and a fine gain (HOR Cal fine gain in Figure 10) control signal to be applied to the digital path by the gain compute block 1212 of the HOR/ZOR EQ block 1142. [0180] More particularly, the Rout control block 1064 can obtain the Relative_HOR_gain value and perform computations to determine how to change the sense resistance (Rs) relative to its present setting. Based on the change it makes to the sense resistance (Rs) setting, the Rout control block 1064 can compute the digital fine gain adjustment needed to make the Relative_HOR_gain value to be 1. Examples of Combinations of Features [0181] For the purpose of description, Figures 12 to 15 relate to first feature or Feature 1; Figures 16 to 18 relate to second feature or Feature 2; Figures 19 to 23 relate to third feature or Feature 3; Figures 24 to 26 relate to fourth feature or Feature 4; Figures 27 to 29 relate to fifth feature or Feature 5; Figures 30 to 33 relate to sixth feature or Feature 6; Figures 34 and 35 relate to seventh feature or Feature 7; Figures 36 and 37 relate to eighth feature or Feature 8; Figures 38 to 40 relate to ninth feature or Feature 9; and Figures 41 to 43 relate to tenth feature or Feature 10. [0182] In some embodiments, each of the foregoing ten features can be implemented in one or more blocks of an audio amplifier circuit, such as the audio amplifier circuit 1000 of Figure 5. Thus, in some embodiments, a combination of two or more of the foregoing ten features can also be implemented in one or more blocks of an audio amplifier circuit, such as the audio amplifier circuit 1000 of Figure 5. In some embodiments, such an audio amplifier circuit can be implemented in a system, a device, or some combination thereof. [0183] In some embodiments, a combination of features can include at least Feature 1 and Feature 2. In some embodiments, such combination can further include some or all of the remaining eight features. [0184] In some embodiments, a combination of features can include at least Feature 1 and Feature 3. In some embodiments, such combination can further include some or all of the remaining eight features. [0185] In some embodiments, a combination of features can include at least Feature 1 and Feature 4. In some embodiments, such combination can further include some or all of the remaining eight features. [0186] In some embodiments, a combination of features can include at least Feature 1 and Feature 5. In some embodiments, such combination can further include some or all of the remaining eight features. [0187] In some embodiments, a combination of features can include at least Feature 1 and Feature 6. In some embodiments, such combination can further include some or all of the remaining eight features. [0188] In some embodiments, a combination of features can include at least Feature 1 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0189] In some embodiments, a combination of features can include at least Feature 1 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0190] In some embodiments, a combination of features can include at least Feature 1 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0191] In some embodiments, a combination of features can include at least Feature 1 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0192] In some embodiments, a combination of features can include at least Feature 2 and Feature 3. In some embodiments, such combination can further include some or all of the remaining eight features. [0193] In some embodiments, a combination of features can include at least Feature 2 and Feature 4. In some embodiments, such combination can further include some or all of the remaining eight features. [0194] In some embodiments, a combination of features can include at least Feature 2 and Feature 5. In some embodiments, such combination can further include some or all of the remaining eight features. [0195] In some embodiments, a combination of features can include at least Feature 2 and Feature 6. In some embodiments, such combination can further include some or all of the remaining eight features. [0196] In some embodiments, a combination of features can include at least Feature 2 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0197] In some embodiments, a combination of features can include at least Feature 2 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0198] In some embodiments, a combination of features can include at least Feature 2 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0199] In some embodiments, a combination of features can include at least Feature 2 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0200] In some embodiments, a combination of features can include at least Feature 3 and Feature 4. In some embodiments, such combination can further include some or all of the remaining eight features. [0201] In some embodiments, a combination of features can include at least Feature 3 and Feature 5. In some embodiments, such combination can further include some or all of the remaining eight features. [0202] In some embodiments, a combination of features can include at least Feature 3 and Feature 6. In some embodiments, such combination can further include some or all of the remaining eight features. [0203] In some embodiments, a combination of features can include at least Feature 3 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0204] In some embodiments, a combination of features can include at least Feature 3 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0205] In some embodiments, a combination of features can include at least Feature 3 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0206] In some embodiments, a combination of features can include at least Feature 3 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0207] In some embodiments, a combination of features can include at least Feature 4 and Feature 5. In some embodiments, such combination can further include some or all of the remaining eight features. [0208] In some embodiments, a combination of features can include at least Feature 4 and Feature 6. In some embodiments, such combination can further include some or all of the remaining eight features. [0209] In some embodiments, a combination of features can include at least Feature 4 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0210] In some embodiments, a combination of features can include at least Feature 4 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0211] In some embodiments, a combination of features can include at least Feature 4 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0212] In some embodiments, a combination of features can include at least Feature 4 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0213] In some embodiments, a combination of features can include at least Feature 5 and Feature 6. In some embodiments, such combination can further include some or all of the remaining eight features. [0214] In some embodiments, a combination of features can include at least Feature 5 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0215] In some embodiments, a combination of features can include at least Feature 5 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0216] In some embodiments, a combination of features can include at least Feature 5 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0217] In some embodiments, a combination of features can include at least Feature 5 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0218] In some embodiments, a combination of features can include at least Feature 6 and Feature 7. In some embodiments, such combination can further include some or all of the remaining eight features. [0219] In some embodiments, a combination of features can include at least Feature 6 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0220] In some embodiments, a combination of features can include at least Feature 6 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0221] In some embodiments, a combination of features can include at least Feature 6 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0222] In some embodiments, a combination of features can include at least Feature 7 and Feature 8. In some embodiments, such combination can further include some or all of the remaining eight features. [0223] In some embodiments, a combination of features can include at least Feature 7 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0224] In some embodiments, a combination of features can include at least Feature 7 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0225] In some embodiments, a combination of features can include at least Feature 8 and Feature 9. In some embodiments, such combination can further include some or all of the remaining eight features. [0226] In some embodiments, a combination of features can include at least Feature 8 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. [0227] In some embodiments, a combination of features can include at least Feature 9 and Feature 10. In some embodiments, such combination can further include some or all of the remaining eight features. Feature 1 [0228] As described herein, the audio amplifier circuit 1000 of Figure 5 can be configured to operate in one of two modes of operation (a high output resistance (HOR) mode and a zero output resistance (ZOR) mode) to provide desired combinations of optimal performance and power-consumption. Accordingly, such an audio amplifier circuit can switch between the two modes depending on the desired tradeoff between performance and power-consumption. [0229] During the foregoing switching between the two modes, audio artifacts (some of which may be audible) can arise from a difference in gain of the amplifier between the two modes. Such a difference in gain can result from differences in operating circuitry between the two modes, as well as other factors such as temperature variations, circuit performance variations, and/or chip-to-chip variations. [0230] Figure 12 shows a block diagram of a gain calibration architecture 100 that is similar to the examples of Figures 10 and 11. More particularly, in Figure 12, the gain calibration architecture 100 is shown to include an output signal (at an output node 116) of an H-bridge driver 1052 being sampled by a gain calibration ADC 1084, and such an ADC is shown to provide a digitized signal representative of the output signal to a gain calibration block 1070. As described herein, the foregoing output signal results from amplification of a feedforward digital signal provided to a PWM controller 1050 from a node 114 in a digital audio path 1042, such that the PWM controller 1050 provides an appropriate signals to drive the H-bridge driver 1052 to thereby generate the output signal. [0231] As shown in Figure 12, the gain calibration block 1070 is shown to be also provided with a digital signal from the node 114. Accordingly, the digital signal from such a node of the digital audio path 1042 can be considered to be an input digital signal for the PWM amplifier 1022. [0232] As described herein, and also shown in Figure 12, the gain calibration block 1070 is shown to provide a calibration tone (Cal tone) to a mixer 1144, such that the input digital signal at the node 114 includes the calibration tone. Such a calibration tone can be, for example, an ultrasonic tone not audible to a listener. [0233] As described herein, and also shown in Figure 12, the gain calibration block 1070 is shown to provide a control signal to a HOR/ZOR EQ block 1142 to adjust the input digital signal based on a gain calibration computation determined by the gain calibration block 1070. The HOR/ZOR EQ block 1142 can then provide a gain-adjusted input digital signal to the input node 114 through the mixer 1144. [0234] In the example of Figure 12, the gain calibration block 1070 samples both of the input signal (from the node 114) and the output signal (from the node 116). It is noted that if only an output signal is sampled by a gain calibration scheme, it is possible to measure the output signal at the frequency of a calibration tone signal for each of HOR and ZOR modes, thereby allowing determination of the difference in the levels of the output signals between the two modes. However, such a scheme relies on an assumption that the input signal being amplified does not include any of content in the frequency of the calibration tone signal. If the input signal has any significant energy at or around the frequency of the calibration tone signal, such portion of the input signal will affect the output level too, thereby making the comparison of signal levels between the two modes meaningless or less useful. [0235] Figure 13 shows that in some embodiments, the gain calibration architecture 100 of Figure 12 can be implemented as a more specific example architecture 100. In Figure 13, the gain calibration architecture 100 is shown to include a gain calibration block generally indicated as 1070. Such a gain calibration block is shown to sample an input digital signal at an input node 114 for a PWM amplifier 1022 and an output signal at an output node 116 of the PWM amplifier 1022. In Figure 13, the input node 114 is shown to be after a signal limiter 1146, similar to the example of Figures 10 and 11. [0236] As also described in reference to Figures 10 and 11, and as also shown in Figure 13, a calibration tone (Cal tone) 122 is shown to be generated by the gain calibration block 1070 and provided to a mixer 1144 where the calibration tone is mixed with an input digital signal. As described herein, such a calibration tone can be, for example, an ultrasonic tone having a frequency of approximately 25 KHz. [0237] Referring to Figure 13, the gain calibration block 1070 can be configured to compute a gain mismatch between HOR and ZOR modes by injecting the ultrasonic calibration tone 122 into the digital audio stream and measuring its relative magnitude and phase at the output 116 of the amplifier 1022 (with respect to the input 114 of the amplifier 1022). As shown in Figure 12, a calibration ADC 1084 samples the output voltage across the load. As shown in Figure 13, the input digital signal can be sampled as a reference measurement at the input 114 of the amplifier 1022. [0238] In some embodiments, for gain calibration purpose, signal energy near the tone frequency can be removed or sufficiently reduced for the input digital signal (without the calibration tone) and the output signal (without the calibration tone), so that such signal energy does not affect gain ratios when calibration tone is utilized. For example, a demodulated calibration ADC output can be divided by a demodulated reference (input) signal to reject the host audio energy that may be present near the tone frequency. [0239] In some embodiments, measurement and computation of relative HOR mode gain can be implemented inside the gain calibration block 1070 utilizing an algorithm disclosed herein. For example, a measurement can be triggered on detection of a ‘gcc_start_cal’ pulse from a gain calibration controller (GCC) block (1238 in Figure 11). A relative HOR gain computed in the gain calibration block 1070 can be used by a resistance control block (1064 in Figure 11) to apply a gain adjustment via a coarse gain (e.g., applied in the analog path) and a fine gain (e.g., applied in the digital path). [0240] Referring to Figure 13, the example algorithm can include an ultrasonic calibration tone (Cal tone having a frequency ^ _^ ) being injected in the digital audio path. A frequency response of the analog subsystem associated with the amplifier 1022 and the ADC (1084 in Figure 12) can be estimated by taking the ratio of a discrete Fourier transform (DFT) of its output to that of its input to provide a transfer function of where !^^ _^ ^ and "^^ _^ ^ are representative of the output and input, respectively. With the analog subsystem being represented by a lumped system model ^ ^{^^^^^} ^ _^^^ ^^ _^ ^^ _^^ ^^ _^ ^, the output can be represented as ! ^{^} ^ _^ ^{^} = and the input can be represented as "^^ _^ ^ = ^ ^{^^^^^^} "^^ _^ ^, to thereby arrive at the expression for the ratio ^^^ _^ ^ on the right side of Equation 1. [0241] In some embodiments, sampling of the input and output signals at the calibration tone frequency (^ _^ ) can be achieved by a discrete Fourier transform (DFT) of each of the input and output signals at a single frequency which coincides substantially with the calibration tone frequency (^ _^ ). In Figure 13, such a single-bin DFT is indicated as 115 for the input signal from the input node 114, and as 117 for the output signal from the output node 116. [0242] In some embodiments, each of the single-bin DFTs (117, 127) can be implemented to include a lowpass filter that is provided with a product of the respective signal and a complex sinusoid having the calibration tone frequency (^ _^ ). In the example of Figure 13, the single-bin DFT (117) sampling of the input signal is shown to be achieved by providing a sampling path, from the input node 114, having a path delay (indicated as 111), such that the time-delayed input signal is multiplied with the complex sinusoid (^ ^{^^^^#} ) by a multiplier 113. The product from the multiplier 113 is shown to be provided to a lowpass filter 115. Similarly, the single-bin DFT (127) sampling of the output signal is shown to be achieved by providing a sampling path, from the output node 116, such that the time-delayed output signal is multiplied with the complex sinusoid by a multiplier 123. The product from the multiplier 123 is shown to be provided to a lowpass filter 125. [0243] Figure 13 shows that in some embodiments, each of the lowpass filters 115, 125 can be implemented as a cascaded integrator comb (CIC) filter such as a 3rd- order CIC (CIC3) filter. Examples related to such CIC filters are described herein in greater detail. [0244] In the example of Figure 13, the lowpass filter 115 provides a single-bin DFT signal "^^ _^ ^ representative of the output signal, and the lowpass filter 125 provides a single-bin DFT signal !^^ _^ ^ representative of the input signal. Such signals from the respective lowpass filters 115, 117 are shown to be provided to a block 131 that computes a ratio ^^^ _^ ^ to provide a transfer function ^ ^{^} _^^^ ^^ _^ ^. [0245] Referring to Figure 13, the transfer function ^ ^{^} _^^^ ^{^} ^ _^ ^{^} can be obtained for each of the HOR and ZOR modes as ^ ^{^} _^$% ^{^} ^ _^ ^{^} and ^ ^{^} _&$% ^{^} ^ _^ ^{^} , respectively, and such transfer functions (^ ^{^} _^$% ^{^} ^ _^ ^{^} and ^ ^{^} _&$% ^{^} ^ _^ ^{^} ) can be compared to estimate a relative gain difference between the two modes. For example, a ratio of (^ ^{^} _^$% ^^ _^ ^ and obtained, such that Gain = ^ ^{^} _^$% ^^ _^ ^/^ ^{^} _&$% ^^ _^ ^. [0246] Figure 13 shows that in some embodiments, the real part of the ratio of the transfer function in the two modes can be obtained, where such a real part represents the DC gain ratio between the two modes. In Figure 13, such a real part is indicated as Re(A/B), where A/B is the foregoing gain ^ ^{^} _^$% ^^ _^ ^/^ ^{^} _&$% ^^ _^ ^. It is noted that the imaginary part of the complex ratio ^ ^{^} _^$% ^{^} ^ _^ ^{^} /^ ^{^} _&$% ^{^} ^ _^ ^{^} depends on an inductance of the load and can be frequency dependent. [0247] In some embodiments, the ratio of the two gains ('()* = ^{^^} _+,- ^{^^} _^ ^{^ ^^} _.,- ^{^^} _^ ^{^} ) can be provided as an output for a coarse gain adjustment by the resistance control block (1080 in Figure 10) and a fine gain adjustment by the HOR/ZOR EQ block (1142 in Figure 10). [0248] In some embodiments, in the foregoing gain calibration technique, each of the lowpass filters 115, 125 can be implemented with six CIC filters (or 3 complex ones). In the example context of each lowpass filter being implemented as a CIC3 filter, each of the CIC3 filters can include three accumulators. Such accumulators can have a large bit-width (e.g., 64 bits) due to a potentially large decimation ratio. [0249] Figures 14A to 14C show examples of how DFT computation can be achieved to provide a desired effect. Referring to Figure 14A, a signal and a tone are shown to be multiplied by a multiplier, and the product is shown to be provided to a CIC3 filter to generate an impulse response as a single-bin DFT output. Such a CIC filter can be the CIC3 filter 115 or the CIC3 filter 125 of Figure 13. For the former (CIC3 filter 115), the signal is the input signal, and the multiplier is 113 in Figure 13, with the tone being a complex sinusoid tone (indicated as ^ ^{^^^^#} signal in Figure 13). For the latter (CIC3 filter 125), the signal is the output signal, and the multiplier is 123 in Figure 13, with the tone being the same complex sinusoid tone. [0250] Figure 14B shows that in some embodiments, the impulse response from the CIC3 (CIC3 impulse response) described above in reference to Figure 14A can be multiplied with a product of signal and tone (multiplied by a multiplier similar to Figure 14A) to generate a product that is provided to an assembly of accumulator(s). Such an assembly of accumulator(s) then provides a single-bin DFT output. [0251] Figure 14C shows that in some embodiments, the impulse response from the CIC3 (CIC3 impulse response) described above in reference to Figure 14A can be pre-multiplied with a tone (complex sinusoid) to generate a windowed tone. Such a windowed tone is shown to be multiplied with a signal by a multiplier similar to generate a product that is provided to an assembly of accumulator(s). Such an assembly of accumulator(s) then provides a single-bin DFT output. [0252] In some embodiments, a windowing technique can be applied to the measurement tone (e.g., as in the example of Figure 14C) to make it inaudible by preventing sidelobe leakage into the audio band. As described in reference to Figure 14C, pre-multiplying the tone with the CIC3 impulse response can provide a desirable tone ramp up/down and simplify the CIC3 filter implementation to a single accumulator. [0253] In some embodiments, duration of the foregoing tone can be controlled by, for example, an 18-bit programmable register which specifies the number of samples divided by 3. The example division by 3 is for ease of implementation of CIC3 impulse response. [0254] Figure 15 shows an example of a windowing process that can be applied to the measurement tone described above. In the example of Figure 15, a 3rd order window is generated by a window circuit configured as a sinc3 window generator. Additional details concerning such an example window are described herein. [0255] In some embodiments, a calibration cycle can include some or all of the following operations: (1) Injecting of an ultrasonic calibration tone having an amplitude, frequency, and duration; (2) Enabling, for the duration of the calibration tone, an ADC that digitizes the PWM amplifier output and sends the digitized signal back to the gain calibration block; (3) also routing a copy of the signal going to the amplifier (including the input signal and the calibration tone) to the gain calibration block; (4) computing a single-frequency DFT (at the calibration tone frequency) of the PWM amplifier output signal and computing a single-frequency DFT (at the calibration tone frequency) of the PWM amplifier input signal in parallel; and (5) saving the ratio of the two single- frequency DFTs (DFT of the PWM amplifier output to DFT of the amplifier input) as a transfer function (TF), with the TF being TF_HOR if the calibration cycle was performed in the HOR mode, or TF_ZOR if the calibration cycle was performed in the ZOR mode. [0256] It is noted that the transfer function described above is generally immune to the presence of ultrasonic energy in the input signal. In fact, any energy around the calibration tone frequency in the input signal acts substantially the same as the calibration tone and can provide an enhanced measurement. In contrast, such an energy around the calibration tone frequency acts as an interferer for a calibration configuration where only the amplifier output level is being measured for calibration. [0257] In some embodiments, a gain calibration algorithm can include some or all of the following: (1) A calibration cycle can be performed if a programmable time interval has passed. There may be parallel timers for HOR mode and ZOR mode. If sufficient time has passed since a successful calibration cycle in HOR mode, a new HOR mode calibration cycle can be implemented as soon as the audio amplifier enters HOR mode. The same can be achieved for ZOR mode as well. (2) At the end of each successful calibration cycle, a ratio of saved TF_HOR and TF_ZOR can be computed. (3) The foregoing ratio can be further transformed by a programmable multiplicative correction factor followed by a programmable additive correction factor. The real part of the final result can be treated as an effective relative HOR gain of the system (e.g., HOR mode gain when treating the ZOR mode gain as unit gain). Multiplicative and additive correction factors can be utilized to compensate for any systematic bias in the estimation process. By default, the multiplicative correction factor can be set to 1, and the additive correction factor can be set to 0, so as to not have any effect. [0258] For the purpose of description, let u(n), v(n), x(n) and y(n) represent the n-th samples of the digital input signal, calibration tone, amplifier input signal and amplifier output signal, respectively. If the duration of the calibration tone is N samples, then n can range from 0 to N-1. Then, v(n) can be expressed as v(n) = A * w(n) * cos(2*pi*f*n/Fs), where A is a programmable tone amplitude, f is a programmable calibration tone frequency, Fs is a sample rate (e.g., 3.072 MHz), and w(n) is a window function to fade in and out the calibration tone smoothly, since a sudden start/stop might produce an audible pop. In some embodiments, the window function w(n) can be one of defined window functions. For example, the window function can be an impulse response of a third-order CIC filter. In such a configuration, a window function can be generated on the fly easily without the need for storing the window shape. [0259] It is noted that x(n) = u(n) + v(n), DFT_X = sum_over_n (x(n) * w(n) * (cos(2*pi*f*n/Fs) + 1i * sin(2*pi*f*n/Fs))), and DFT_Y = sum_over_n (y(n) * w(n) * (cos(2*pi*f*n/Fs) + 1i * sin(2*pi*f*n/Fs))), where w(n) represents a window function to limit sidelobe leakage. In some embodiments, a window function may or may not be utilized. Use of the window function based on the same CIC3 window described above can be beneficial to fade in/out the cal tone. [0260] It is noted that TF_xOR = DFT_Y/DFT_X, where x is “H” for HOR or “Z” for ZOR. Thus, the ratio TF_xOR can be either TF_HOR or TF_ZOR depending on which mode the calibration cycle was performed in. [0261] It is noted that CORR_MUL (complex-valued) and CORR_ADD (real- valued) can be programmable correction factors. Then, the final output (relative HOR gain) can be given by Relative_HOR_gain = real(CORR_MUL * TF_HOR / TF_ZOR) + CORR_ADD. [0262] In some embodiments, some or all of the following additional features can be implemented. For example, a calibration cycle can be aborted and not marked successful (or as not have happened) in the following events: (1) There is a mode transition during the calibration cycle. (2) The magnitude of the DFT of the analog amplifier input signal is lower than a threshold. This is to protect against a very unlikely case that the calibration tone and digital input signal cancelled each other out very well at the calibration tone frequency. (3) The magnitude of the DFT of the amplifier input signal (same as above) is above a certain threshold. This is to protect against making measurements when some analog parts of the amplifier may be in significant non-linear mode of operation. [0263] In another example, the right hand side of the above-referenced DFT computation can contain the calibration tone. [0264] In yet another example, some or all of the frequency, amplitude, and duration of calibration tone can be programmable. It is noted that a programmable frequency provides an ability to change the location of the calibration tone to avoid any problematic part of the spectrum in a product. It is also noted that a higher tone level can result in more accurate estimate, but can also consume more power and would be more likely to push analog into a non-linear mode. It is also noted that a longer duration can also make the estimates more accurate. [0265] In yet another example, a boot calibration process can be implemented as part of a boot up sequence, before any input audio is processed. HOR and ZOR cal cycles can be performed to start the chip with a good estimated of relative HOR gain. [0266] In yet another example, an ADC nonlinearity correction can be applied. The ADC used to digitize the amplifier output for the calibration process can suffer from some nonlinearity. Such an effect can be corrected by modifying the equation for x(n) as follows: x(n) = u(n) + v(n) + k*d(n), where d(n) is an estimate of the non-linearity produced by the ADC. This is estimated by another part of the design (e.g., PWM controller) and routed to the gain calibration block. The quantity k is a parameter stored in, for example, an OTP memory as part of a calibration process during ATE testing of the chip. Feature 2 [0267] As described above, a window circuit can be implemented with a gain calibration circuit to provide a windowing functionality for the calibration circuit. It is noted that a windowing technique can be utilized to process a signal to, for example, reduce a sidelobe leakage during a Fourier transform process such as a DFT or FFT, and/or smoothly fade in and out a signal without creating a large discontinuity (or an audible artifact such as a "pop" noise). In some embodiments, such a window can be configured to provide sufficient sidelobe attenuation for a signal being windowed. [0268] In some embodiments, a window having one or more features as described herein can be generated without evaluating complicated functions. In some embodiments, a window having one or more features as described herein can be implemented without having to retrieve a saved window configuration that was previously generated. [0269] In some embodiments, a window circuit can include a sinc function based window that allows generation of a desired window on-the-fly (e.g., while the window circuit is in operation) with an efficient hardware implementation. Such a window can provide desirable features such a high sidelobe attenuation, large length if needed or desired, and be configured with relatively simple logic circuits such as a few adders. [0270] It is noted that when a signal that is windowed by the foregoing sinc function based window circuit undergoes a Fourier transform, the resulting transform can be represented by one or more powers of the sinc function. For example, a sinc3 window results in a Fourier transform being a third power of the sinc function. Similarly, a sinc4 window results in a Fourier transform being a fourth power of the sinc function. In some embodiments, a higher order sinc window configuration can provide more sidelobe attenuation. [0271] Figure 16 shows a block diagram of a window circuit 150 that can provide the foregoing functionality, including the sinc function based windowing functionality. The window circuit 150 is shown to include a pulse train generator 152 configured to generate a sequence of M rectangular pulses based on an amplitude vector, for an M-th order window. Each pulse can be L samples wide if the total desired window duration is to be L x M samples. The amplitude of each pulse (for all L samples within it) can be provided as a value in the input amplitude vector. In some embodiments, such an amplitude vector can include M values that are specified in, for example, a table such as a lookup table. [0272] Referring to Figure 16, the pulse train generated by the generator block 152 can be fed to a chain (156) of M-1 accumulators 154. In some embodiments, the output of the last accumulator of the chain 156 can be utilized as a desired window having a width of L x M samples. [0273] Figure 17 shows an example of a 4-th order window generated by the window circuit 150 of Figure 16 configured as a sinc4 window generator. In such a configuration, M = 4, and suppose that each rectangular pulse has a width of L = 64 samples. Then, the resulting sinc4 window has a length of M x L = 256 samples. [0274] Referring to the example of Figure 17, the left-most panel shows an output of the rectangular pulse train generator 152 of Figure 16, with an initial amplitude being specified to be 1. The chain 156 of accumulators includes three accumulators 154 since M-1 = 3. Thus, an output of the first accumulator is shown in the panel indicated as Accumulator 1; an output of the second accumulator is shown in the panel indicated as Accumulator 2; and an output of the third accumulator is shown in the panel indicated as Accumulator 3. [0275] In the example of Figure 17, the output of the third accumulator (Accumulator 3) can be utilized as a desired window of the sinc4 window. [0276] It is noted that in the example of Figure 15 described herein, the example window is a 3rd order window that can be generated by the window circuit 150 of Figure 16 configured as a sinc3 window generator. In such an example configuration, M = 3, and each rectangular pulse has a width of L. [0277] Referring to the example of Figure 15, the top panel shows an output of the rectangular pulse train generator 152 of Figure 16, with an initial amplitude being specified to be 1. The chain 156 of accumulators includes two accumulators 154 since M-1 = 2. Thus, an output of the first accumulator is shown in the middle panel, and an output of the second accumulator is shown in the bottom panel. [0278] In the example of Figure 15, the output of the second accumulator can be utilized as a desired window of the sinc3 window. [0279] In some embodiments, a window generated by the window circuit 150 of Figure 16 can be normalized with respect to some or all of the following. For example, a window can be scales such that its peak is approximately 1. In another example, a window can be scaled such that the sum of all samples is approximately 1. In yet another example, a window can be scaled such that its RMS of all samples is approximately 1. [0280] It is noted that the window circuit configured to provide sinc function based windows can provide efficient normalization, including some or all of the foregoing normalization examples, by scaling few samples in an amplitude vector that controls the amplitudes of the rectangular pulse train. For example, an amplitude vector can be scaled such that the peak output of the final accumulator is a power of 2. In such a configuration, the final output can be shifted (e.g., right-shifted) to normalize the peak to be approximately 1. [0281] Table 1 lists examples of amplitude vectors, for various example orders, that can be provided to the rectangular pulse train generator 152 of the window circuit 150 of Figure 16. For example, the amplitude vector for the 3rd order is shown to provide the amplitudes in the rectangular pulse train in the example of Figure 15. In another example, the amplitude vector for the 4th order is shown to provide the amplitudes in the rectangular pulse train in the example of Figure 17. Table 1 [0282] Referring to Table 1, it is noted that in some embodiments, an amplitude vector (AmpM(i), i = 1 to M)) for generating an M-th order window can be obtained by setting AmpM(1) = 1, and AmpM(i) = AmpM-1(i) – AmpM-1(i-1), where AmpM-1 is the amplitude vector for the M-1 order window, and AmpM-1(i) = 0 for i > M. [0283] Thus, and by way of example, Table 2 lists the same amplitude vectors as in the example of Table 1, but in which an M-th order array can be provided with zeros for at least the i = M + 1 element. In the example of Table 2, an M-th order array is shown to be provided with zeros for elements having i > M. Table 2 [0284] Thus, for example, the 3rd order amplitude vector listed in Table 2 can be generated as follows: Amp3(1) = 1, Amp3(2) = Amp2(2) – Amp2(1) = -1 – 1 = -2, and Amp3(3) = Amp2(3) – Amp2(2) = 0 – (-1) = +1. [0285] Similarly, the 4th order amplitude vector listed in Table 2 can be generated as follows: Amp4(1) = 1, Amp4(2) = Amp3(2) – Amp3(1) = -1 – 1 = -3, Amp4(3) = Amp3(3) – Amp3(2) = 1 – (-2) = +3, and Amp4(4) = Amp3(4) – Amp3(3) = 0 – 1 = -1. [0286] Referring to the example of Table 2, it is noted that the foregoing scheme of obtaining the value of an i-th element of an M-th order vector by a difference between successive terms of the (M-1)-th order vector can be generalized to include the first element, instead of the first element being specified as having a value of 1 (i.e., AmpM(1) = 1), if one assumes that the value of AmpM-1(i) = 0 if i = 1. Thus, Amp3(1) can be calculated as Amp3(1) = Amp2(1) – Amp2(i<1) = 1 – 0 = 1. Similarly, Amp4(1) can be calculated as Amp4(1) = Amp3(1) – Amp3(i<1) = 1 – 0 = 1. [0287] In some embodiments, a window circuit can be configured to generate an M-th order window by retrieving stored values for a respective amplitude vector (such as the vector values of Table 2), by generating values for a respective amplitude vector on- the-fly in a recursive manner, or some combination thereof. [0288] Figure 18A shows an example of a 4th order window in time domain, and Figure 18B shows the same window in frequency domain, generated by the window circuit of Figures 16 and 17. Feature 3 [0289] In many electronic applications, a digital-to-analog converter (DAC) is utilized to convert a digital signal to an analog signal. Typically, the resulting analog signal is an output voltage within a range and resolution defined by the number of bits in the input digital signal. Accordingly, it is desirable to have an output voltage of a DAC to accurately reflect a given set of bits in the input digital signal. [0290] Figure 19 shows a DAC 101 configured to convert a digital input signal into a corresponding analog output signal. Operation of such a converter can be supported by a reference circuit 102 that provides a reference voltage to each bit cell of the DAC 101. Accordingly, and depending on the type of bit cell-configuration, bit cells enabled by the digital input signal provide a combination of their respective reference voltages to yield an output voltage representative of the digital input signal. Thus, accuracy of the reference voltage(s) provided to the bit cells of the DAC is important for obtaining an accurate analog output signal. Described herein are examples related to circuits and methods for providing such accurate reference voltages for DACs. [0291] Figure 20 shows that in some embodiments, the DAC 101 of Figure 19 can be implemented as the DAC 1044 as described herein (e.g., in reference to Figures 5, 7 and 8). Accordingly, in Figure 20, the DAC 1044 is also indicated as 101. [0292] Referring to Figure 20, a reference circuit 102 is shown to be implemented with the DAC 101, 1044, and such a reference circuit can include one or more features as described herein. [0293] In the example of Figure 20, the DAC 101, 1044 is shown to be a part of a PWM amplifier 1022 which is a part of a device (e.g., a chip) having an audio amplifier circuit 1000. The DAC 101, 1044 is shown to receive a digital signal from a digital audio path 1044 and provide an analog output representative of the input digital signal to a loop circuit associate with an H-bridge driver 1052. [0294] It will be understood that a DAC 101 having one or more features as described herein can be utilized as the foregoing DAC 1044 for the audio amplifier circuit 1000, as well as in any other electronic circuits that utilize DACs. [0295] Figure 21 depicts a portion of a DAC calibration circuit 12 configured to set a DAC bit cell current. In such a circuit, a reference voltage Vref from a reference voltage source 14, typically a bandgap based reference voltage, is provided to a comparator 18 along with a feedback voltage Vreffb representative of an output voltage Vgs. More particularly, a bit cell bias circuit 20 is shown to provide a current through a resistance R, and Vreffb is obtained from a node 22 before the resistance R. With the foregoing feedback circuit, the bit cell bias circuit 20 can provide an output voltage for bit cells that is substantially equal to, or accurately tracks, the reference voltage Vref. [0296] In the example of Figure 21, the DAC calibration circuit 12 is shown to include a capacitor C implemented between a node 16 and ground. Capacitance of such a capacitor can be selected to provide filtering functionality, such that the Vref voltage being input into the comparator 18 has a low level of noise. Such a capacitance can be, for example, greater than 800 pF; and the corresponding capacitor C would be a relatively large device if implemented as an on-chip device. [0297] Thus, if space is of no concern on a device 10 of Figure 21, implementation of the DAC calibration circuit 12 on such a device can be practical. However, if the device 10 of Figure 21 is, for example, a semiconductor die and space and/or any capacitor effects are of concern, the large size of the capacitor C on the die would not be practical for implementation. [0298] Figure 22 depicts a DAC calibration circuit 102 configured to set a DAC bit cell current. In some embodiments the DAC calibration circuit 102 can include or be coupled to a local low-noise reference source 104 that provides a low-noise reference voltage Vrefln to a comparator 108. A feedback voltage Vreffb is shown to be generated by a bit cell bias circuit 120 based on an output Vgs of the comparator 108, and such a feedback voltage is also shown to be provided to the comparator 108. More particularly, the bit cell bias circuit 120 is shown to provide a current Ical through a variable resistance Rcal, and Vreffb is obtained from a node 122 before the resistance Rcal. With the foregoing feedback circuit, the bit cell bias circuit 120 can provide an output voltage that is substantially equal to, or accurately tracks, the low-noise reference voltage Vrefln. [0299] It is noted that in the example of Figure 22, the local low-noise reference voltage Vrefln is being used to drive the current source bit cells. In some embodiments, such a reference voltage can be optimized for lower power and noise with a small layout area, but with a larger temperature coefficient. Thus, in some embodiments, such a reference voltage can be calibrated with respect to, for example, a trimmed main bandgap based voltage reference to ensure that the gain accuracy of the DAC is maintained over temperature. [0300] In the example of Figure 22, the foregoing calibration of the local low- noise reference voltage Vrefln can be achieved by a bit cell reference current (Iref) circuit 130 that senses the output voltage of the bit cell bias circuit 120 as a sensed voltage Vrefsense. A corresponding current Irefsense is shown to be provided at a path between the bit cell reference current circuit 130 and ground, with the path having a resistance Rsense. [0301] The sensed voltage Vrefsense is shown to be provided to a calibration block 150 through a path 134 from a node 132. The calibration block 150 is shown to generate a control signal 152 to adjust the resistance of the variable resistance Rcal, thereby calibrating the output of the bit cell bias circuit 120 that is being driven by the local low-noise reference voltage Vrefln. Examples related to the calibration block 150, including a reference voltage Vref used by the calibration block 150, are described herein in greater detail. [0302] In the example of Figure 22, the bit cell reference current circuit 130 is shown to provide the sensed voltage Vrefsense (which is substantially equal to, or accurately tracks, the reference voltage Vref of the calibration block 150) to a bit cell output circuit 140. The bit cell output circuit 140 is shown to provide an output current I based on Vrefsense which is now substantially equal to Vref. More particularly, the output current can be I = Vref/Rsense. [0303] Figure 23 shows a DAC calibration circuit 102 that can be a more specific example of the DAC calibration circuit 102 of Figure 22. More particularly, Figure 23 shows a more detailed example of the calibration block 150 of Figure 22. In Figure 23, various components 104, 108, 120, 130 and 140 are arranged generally the same as in Figure 22. [0304] Figure 23 shows that in some embodiments, the calibration block 150 of Figure 22 can utilize an output of a comparator 160 that receives a reference voltage Vref from a reference source (e.g., main bandgap) through a path 162, and the sensed voltage Vrefsense through a path 134. The comparator 160 is shown to provide its output at node 166, and a capacitive feedback circuit with capacitance Ccal is shown to be provided between the output 166 and the second input (node 164) of the comparator 160. [0305] Referring to Figure 23, the output signal of the comparator 166 is shown to be converted into a digital signal by an ADC 170 having a quantizer 170 operating with a calibration clock and a successive approximation register (SAR) 180. The digitized signal from the SAR 180 is shown to be provided as control codes (RCAL_codes) to the variable resistance Rcal through a path 152. Accordingly, the current (Ical in Figure 22), and thus the local reference voltage Vrefln can be adjusted (e.g., for temperature-dependent variation) so that the voltage Vrefsense being compared to the reference voltage Vref is made to be substantially equal to the reference voltage Vref. [0306] In the example of Figure 23, the resistance Rsense for determining the sensed current Irefsense at node 132 can be implemented to be adjustable by a control code Vreftrim_code provided by, for example, the calibration block 150. Such an adjustment to the resistance Rsense can allow trimming of the voltage Vrefsense being provided to the comparator 160. [0307] In some embodiments, the local low-noise reference source 104 can be configured to provide local reference voltages having different levels of noise. For example, local reference voltages can have successively lower noise levels, but the expense of successively higher power consumption. [0308] In some embodiments, the DAC calibration circuit 102 of Figures 22 and 23 can be operated in the background while a device (100 in Figure 22, and, for example, a device having the audio amplifier circuit 1000 of Figure 5) having the corresponding DAC (e.g., 1044 in Figure 5) is operating in an audio mode. If there is an update to be made by the DAC calibration circuit 102, a corresponding adjustment can be made and applied at, for example, the next audio signal zero crossing to minimize or reduce any artifact. [0309] It is noted that in some embodiments, the device 100 on which the DAC calibration circuit 102 is implemented on does not have a capacitor similar to the capacitor C of Figure 21. Accordingly, a DAC calibration circuit, such as the DAC calibration circuit 102 of Figures 22 and 23, does not require such a relatively large capacitor. Thus, such an absence of the relatively large capacitor is beneficial when the device 100, such as a semiconductor die, is relatively small. [0310] In some embodiments, a DAC calibration circuit having one or more features as described herein can be implemented for any electronic application where a DAC is utilized. As described herein, such an electronic application can include an audio signal processing application. Feature 4 [0311] Described herein are examples related to a driver configured to provide output pulses having multiple voltage levels. In some embodiments, such a multi-level output driver can be utilized to provide driving pulses with variable voltage levels for an audio amplifier such as the PWM amplifier 1022 of Figure 7. More particularly, in the example of Figure 7, the H-bridge driver 1052 can be configured to provide driving pulses with variable voltage levels to the output nodes HPP, NPN for driving the speaker 1004. As described herein, use of such width-modulated pulses with variable voltage level can provide improved performance such as improved efficiency for higher- power signals (e.g., in ZOR mode) and lower noise for lower-noise signals (e.g., in HOR mode). [0312] Figure 24 shows an example of a multi-level output driver 10 configured to generate output pulses having an amplitude Vout that ranges from approximately 0 to approximately VDD which is the maximum drive voltage being provided as a supply voltage. In the example of Figure 24, the driver 10 is shown to include a PMOS device having its source coupled to a supply voltage (VDD) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. Configured in the foregoing manner, an input signal can be provided to each of the gates of the PMOS and NMOS devices, and the gates can be controlled to generate the output pulses. [0313] As described above, the single driver 10 of Figure 24 is designed to handle up to the maximum voltage (the supply voltage VDD in Figure 24). If such a supply voltage is the same as a battery voltage (e.g., in a wireless application), the transistor devices may be unnecessarily large for operating conditions where the output voltage is significantly less than the battery voltage. Further, and also as described above, the relatively large battery voltage can result in an unnecessarily high switching loss where the output voltage is significantly less than the battery voltage. [0314] It is noted that when the foregoing transistor devices are large to allow handling of higher voltages, such transistors typically have long channel lengths that results in larger parasitic capacitances. It is also noted that in terms of power efficiency of an audio amplifier which is directly related to the on-resistance (Ron) of an output device such as the foregoing transistor device, bigger device and larger drive voltage (for low Ron) are desirable. On the other hand, such features can result in higher switching energy loss based on a switching power relation P = CV ² f (where C is capacitance, V is drive voltage swing, and f is switching frequency). [0315] Figure 25 shows that in some embodiments, a multi-level output driver 100 can include a plurality of driver groups (e.g., 102a, 102b) where each driver group is configured to receive an input signal and generate an output signal having pulses with an amplitude in a range based on a respective supply voltage value. For example, a first driver group 102a is shown to receive an input signal (Input1) and generate an output signal (Output1), based on operation with a supply voltage Vmax1, where the output signal has pulses with an amplitude in a range from approximately 0 to approximately the supply voltage value Vmax1. In another example, a second driver group 102b is shown to receive an input signal (Input2) and generate an output signal (Output2), based on operation with a supply voltage Vmax2, where the output signal has pulses with an amplitude in a range from approximately 0 to approximately the supply voltage value Vmax2 (supply voltage of the second driver group 102b). It will be understood that one or more additional driver groups may also be implemented for the multi-level output driver 100. [0316] Figure 25 also shows that in some embodiments, a switch assembly 104 can be implemented to allow selection of a driver group for operation, and/or to provide output protection for one driver group from operation of another driver group. Examples of the foregoing switch assembly are described herein in greater detail. [0317] In the example of Figure 25, the multi-level output driver 100 is shown to provide an output (Output) having pulses with an amplitude in a range that covers the ranges of the driver groups. More particularly, in the example of Figure 25, the range of amplitude of the output of the multi-level output driver 100 is shown to in a range from approximately 0 (lower limit of the output range of the first driver group 102a) to approximately Vmax2 (upper limit of the output range of the second driver group 102b), assuming that Vmax2 is greater than Vmax1. [0318] In the example of Figure 25 where Vmax1 of the first driver group 102a is less than Vmax2 of the second driver group 102b, the transistors of the first driver group 102a can be dimensioned sufficiently large to handle the maximum voltage Vmax1, but nor unnecessarily larger. Similarly, the transistors of the second driver group 102b can be dimensioned sufficiently large to handle the maximum voltage Vmax2. Thus, in an operation where lower voltage levels are needed, the first driver group 102a can be utilized with the switch 104 configured appropriately, such that the output of the driver 100 is in a range between 0 and Vmax1 without undesirable effects of the larger transistor devices of the second driver group 102b. In an operation where higher voltage levels are needed, the second driver group 102b can be utilized with the switch 104 configured appropriately, such that the output of the driver 100 is in a range between 0 and Vmax2 where benefits associated with improved power efficiency can outweigh undesirable effects of the larger transistor devices of the second driver group 102b. [0319] In the example of Figure 25, the switch 104 can be configured so that one driver group is sufficiently isolated from operation of the other driver group. For example, when the higher voltage second driver group 102b is in operation, the switch 104 can be configured to support such an operation and to sufficiently isolate the lower voltage first driver group 102a from the second driver group 102a. Accordingly, the first driver group 102a, which is more susceptible to damage from higher voltages, can be protected from operation of the second driver group 102b. [0320] Figure 26 shows an example where a multi-level output driver 100 includes three driver groups 102a, 102b, 102c and a switch assembly 104 that are implemented to provide an output having pulses with amplitude in a range of approximately 0 to approximately VBAT which is an example maximum supply voltage value among the three driver groups. [0321] More particularly, the first driver group 102a is shown to include a PMOS device having its source coupled to a first supply voltage (VDD (Low)) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. Configured in the foregoing manner, a first set of control signals (VGP_L, VGN_L) can be provided to the gates of the PMOS and NMOS devices to generate a first output of pulses having a first range of approximately 0 to approximately the first supply voltage VDD (Low). [0322] The second driver group 102b is shown to include a PMOS device having its source coupled to a second supply voltage (VDD (Medium)) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. Configured in the foregoing manner, a second set of control signals (VGP_M, VGN_M) can be provided to the gates of the PMOS and NMOS devices to generate a second output of pulses having a second range of approximately 0 to approximately the second supply voltage VDD (Medium). [0323] The third driver group 102c is shown to include a PMOS device having its source coupled to a third supply voltage (VDD (VBAT)) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. Configured in the foregoing manner, a third set of control signals (VGP_H, VGN_H) can be provided to the gates of the PMOS and NMOS devices to generate a third output of pulses having a third range of approximately 0 to approximately the third supply voltage VDD (VBAT). [0324] In the example of Figure 26, the output of the first driver group 102a is coupled to an output (Output) of the multi-level output driver 100 through a first switch HVNMOS controlled by application of a control voltage Vcontrol_L to its gate. Similarly, the output of the second driver group 102b is coupled to the output of the multi-level output driver 100 through a second switch HVNMOS controlled by application of a control voltage Vcontrol_M to its gate. The output of the third driver group 102c is shown to be coupled to the output of the multi-level output driver 100 without a switch. [0325] Configured in the foregoing manner, the multi-level output driver 100 can provide an output of pulses having an amplitude in the first range (0 to VDD (Low)) associated with the first driver group 102a by enabling the first driver group 102a, turning ON the first switch HVNMOS at the output of the first driver group 102a, and disabling each of the second driver group 102b and the third driver group 102c. The second switch HVNMOS at the output of the second driver group 102b is preferably turned OFF to reduce the effect of off-capacitance of the second driver group on the operation of the first driver group 102a. [0326] Referring to Figure 26, the multi-level output driver 100 can provide an output of pulses having an amplitude in the second range (0 to VDD (Medium)) associated with the second driver group 102b by enabling the second driver group 102b, turning ON the second switch HVNMOS at the output of the second driver group 102b, and disabling each of the first driver group 102a and the third driver group 102c. The first switch HVNMOS at the output of the first driver group 102a can be turned OFF to protect the transistor devices of the first driver group 102a from the output voltage of the operating second driver group 102b, since such an output voltage (of the second driver group 102b) has a value higher than the design limit of the transistor devices of the first driver group 102a. The transistor devices of the third driver group 102c are able to handle the maximum output voltage (VDD (Medium)) of the lower operating range of the second driver group 102b. [0327] Referring to Figure 26, the multi-level output driver 100 can provide an output of pulses having an amplitude in the third range (0 to VDD (VBAT)) associated with the third driver group 102c by enabling the third driver group 102c, turning OFF each of the switch HVNMOS at the output of the first driver group 102a and the switch HVNMOS at the output of the second driver group 102b, and disabling each of the first driver group 102a and the second driver group 102b. The first switch being OFF at the output of the first driver group 102a protects the transistor devices of the first driver group 102a from the output voltage of the operating third driver group 102c, since such an output voltage (of the third driver group 102c) has a value higher than the design limit of the transistor devices of the first driver group 102a. Similarly, the second switch being OFF at the output of the second driver group 102b protects the transistor devices of the second driver group 102b from the output voltage of the operating third driver group 102c, since such an output voltage (of the third driver group 102c) has a value higher than the design limit of the transistor devices of the second driver group 102b. [0328] It is noted that in the example of Figure 26, the three driver groups used for multi-level output generation are categorized based on output voltage ranges defined by their respective supply voltage levels; and more particularly, as a low level supply group, a medium level supply group, and a high level supply (e.g., battery level) group. In the low level group, transistor devices with the shortest channel length (among the three groups) can be utilized; in the medium level group, transistor devices with a mid-length channel length (among the three groups) can be utilized; and in the high level group, transistor devices with the longest channel length (among the three groups) can be utilized. [0329] In the example of Figure 26, a given driver group can utilize any supply level below the upper operating limit associated with the respective transistor devices. Thus, as example, the first driver group (low level supply group) can be operated to generate a low level signal (e.g., zero to VDD (Low)); the second driver group (medium level supply group) can be operated to generate a medium level signal (e.g., zero to VDD (Medium), with VDD (Low) < VDD (Medium)); and the third driver group (high level supply group) can be operated to generate a high level signal (e.g., zero to VBAT, with VDD (Medium) < VBAT). [0330] Accordingly, in some embodiments, the low level supply group 102a can be utilized to generate low level signals (e.g., level less than V_low), the medium level supply group 102b can be utilized to generate medium level signals (e.g., V_low ≤ level < V_medium), and the high level supply group 102c can be utilized to generate high level signals (e.g., V_medium ≤ level < VBAT). [0331] It is further noted that for the foregoing example where the driver groups are based on output voltage ranges (e.g., low level, medium level, high level), the transistor devices in the low and medium level groups can be protected from the higher operating voltage of the high level group, by the respective HVMOS switches implemented along the respective output paths. Accordingly, each transistor device in each group can be implemented with a respective shortest channel length, so as to yield a smaller parasitic capacitance. Thus, power loss can be minimized or reduced during the output switching operation. Such minimization or reduction of power loss can be beneficial for minimizing or reducing power consumption of the multi-level output driver and/or for improving power efficiency when the audio output is low. [0332] It is further noted that because the output level transition among the driver groups to accommodate changes in the audio signal level is typically not frequent, any switching loss associated with the protection switches (HVMOS in Figure 26) is much smaller compared to the switching losses resulting from the transistor devices in the low and medium groups occurring in every cycle running at the modulation frequency. When the audio level is high, only the transistor devices in high level group are performing switching operations; thus, during such an operating state, protection from the high output level (e.g., up to VBAT) is provided for the low and medium groups by the respective switches (HVMOS) being turned OFF. [0333] In some embodiments, and as described herein, a multi-level output driver having one or more features as described herein can be implemented for any electronic application where an audio amplifier is being utilized, including, for example, a Class D PWM audio amplifier. Feature 5 [0334] As described herein, an audio amplifier circuit can be configured to operate in a high output resistance (HOR) mode or in a zero output resistance (ZOR) mode to provide desirable balance of power efficiency and performance. Figure 27 shows an output portion of an H-bridge driver 100 (1052 in Figures 7 and 8) configured to operate in such a HOR mode or ZOR mode. For example, when in a HOR mode, the ZOR Mode P Drive circuit is disabled, and the HOR Mode P Drive circuit is enabled to drive a load 110 (e.g., a speaker, 1004 in Figure 7) along with the N Drive circuit. As described herein, such an output stage of Figure 27 can be configured to operate as a Class D audio amplifier with pulse width modulation (PWM). [0335] It is noted that in order to maximize drive, constrain output pin voltage range, and control reverse power supply current, the positive and negative drive outputs (HPP, HPN) of the foregoing amplifier in the HOR mode often need to have voltages that do not follow a signal voltage, such that there can be a large harmonic content on the per-pin voltage, even though the output differential voltage has a very low total harmonic distortion (THD). Since such an HOR amplifier is outputting a current, the harmonic components of output voltages will be converted to currents at the impedance of the combination of both internal driver capacitances and external components, and these currents will be added or subtracted from the load current and thus will be presented as an increased THD to the load. [0336] It is further noted that voltages on the output pins (HPP, HPN) that are current driven can have a mixture of harmonic and signal values. A reactive impedance of internal and external devices typically causes a very small gain error with the pin changes that follow the signal, so such a reactive impedance can be neglected. In some embodiments, however, such a reactive impedance can be tracked for high gain accuracy. The foregoing feature allows the voltage drop across the output switching devices to be ignored since it will follow the signal current and therefore does not add significant amount of harmonic content. [0337] In some embodiments, a PWM logic can be configured to estimate an input drive to switching devices of an PWM-controlled audio amplifier, either by using a nominal supply voltage that has a narrow range, or by measuring a voltage where the range is larger, to convert a change associated with that voltage into a corresponding current with information about the internal/external devices. Such a current/information can then be injected this into the digital signal path so that a complementary current is driven out to cancel the effect. [0338] By way of an example, a look up table with charge vs voltage can be configured, and when the output drive voltage changes, a corresponding delta in current between the entries can be used to drive a correction signal. Additionally this correction can be limited in amount for a single cycle, or be implemented over multiple cycles to deliver some or all of an entire correction to achieve a desired result without affecting system stability. [0339] Figure 28 depicts various currents that may be present during a HOR mode operation, at the HORP (output of the HOR mode P Drive, 1172 in Figures 7 and 8), HPP (output for the load, as well as the ZOR mode P Drive, HPP in Figures 7 and 8) and HPN (output for the load, as well as the N Drive for both HOR and ZOR modes, HPN in Figures 7 and 8) nodes of Figure 27. Figures 28 and 29 show that in some embodiments, a correction techniques as described herein can be implemented. [0340] Referring to Figure 28, it is noted that in the example HOR mode, the H- bridge driver has the HOR driver (1172 in Figures 7 and 8) operate as a current driver with the controlled current being driven from HORP node, across the sense resistance Rs and into the HPP node. The current driven into the load 110 can be sensed as a voltage across the sense resistance Rs. It is noted that the voltage on the HPP node can have a complicated and non-linear relationship to the audio signal. It is also noted that any current diversions into/away from HPP node can be a possible source of error in the current waveform as seen by the load 110. It is also noted that the disabled ZOR driver (1170 in Figures 7 and 8) is still attached to the HPP node, and presents a capacitive load, and the board trace from the HPP node to the headphone speaker also presents an additional capacitive load. [0341] For example, the H-bridge driver can operate in HOR mode at one of multiple sense resistance values (e.g., modes 0, 1, 2, 3, 4 corresponding to successively higher resistance values). In the example of Figure 28, the HOR driver (1172 in Figures 7 and 8) is shown to be operating in mode 3, such that the HORP node is indicated as HORP<3>. From the node HORP<3>, current IS is shown to be provided through the sense resistance Rs, and a feedback current is shown to be provided as Feedback_HORP<3>. At the node HPP, the current IS is shown to drive the load 110 as current IL, and a feedback current is shown to be provided as Feedback_HPP. Also from the HPP node, a stray current Istray is shown to be present. Such a stray current can result from resistive and capacitive loads associated with inactive operating modes (e.g., modes, 0, 1, 2, 4) presented to the HPP node. The stray current can also result from a capacitive load associated with the inactive ZOR driver. Referring to Figure 28, a stray current (IstrayHPN ) can also be present from the HPN node. [0342] It is noted that whenever the voltage on the HPP node changes, the rate- of-change of that voltage, times the combined capacitance, creates an error current to the load. If the HPP node followed the audio signal, the error would just be a small phase shift and would have a negligible effect on THD+N performance. However, the waveform at the HPP node can have considerable harmonic and noise content, due to the many constraints of HPP excursion protection, multiple power rails and other switching efficiency features, such that the current injection (Istray) due the parasitic capacitances create harmonic distortion in the output. It is noted that capacitance from HPP to HPN is generally not an issue, as the voltage across the load has a small harmonic content. [0343] In some embodiments, an HPP correction (HPPC) functionality can be provided, to compute and apply a correction based on some or all of the foregoing effects that contribute to the stray current at the HPP node. In some embodiments, such an HPP correction can include a compensation for parasitic capacitance present at the HPP node. [0344] It is noted that if both voltage and capacitance are known on the HPP node, the amount of dynamic current that is strayed from the HPP node can be determined or estimated, and a compensating current to counteract such a current loss can be provided into the output current. It is also noted that the voltage on the HPP node is typically very close to the voltage on the HOR positive driver (HORP in Figure 28) minus the output current multiplied by the sense resistance Rs. Since the voltage across the sense resistance Rs is substantially the same as the desired drive signal, the capacitive current change caused by the voltage drop across Rs, similar to the capacitance across the load (110 in Figure 28), does not produce any significant amount of THD. Further, any small gain resulting therefrom can typically be ignored. Accordingly, knowing the voltage on the HOR positive (HORP) driver can be sufficient to determine or estimate a value of capacitive current that contributes to THD. [0345] In some embodiments, and as described herein, the voltage on the HOR positive (HORP) driver can be controlled by the PWM controller (1050 in Figures 7 and 8). Such a controller can select which drive voltage rails are selected during each PWM cycle. Additionally, and as shown in Figure 29, a supply voltage monitor (SVM) 1120 can be provided so that the voltage on the battery voltage rail is known when utilized. It is noted that with switching operations performed by the PWM controller, the HOR positive (HORP) driver is outputting a static voltage, ground during negative drive, or stepping to increase voltages during positive drive to follow an envelope of the output. The HORP driver typically performs PWM switching operation within the cycle when the waveform is at or near a zero crossing. As a result, the value of the voltage output by the HORP driver at the idle portion of each PWM cycle is sufficiently close to the cycle average HORP output, such that an error introduced by using the idle voltage to approximate the HORP voltage is negligible or sufficiently small. Accordingly, the HORP idle voltage can be utilized for approximating the current drive level and generating a desired compensation. [0346] With the foregoing estimation that the idle voltage of the HORP driver can be utilized to determine a correction, the level of charge at each of the possible idle voltages can be estimated. Then, whenever the idle voltage changes, a corresponding change in charge can be injected into the digital audio path to compensate for the current that strayed away from the load, and thus not seen by the load. [0347] In some embodiments, a look-up table (LUT) can be implemented to achieve the foregoing corrective charge estimation. Such a look-up table can be beneficial for minimized or reduced power consumption and complexity. For example, for each PWM drive voltage rail, a table of entry or entries can be initialized with values calculated by various system values; then, as the PWM controller changes HORP driver rails, the difference in these table values can be fed into the digital audio path and consequently the output. In some embodiments, all of the foregoing computation can be performed initially to allow run-time operations to be achieved efficiently and with lower power consumption. [0348] In some embodiments, the foregoing look-up table can include an HPPC entry as <hppc> = <charge in Coulombs> * <PWM frequency> * <sense resistance>, normalized to the max scale of the DAC (1044 in Figure 29). In the foregoing formula, <charge in Coulombs> can be calculated as <voltage in volts> * <capacitance in Farads> for a linear capacitor. For a non-linear capacitor, charge can be measured or estimated from a capacitance curve. [0349] Figure 29 shows a portion of a digital audio path 1042 having parts that are described in greater detail in reference to Figures 5 and 6. Figure 29 shows that in some embodiments, an HPPC block 111 can be provided in such a digital audio path to provide the foregoing HPP correction functionality. More particularly, the HPPC block 111 is shown to be implemented between the signal limiter 1146 and the DSM block 1146, and be coupled to the PWM controller 1050. [0350] As described herein, the PWM controller 1050 provides control signals to the H-bridge driver 1052 to provide an output signal at the HPP and HPN nodes based at least in part on the digital signal provided through the path 1043. In the example of Figure 29, the PWM controller 1050 is shown to be coupled to the supply voltage monitor (SVM) 1120 to, for example, obtain information about the supply voltages being utilized for driving of the H-bridge driver 1052. [0351] Thus, in some embodiments, a charge (<charge in Coulombs>) associated with an operating voltage can be obtained from the look-up table for a given operating configuration. In some embodiments, such a charge estimation can be achieved by the PWM controller 1050, the HPPC block 111, or some combination thereof. [0352] Figure 29 shows that in some embodiments, the HPPC block 111 can be configured to introduce a charge to the digital signal based on the charge estimate obtained in the foregoing manner. For example, the HPPC block 111 can be implemented between the signal limiter 1146 and the DSM block 1148 of the digital audio path 1042, such that the digital signal provided to the PWM controller 1050 (through the path 1043) includes the compensating injection of charge. [0353] It is noted that in the foregoing example of HPP compensation, the look- up table can be indexed by the voltage between the output of the HORP driver and the sense resistance. If a correction is enabled, it can be mixed into the audio signal just after the signal limiter block 1146 to thereby provide an improvement in THD+N performance. [0354] It is also noted that the PWM controller 1050 can be configured to control the voltage driven from the HORP, and the voltage across Rs is equal to the signal value, so the voltage on the HPP node (/^00 = /^120 + /23) can be determined with high accuracy. The parasitic capacitance presented to the HPP node can be from active devices, and thus can be voltage dependent. However, it will have a charge vs voltage curve. By determining the average HPP voltage during each cycle, the average charge on the capacitance can be determined for the cycle as well. [0355] For example, for every cycle, average stray current can be determined as a change in charge from the previous cycle. Thus, a lookup table can be implemented, indexed by the known voltage on the HPP node for each cycle, to determine the average charge during the cycle. [0356] At each cycle, a change in charge can be determined from subtraction, and that amount can be added to the digital audio path to counteract the missing stray current. At startup, the lookup table entries can be loaded with charge values based on a known charge vs voltage behavior of the ZOR driver plus the extra charge from board trace and/or other external devices. [0357] In some embodiments, the HPPC block 111 can be configured to include an ‘Enable’ bit, with a separate enable for a particular HOR mode. In some embodiments, a correction can be executed only in full HOR mode and in intermediate Rout mode corresponding to the particular HOR mode. In some embodiments, a correction applied in a single cycle can be configured to not exceed a certain signal level as set by a user programmable register. In some embodiments, a correction can be configured to not cause an overflow in the signal or in the loop filter. In some embodiments, a correction can be configured to not cause signal to exceed DSM overload threshold. [0358] In some embodiments, an on-chip parasitic capacitance at the HPP pin can be measured and stored in, for example, an OTP during a testing stage. [0359] In some embodiments, a charge vs voltage curve for an on-board capacitor can be determined during or for an application process. During or for such an application process, an HPPC value stored in the OTP can be read out, and using such a value can be utilized to scale the charge at LUT index voltages. Such scaled values can be written back into respective LUT registers. [0360] In some embodiments, and as an example, the PWM controller can be configured to drive HORP using one of six voltage rails. The idle HORP voltage can be obtained from the PWM controller. Each voltage (and subrange for VBAT) can have a LUT entry which is the HPPC charge. These entries can be in scaled AUDAC values. [0361] In some embodiments, the charge level can be obtained from a LUT indexed by the HORP voltage reported by the PWM controller. The correction can then be computed as the change in the charge from the previous cycle. [0362] In some embodiments, a maximum correction of max1cycle_corr can be applied in a single cycle. The remaining correction can be stored in a register corr_acc, which accumulates subsequent corrections. In this manner, the correction in every cycle can be limited by max1cycle_corr, and a larger correction can be applied over multiple cycles until the register empties out. Feature 6 [0363] As described herein, a pulse width modulation (PWM) controller can receive an input signal at an input node and generate gate driving pulse signals for an H-bridge driver. Such driving of the H-bridge driver generates an amplified output signal at an output node, and the output signal can drive a speaker to generate sound waves. [0364] Figure 30 depicts an audio amplifier 50 such as a PWM amplifier. In such an amplifier, the foregoing PWM controller is indicated as 104, and the H-bridge driver is depicted as 106. The H-bridge driver 106 is shown to be configured such that the gate driving pulse signals are provided to the gates of first and second transistors M1, M2. Such driving of the transistors M1, M2 generates an amplified output signal at an output node 108, and the output signal is shown to drive a speaker 112 to generate sound waves. The speaker 112 is shown to be coupled to the output node 108 through a low-pass filter having inductance Lf and capacitance Cf. The low-pass filter and the speaker 112 are collectively indicated as a load 110. [0365] In the example of Figure 30, a feedback circuit including a feedback path 130 and a control loop circuit 114 is shown to be implemented between the output node 108 and an input node 102 of the PWM controller 104. [0366] Figure 31 shows an example of the feedback path and control loop circuit (130, 114) of Figure 30. In such an example, the amplified signal is shown to be obtained from the output node 108 and provided to the PWM controller 104 through a loop filter 132, an ADC 134, and a digital filter 136. To accommodate such a fully amplified signal that can include high amplitudes, the ADC 134 needs to have a relatively high dynamic range to accommodate high-amplitude signals even if the amplified signal has a low amplitude (e.g. at or near silence). Additionally, the foregoing dynamic range requirement may even be higher due to effects of the digital filter, and/or needed headroom for saturation detection. [0367] Figure 32 shows that in some embodiments, an audio amplifier 100 such as a PWM amplifier can include a feed-forward circuit 140 for a digital input signal, such that the digital input signal is provided to a PWM controller 104 from an input node 101. In the example of Figure 32, the PWM controller 104 generate gate driving pulse signals for first and second transistors M1, M2 of an h-bridge driver 106, similar to the example of Figure 30. Such driving of the transistors M1, M2 generates an amplified output signal at an output node 108, and the output signal can drive a speaker 112 to generate sound waves. The speaker 112 is shown to be coupled to the output node 108 through a low-pass filter having inductance Lf and capacitance Cf. The low-pass filter and the speaker 112 are collectively indicated as a load 110. [0368] In the example of Figure 32, a feedback circuit including a feedback path 130 and a control loop circuit 114 is shown to be implemented between the output node 108 and the PWM controller 104, similar to the example of Figure 30. [0369] In some embodiments, the feed-forward and feedback circuit configuration of Figure 32 can allow implementation of the audio amplifier 120 (1022 in Figures 5 and 7) where an error estimation signal obtained with the feedback circuit 130/114 is a much smaller signal than the fully amplified signal that is used for the feedback circuit of Figure 30. [0370] Referring to Figure 32, since the error estimation signal is much smaller than the full amplified signal (of Figure 30), an ADC utilized in the control loop 114 of Figure 32 can be configured with a lower dynamic range when compared to the ADC 134 of the control loop 114 Figure 30. Accordingly, the ADC of Figure 32 can be implemented to be smaller and/or consume lower amount of power. [0371] In some embodiments, the foregoing error estimation signal can be obtained by comparison of a reference signal representative of the digital input signal with a feedback signal representative of the amplified signal. In some embodiments, the error estimation signal can include filtering, and such filtering can be changed to optimize the system performance at different levels. For example, at low signal levels, the error estimation signal can be tuned to match a noise transfer function of the system, such that PWM levels are reduced to save power and to lower system noise contributions from PWM activity. In another example, at higher driver levels, the error estimation signal can be tuned to match an expected output to minimize ADC levels to improve dynamic range and reduce effects of loop filter non-linearity. [0372] Figure 33 shows an example of an architecture of an audio amplifier 100 that can be implemented to provide the feed-forward functionality of Figure 32. In the example of Figure 33, a feed-forward circuit 140 is shown to be implemented as a signal path 140 from a node 102 to the PWM controller 104. Thus, an input signal delivered to the PWM controller 104 through the feed-forward circuit 140 is a digital signal to be utilized by the PWM controller 104. In some embodiments, and as described herein, the PWM controller 104 can generate control signals for the H-bridge driver 106 based mostly on the digital input signal delivered through the feed-forward circuit 140. [0373] In the example of Figure 33, and as described herein, a reference signal can be utilized to compare against an amplified signal from the output of the H-bridge driver 106. Such a reference signal can be obtained by routing the digital signal from the node 102 (where the feed-forward signal is routed to the PWM controller 104), through a DSM block (1148 in Figure 6), and through DEM block (1150 in Figures 6 and 7) and ADC (1044 in Figures 6 and 7). [0374] In the example of Figure 33, and as described herein, a feedback signal to be compared with the reference signal can be obtained from the amplified signal the output of the H-bridge driver 106, passed through a feedback resistance network (1080 in Figure 7). Then, the comparison of the reference signal and the feedback signal can provide an error estimation signal. [0375] Referring to Figures 7 and 33, such an error estimation signal can be provided to the PWM controller (104 in Figure 33 and 1050 in Figure 7) through a loop filter (1046 in Figure 7) and a SAR ADC (1048). In some embodiments, the output of the SAR ADC can be provided to a digital loop filter (1162 in Figure 7) before being added with the digital input signal provided through the feed-forward path (140 in Figure 33 and 1043 in Figure 7). Thus, one can see that such an addition of the error estimation signal with the digital input signal allows the digital input signal to be adjusted accordingly to generate an output from the H-bridge driver that is a better representation of the digital input signal. [0376] It is noted again that comparison of the reference signal (that is based on the digital input signal) with the feedback signal (that is based on the output signal and scaled appropriately by the feedback resistance network) allows the error estimation signal to be relatively small, thereby providing a number of desirable features. For example, and as described above, the SAR ADC in the feedback circuit can be desirably configured with a smaller dynamic range without sacrificing performance. Feature 7 [0377] As described herein, an audio amplifier such as the audio amplifier 1000 of Figures 5 and 7 includes a feedback loop circuit from an output (HPN and HPP nodes) of an H-bridge driver 1052 to an input of the H-bridge driver 1052 through a PWM controller 1050. Such a feedback loop circuit can support providing of a desired signal at the output of the H-bridge driver 1052 for driving a speaker, based on a reference signal. [0378] Figure 34 depicts an audio circuit 100 that includes an audio amplifier 120 that can be similar to the PWM amplifier 1022 of Figures 5 and 7. It is noted that while various examples related to the audio circuit 100 are described in the context of the audio amplifier 120 being a Class D PWM audio amplifier, it will be understood that one or more features of the present disclosure can also be implemented with other types of amplifiers. [0379] In the example of Figure 34, and as described herein, a pulse width modulation (PWM) controller 104 (1050 in Figures 5 and 7) of the PWM amplifier 120 can receive a digital input signal at an input node 102 and generate driving pulse signals for an H-bridge drier 106 (1052 in Figures 5 and 7) that is depicted as having first and second transistors M1, M2. More particularly, the driver 106 is shown to include a PMOS device (M1) having its source coupled to a supply voltage (VDD) node and its drain coupled to the drain of an NMOS device (M2). The source of the NMOS device is shown to be coupled to a ground. Configured in the foregoing manner, an input signal can be provided to each of the gates of the PMOS and NMOS devices, and the gates can be controlled to generate the output pulses. [0380] Such driving of the transistors M1, M2 generates an amplified output signal at an output node 108, and the output signal can drive a speaker 112 to generate sound waves. The speaker 112 is shown to be coupled to the output node 108 through a low-pass filter having inductance Lf and capacitance Cf. The low-pass filter and the speaker 112 are collectively indicated as a load 110. [0381] It is noted that without any compensation, the inductance of the load in foregoing speaker-driving configuration can lead to significant differences in an open- loop frequency response at high frequencies (e.g., greater than 100 KHz) between HOR and ZOR modes of operation. Such an effect is due to the current-mode drive of the sense resistance (Rs in Figures 5 and 7) resulting in frequency dependent impedance of the load inductance during the HOR mode of operation. [0382] It is further noted that the PWM loop as described herein performs well in the ZOR mode. In the HOR mode, a compensation can be implemented to provide improved performance. Examples related to such a compensation are described herein. [0383] In the example of Figure 34, a feedback circuit 114 is shown to be provided between the output node 108 and the input node 102. In some embodiments, such a feedback circuit can include a compensation circuit having one or more features as described herein. [0384] Figure 35 shows a feedback circuit 114 that can be a more specific example of the feedback circuit 114 of Figure 34. In Figure 35, the H-bridge driver of the PWM amplifier 120 is shown to drive the load 110 through HPP and HPN nodes. Accordingly, the HPP node is shown to provide pulses having an amplitude Vsupply (VDD in Figure 34), the HPN node is shown to be at zero volt. Such HPP and HPN nodes are shown to be coupled to respective nodes (1081, 1083 in Figure 7) through feedback resistances RFB, RFB (e.g., Rh2 and Rz_n in Figure 7). [0385] Referring to Figures 7 and 35, the nodes 1081, 1083 are shown to be coupled to a common-mode-limit (CML) amplifier 130 (1082 in Figure 7), as well as to a DAC (1046 in Figure 7) for receiving of a reference current (Iin+ and Iin-) representative of the input digital signal. In some embodiments, the common-mode-limit (CML) amplifier 130 can be configured to provide a high bandwidth input common mode regulation loop. [0386] The foregoing regulation loop can be utilized to convert single ended step currents from the output nodes into differential currents to minimize or reduce error in the PWM amplifier. However, such a common mode regulation loop on the input side of the feedback loop can present a series load capacitance for the output side of the feedback loop. [0387] In some embodiments, the foregoing high bandwidth input common mode regulation loop can be compensated providing an additional phase change (e.g. an additional phase lead) with a low bandwidth output common mode loop along the feedback loop of the PWM amplifier 120. [0388] Referring to Figure 35, it is noted that the high bandwidth common mode regulation loop is typically utilized to convert single ended step currents from the H- bridge feedback into differential currents to minimize or reduce an error in the PWM amplifier. Stability requirements of the loop can limit the achievable high bandwidth required or desired for a fast step response. [0389] It is further noted that existing solutions include standard compensation techniques such as Miller compensation and feedforward compensation. Miller compensation typically requires additional components such as capacitors of the same order of magnitude as integrator capacitors that consume additional area and additional power to drive large capacitors. Feedforward compensation typically requires additional parallel amplifier path, which adds complexity. [0390] Figure 35 shows that in some embodiments, the high bandwidth input common mode loop 130 can be compensated by utilizing a closed loop impedance of a low bandwidth output common mode loop 134. [0391] It is noted that in a PWM amplifier, an output common mode regulation loop can correct for errors in a low bandwidth integrator output, hence the bandwidth requirement of the output common mode loop can be relaxed. [0392] In the example of Figure 35, the closed loop impedance of the output common mode loop 134 appears in series with the load capacitance of the input common mode loop 130. Such an arrangement can be utilized to provide a phase change, such as a phase lead (depicted as 132 in Figure 35), for the input common mode loop 130, which therefore provides a large degree of freedom to increase the bandwidth of the input common mode loop 130 while keeping the loop stable over a wide frequency range. [0393] In the example of Figure 35, the input common mode loop 130 is shown to include first and second transconductance opamps gm1i and gm2i arranged in a loop. More particularly, the nodes (1081, 1083 in Figure 7) that are coupled to the HPP and HPN nodes through the feedback resistances RFB, RFB (e.g., Rh2 and Rz_n in Figure 7) are shown to be coupled to respective first and second nodes of the input common mode loop 130. Sampled currents (ICM) from such first and second nodes are shown to be provided to the first transconductance opamp gm1i as inputs, and an output of gm1i is shown to be provided to the second transconductance opamp gm2i as an input. The second transconductance opamp gm2i is shown to provide first and second outputs that are coupled to the respective first and second nodes, thereby forming the input common mode loop 130. [0394] In some embodiments, the foregoing input common mode loop 130 can be implemented as part of the common-mode-limit (CML) amplifier 1082 in Figure 7, as a separate circuit, or some combination thereof. [0395] In the example of Figure 35, the output common mode loop 130 is shown to be implemented to provide inputs to an assembly of filter (1162 in Figure 7) and PWM controller (1150 in Figure 7). More particularly, the nodes (1081, 1083 in Figure 7) that are coupled to the first and second nodes of the input common mode loop 130 are shown to be coupled to respective first and second nodes of the output common mode loop 130 through a transconductance opamp 133. For the transconductance opamp 133, each of the two ouputs (von1, vop1) is shown to be coupled the respective input through a feedback capacitance Cin. [0396] In the example of Figure 35, the output common mode loop 134 is shown to include first and second transconductance opamps gm1o and gm2o arranged in a loop. More particularly, the first and second output nodes of the transconductance opamp 133 are shown to be coupled to respective first and second inputs of the first transconductance opamp gm1o, and an output of gm1o is shown to be provided to the second transconductance opamp gm2o as an input. The second transconductance opamp gm2o is shown to provide first and second outputs that are coupled to the respective first and second nodes, thereby forming the output common mode loop 134. [0397] In the output common mode loop 134 of Figure 35, each output of gm2o is shown to be coupled to the common input through a feedback capacitance Cc. [0398] In some embodiments, the foregoing output common mode loop 134 can be implemented as part of the DLF block 1162 in Figure 7, as a separate circuit, or some combination thereof. Feature 8 [0399] A bandgap reference circuit is utilized in many electronic applications where a constant reference voltage is required or desired. Such a bandgap reference circuit typically requires a startup circuit, since it has two stable bias points, a desired reference voltage and an all-off voltage. [0400] A startup circuit typically senses an all-off condition, injects a current to a main bandgap core circuit, and shuts itself off after the main core reaches a desired bias point. A typical startup circuit has a very narrow margin between injecting current and shutting itself off completely. [0401] Sometimes, with mismatches and at extreme process-voltage- temperature (PVT) corners, an undesired leakage current can be injected which causes an error in the output reference voltage. The injected current can also cause a condition that causes a bandgap reference circuit to be stuck in low output voltage condition. [0402] It is noted that because a bandgap reference circuit is a self-biasing circuit, a design for safe operating margin is made difficult by a wider range of operating voltages and conditions than other circuit blocks. [0403] To confirm that there is enough margin between the startup circuit’s on- time and the main core’s on-time, PVT and mismatch simulations can be run. The startup circuit is typically designed to provide enough injected current to kick the bandgap core circuit away from a potential stuck state at low bias currents, and sufficiently shut off to minimize injected error currents. [0404] Figure 36 shows an example of a conventional bandgap reference circuit 10 having a startup circuit 12. In such an example, the startup circuit 12 is shown to include transistors M6, M7, M8, M9. The transistor M9 senses the state of the bandgap reference circuit 10 with its gate connected to the output of OPA1. On startup, the OPA1 output is low and M9 is in the off condition. M6 and M7 pull the gate of M8 high to cause M8 to pull node B to low. Hence, M8 injects a current into node B to kick start the bandgap reference circuit 10. [0405] With the kick start bias current, the main bandgap loop including OPA1 enters an operating condition and drives M4 to take over from the startup current injected by M8. As the bandgap reference starts up and approaches the target output voltage, M9 is turned on and shorts out Vgs of M8 to turn off the startup injected current. [0406] It is noted that in the example of Figure 36, the startup circuit 12 can be problematic, since M9 needs to be designed around the strength of the M6 and M7 pull up devices. If M9 is too strong relative to the strength of the M6 and M7 load, the startup circuit 12 may start to shut off early before the bias currents in the main bandgap loop is able to take over from the injected startup current at node B. Under such a condition, the bandgap reference may get stuck in a low-bias state. If M9 is too weak relative to the strength of the M6 and M7 load, then it may be too weak to sufficiently turn off M8 in the operating condition, and M8 may inject a significant error current. [0407] Compounding the challenge of designing sufficient margins is that the bandgap reference usually has to operate over extended supply voltages and the relative strength of M9 to the M6, M7 load is highly dependent on supply voltages. Since it is desired to minimize startup circuit quiescent power loss, the current through M6, M7 and M9 is preferably kept low. Hence, the Vgs voltage to turn on M9 may be very low and it may be possible for M9 to turn on to begin shutting down the startup injected current before M4 is able to turn on to take over the bias currents. [0408] Figure 37 shows a bandgap reference circuit 100 having a startup circuit generally indicated as 110. In the example of Figure 37, the startup circuit 110 implemented as a low supply bandgap core can be based on a ‘Vreffast’ voltage, which is a linear and PVT-insensitive voltage. [0409] Referring to Figure 37, the startup circuit 110 injects a current to the node ‘ns’ at the gate of M3, and also an output of an opamp 112 of the main core, through a PMOS Mstartup (with its source coupled to a supply voltage (VDD) node and its drain coupled to the ‘ns’ node), when the main bandgap core is off (I = I1 = I2 = 0). Once the voltage at Vreffast exceeds the threshold voltage Vt of Mniv_strtup, the Vstrtup voltage goes down and Mstartup turns off completely. Vreffast voltage is substantially linear and PVT-insensitive, so the startup off voltage is only dependent on Vt of Mniv_strtup voltage. [0410] In Figure 37, the Vreffast voltage node is shown to be coupled to the supply voltage (VDD) node through a PMOS Mcref, such that the source of Mcref is coupled to the supply voltage (VDD) node and the drain is coupled to the Vreffast voltage node to provide a current I2 to the Vreffast voltage node. The Vreffast voltage node further shown to be coupled to ground through a parallel combination of capacitance Cfast and resistance Rfast. [0411] In Figure 37, the node with the voltage Vstrtup is shown to be between NMOS Mna (with its gate coupled to source) and NMOS Mniv_strtup, such that the drain of Mna is coupled to the supply voltage (VDD) node, the source of Mna is coupled to the drain of Mniv_strtup through the Vstrtup node, and the source of Mniv_strtup is coupled to ground. [0412] Since Vreffast is an output of the reference circuit, the voltage in which the startup circuit shuts off is well controlled and can be designed to be substantially higher than in the example of Figure 36. For example, Vrelffast node is shown to be coupled to the ‘ns’ node through a capacitance Ccomp and the parallel combination of capacitance Cfast and resistance Rfast. Some or all of such capacitances and resistance can be selected to provide control of the voltage Vrelffast. [0413] It is noted that even if there is some leakage from Mstartup after the main bandgap core is fully on, there is minimal effect to the main core current ‘I.’ Hence, there is no risk of injecting an error current into the main bandgap loop in the operating condition. [0414] It is noted that the startup circuit 110 of Figure 37 can provide a much more precise startup off condition than that of the startup circuit of Figure 36. Further, the startup circuit function can be much more robust to allow more reliable startup under wider range of conditions, without excessive power consumption in the startup circuit, and with a lower risk of injecting a current that can induce an error in the reference output voltage. These characteristics are particularly important in low-power applications where excessive startup circuit quiescent current consumption is highly undesirable, and the operating bias current of the main bandgap loop needs to be kept low. In these low-current applications, it can be very difficult to achieve robust startup circuit margins with conventional bandgap reference circuits, such as the example of Figure 36. [0415] In some embodiments, a bandgap reference circuit having a startup circuit as described herein can be implemented for one or more functional blocks of an audio amplifier circuit such as the audio amplifier circuit 1000 of Figure 5. For example, and referring to the example of Figure 5, the power management block 1024 includes a reference (Ref) block 1110. Such a reference block can be implemented as a low voltage, low power bandgap reference circuit configured to operate with a supply voltage (e.g., VDD_B) to produce a low reference voltage as an output. As described herein, such a reference voltage can be utilized for operation of an analog LDO regulator 1112 and a digital LDO regulator 1114, as well as other functional blocks of the audio amplifier circuit 1000. Feature 9 [0416] A PWM amplifier as described herein can be configured to operate with multiple supply voltages to provide desired performance for both low and high level signals. For example, the H-bridge driver 1052 of the PWM amplifier 1022 in each of Figures 5 and 7 is shown to be provided with supply voltages VBAT, VDD_A, VDD_B, VDD_D and VDD_E, with VBAT > VDD_A > VDD_B > VDD_D > VDD_E. In such an example PWM amplifier, the four larger voltages (VBAT, VDD_A, VDD_B, VDD_D) can be obtained from one or more external sources, and the smallest voltage (VDD_E) can be obtained from an internal source. [0417] In some embodiments, the foregoing internal source voltage (VDD_E) can be obtained from a low voltage monitor (LVM) block indicated as 1132 in each of Figures 5 and 7. In some embodiments, such a voltage (VDD_E) can be provided to the H-bridge driver 1052. In some embodiments, the voltage VDD_E can also be provided to an external location through a voltage node indicated as VDD_E. [0418] Figure 38 shows a circuit diagram of a low voltage system 100 that can be utilized in an audio amplifier having one or more features as described herein. In some embodiments, such a system can include a low voltage monitoring circuit 102 (1132 in Figure 7), a controller 110 (1050 in Figure 7), an H-bridge driver circuit 112 (1052 in Figure 7), and a capacitor C. As described herein, such a system can allow low voltage operation of an audio amplifier, such as the PWM amplifier 1022 of Figure 7, without a need for an external low voltage supply. It will be understood that while various examples are described herein in the context of such a PWM amplifier, one or more features of the present disclosure can also be implemented with other types of amplifiers, including other types of audio amplifiers. [0419] In Figure 38, the H-bridge driver 112 is shown to be provided with a supply voltage VDD1. As described herein, such a voltage (VDD1) can be the lowest supply voltage (VDD_E in Figure 7). In some embodiments, such a supply voltage (VDD1) can be maintained with use of the capacitor C and charging/discharging of the capacitor C based on monitoring of the supply voltage VDD1 as described herein. [0420] Figure 38 shows that in some embodiments, the low voltage monitoring circuit 102 can include a comparator 106 that compares a voltage at an output node 120 of a P/N driver 104 with a reference voltage Vref. The output node 120 is also shown to be connected to the supply voltage node VDD1. [0421] In Figure 38, the P/N driver 104 is shown to include an arrangement of a PMOS device having its source coupled to a supply voltage (VDD2) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. The gate of the PMOS device is shown to be provided with a control signal UP, and the gate of the NMOS device is shown to be provided with a control signal DN. Thus, the P/N driver 104 can provide an output voltage at the node 120 based on the control signals UP and DN. [0422] In the example of Figure 38, the supply voltage VDD2 for the P/N driver 104 is greater than the supply voltage VDD1. [0423] Referring to Figure 38, an output of the comparator 106 is shown to be provided to the PWM controller 110. Such a controller is shown to provide the UP and DN control signals to the P/N driver 104 based on the output of the comparator 106. [0424] In Figure 38, the PWM controller 110 is also shown to provide control signal Ctrl_R for controlling a resistance R of a variable resistor of a reference voltage circuit. Such a reference voltage circuit is shown to include a current source 108 coupled to ground through the resistor R, with the reference voltage Vref being obtained from a node between the current source 108 and the resistor R. [0425] In Figure 38, the PWM controller 110 is also shown to provide a control signal (PWM code) to the H-bridge driver 112. The H-bridge driver 112 is shown to be coupled to the supply node VDD1 (which is also the output node 120 of the P/N driver 104) so as to allow the speaker 114 to be driven according to the control signal (PWM code). [0426] In Figure 38, the capacitor C is shown to couple the output node 120 of the P/N driver 104 to ground. In some embodiments, the capacitor C can be an external capacitor that is outside of a die having the PWM amplifier. In some embodiments, the capacitor C can be implemented as part of a die having the PWM amplifier. [0427] Configured in the foregoing manner, the low voltage system 100 of Figure 38 can provide a low voltage supply for use in low level operation of the H-bridge driver 112. Such a functionality reduces the power consumption associated with regulation of a low voltage, since the power that would normally be lost in regulation is output to the load instead. It is noted that PWM Class D operation on a low supply reduces switching losses proportional to CV ² , and also reduces noise in the system. [0428] In the system 100 of Figure 38, low voltage regulation can be achieved by monitoring the voltage on the capacitor C (at the output node 120) and configuring switching operations of the H-bridge driver 112 to charge or discharge the capacitor C, depending on whether the monitored voltage is higher or lower than a selected value representative of a desired value for the supply voltage VDD1. Such a selected value can be programmable and/or dynamic if desired. In some embodiments, a programmable selected value can allow control of an idle output common mode of the amplifier. [0429] As described herein, the low voltage monitoring circuit 102 monitors the voltage of the capacitance C at the output node 120 to determine if it is higher or lower than the reference voltage Vref. In some embodiments, such a reference voltage can be a voltage from a software controllable reference source. [0430] In an example operation, during each PWM cycle, the programmable reference voltage can be stepped to track the voltage on the capacitor C in real or approximately real time. The reference voltage Vref can be realized with a fixed current into the variable resistance R that, in some embodiments, can be implemented as a programmable resistor ladder; and such a fixed current through the resistance R can generate the reference voltage Vref being provided to the comparator 106. [0431] If the voltage on the capacitor C is high, next output pulse can be generated by connecting the load between the capacitor C and ground, thereby reducing the voltage on the capacitor C. If the voltage on the capacitor is low, the next output pulse can be generated by connecting the load between the capacitor C and the lowest available supply (VDD1), thereby increasing the voltage on the capacitor C. [0432] In some embodiments, an extension on the foregoing operation can add a programmable amount to any “charge pulse” to deliver more charge to the capacitor C per pulse, which improves the ratio of charge delivered vs power dissipated switching the output stage. [0433] In the example of Figure 38, the foregoing charging and discharging of the capacitor C can be achieved by application of the respective pulses (e.g., PWM codes) to the H-bridge driver 112. Accordingly, the charging and discharging of the capacitor C to maintain a desire value of the supply voltage VDD1 are collectively indicated as 122. [0434] Figure 39 shows the low voltage system 100 of Figure 38 being operated with specific example settings. In Figure 39, the capacitor C has a capacitance value of approximately 300nF, the PMOS device has an effective resistance of approximately 200 ohm, and the NMOS device has an effective resistance of approximately 25 ohms. [0435] Figure 40 shows examples of various signal traces during the operation of the low voltage system 100 of Figure 39. [0436] Referring to Figures 39 and 40, examples of switching operation can involve some or all of the following situations. If a positive drive is needed and the capacitor C needs to be charged, the amplifier’s positive output (out+) can be connected to the lowest available external supply, and the negative output (out-) can be connected to the capacitor C. In Figure 40, such an operating configuration is depicted on the left side of the charging case, where the example lowest available external supply is VDD_D, with VDD_D > VDD_E. [0437] If a negative drive is needed and the capacitor C needs to be charged, out- can be connected to the lowest available external supply, and out+ can be connected to the capacitor C. In Figure 40, such an operating configuration is depicted on the right side of the charging case. [0438] If a positive drive is needed and the capacitor C needs to be discharged, out+ can be connected to the capacitor C, and out- can be connected to ground. In Figure 40, such an operating configuration is depicted on the left side of the discharging case. [0439] If a negative drive is needed and the capacitor needs to be discharged, out- can be connected to the capacitor C, and out+ can be connected to ground. In Figure 40, such an operating configuration is depicted on the right side of the discharging case. [0440] In some situations, the system may require additional decision making criteria, not all switching options may be available at all times, and the low voltage operation cannot be guaranteed to stay within regulation limits over all conditions. To ensure that the supply voltage stays within a desired range, a pullup or pulldown switch can be activated to return the system to regulation. [0441] In some embodiments, if the pullup or pulldown is activated for too many cycles in a row, the system can be assumed to have lost regulation. In such a situation, the low voltage operation can be automatically disabled, and the lowest externally available supply can be utilized. [0442] In some situations, there may be output conditions that move the voltage on the capacitor C faster than the reference can track. In some embodiments, a modified mode of the low voltage system can allow the reference to be moved by more than one code per cycle in order to track the voltage when high current is in the load. If the code needs to change in the same direction for a programmable number of consecutive cycles, the modified mode can be enabled and the code can be changed by a programmable amount each cycle until the reference catches up. Feature 10 [0443] As described herein, a digital signal is provided to a PWM controller as a feed-forward signal; and the PWM controller generates a control signal that drives an appropriate portion of an H-bridge driver. The digital signal is also converted into an analog signal, and such an analog signal is utilized as a reference signal that is compared to a feedback signal from the output of the H-bridge driver. Figure 7 includes examples related to processing of such feed-forward and analog signals. More particularly, the foregoing analog signal can be generated by a digital-to-analog converter (DAC) 1044 based on a digital signal provided to it from a dynamic element matching (DEM) block 1150. The DEM block 1150 is shown to be a part of a digital logic circuit 1020, and more particularly, a digital audio path (1042 in Figure 6) of the digital logic circuit 1020. [0444] Referring to Figure 6, the feed-forward digital signal is shown to be provided to the PWM controller through a path 1043, from a node upstream of a delta sigma modulator (DSM) 1148. A digital signal is also shown to be provided to the DSM 1148, and a digital output of the DSM 1148 is shown to be provided to a DEM block 1150. A digital output of the DEM block 1150 is shown to be provide to a DAC 1144 through a path indicated as 1045. [0445] Configured in the foregoing manner, the DSM block 1148 can be configured to re-modulate a higher-bit input signal (e.g., 24-bit signal), through delta- sigma modulation, into a lower-bit signal (e.g., 9-bit signal) that is appropriate for the DEM block 1150. Accordingly, the example 9-bit DSM output signal drives the DEM block 1150 which can be implemented as a digital block configured to, for example, randomize a pattern of 512-bit cell drive to the DAC 1044 in a manner to linearize the DAC’s response for use as a multi-bit delta-sigma DAC. Such a configuration can provide a desirable reference audio signal for the closed-loop circuit described herein. [0446] Figure 41A depicts a digital-to-analog converter (DAC) 10 having N-bit resolution, where N is a positive integer. Accordingly, the DAC 10 can be referred to as an N-bit DAC. Such a DAC includes an array 12 of N bit cells 14a, 14b, 14c, etc., and each bit cell is provided with a voltage V and a control signal b0, b1, b2, etc. Each cell includes a set resistance and a switch, under the control of the respective control signal, that allows the voltage node (V) to be connected to a common node 16 through the resistance. Depending on the type of DAC, there may be a resistance between neighboring bit cells. [0447] Configured in the foregoing manner, each bit of a digital signal presents either no voltage or a resistance-reduced voltage from the corresponding bit cell to an adder circuit 18 to generate an analog output voltage value Vout representative of the digital signal. [0448] For the purpose of description, Figure 41B depicts the DAC 10 of Figure 41A in a block form. More particularly, an N-bit cell array 12 is assumed to include N bit cells as described in reference to Figure 41A, and N-bit data being applied to the N-bit cell array 12 is assumed to include control signals for the N bit cells. Similarly, a voltage V being provided to the N-bit cell array 12 is assumed to be distributed to the N bit cells. [0449] For example, Figure 42A shows an example where a DAC 10 is a 3-bit DAC, such that an array 12 includes bit cells 14a, 14b, 14c. Each bit cell is shown to be provided with a voltage V and a respective control signal (b0, b1, b2). An output of each bit cell is shown to be coupled to a common node 16 which is coupled to an adder circuit 18 to generate an analog output signal Vout. [0450] In the block form of Figure 42B, the array 12 is indicated as a 3-bit cell array, and the control signals for the three bit cells are indicated as 3-bit data. [0451] It is noted that the DACs of Figures 41 and 42 are examples of fixed bit DACs where the number of bit cells is fixed for each DAC. Accordingly, all of the bit cells in a given DAC are operable. [0452] Figure 43 shows that in some embodiments, a DAC 100 can include a variable bit cell array size. In some embodiments, such a DAC having variable bit cell array size can be utilized as the DAC 1044 of Figures 5 to 8. [0453] In electronic applications such as audio signal processing applications, low power and space constrained DACs typically use small (low resolution) bit cell arrays. DACs with large arrays bit cells can be implemented to obtain high resolution; however, such implementations result in challenges such as larger size requirement, higher noise, and increased quiescent power consumption. [0454] In some embodiments, a DAC architecture having a telescoping functionality can be implemented to allow dynamic adjustment of the DAC’s cell population being used. In such an architecture, a large DAC array can be enabled and utilized without the permanent presence of the foregoing challenges. [0455] For the purpose of description, the foregoing DAC architecture having a telescoping functionality also may be referred to herein as a dynamic element matching (DEM) DAC or a telescoping DEM DAC. [0456] Figure 43 depicts a DAC 100 having an array 102 of N bit cells, where the quantity N is a positive integer that can vary between a lower limit Nlow to an upper limit Nhigh so as to provide a telescoping functionality indicated as an arrow 106. For a given value of N, N cells of the array 102 can be operated by application of a voltage V and an N-bit data, so as to provide (arrow 104) respective voltages to an adder 108 to generate an analog output signal. [0457] In some embodiments, various functionalities, including the telescoping functionality, can be controlled and/or supported by a controller 110. Examples of such control functionalities are described herein in greater detail. In some embodiments, such a controller can be a part of the DAC 100, be external to the DAC 100, or some combination thereof. [0458] It is noted that operationally, a DAC having a large fixed array can also suffer from band artifacts when too few cells are being activated on average in quiescent conditions compared to the total cell population. In some embodiments, a DAC architecture (such as the DAC 100 of Figure 43) having a telescoping functionality can provide dynamic array population control that pushes the foregoing band artifacts out of band by utilizing only a small set of cells at low levels associated with quiescent conditions. [0459] It is also noted that a high resolution DAC array typically uses more power to overcome various implementation challenges. On the other hand, a low power design typically has low resolution. Thus, pushing DEM artifacts out of band can be achieved by either adding out of band signal to the DAC codes or biasing some number of cells to be always on; however, each of such approaches increases power consumption. [0460] In some embodiments, the DAC architecture 100 of Figure 43 can be configured to use a dynamic subset of the array 102 of DAC bit cells. For example, at low output levels, only a small subsection of the array 102 are utilized. In such a configuration, most of the analog circuitry can be shut off, and most of the digital circuitry can be static to reduce current. [0461] When a signal requires more cells than are currently available, additional cells can be added to the active population along with their corresponding digital control circuitry. This allows use of a high precision DAC array while maintaining low quiescent current and eliminating or reducing DEM artifacts in the audio band. [0462] Increasing or decreasing the DAC cell population also changes the gain of the DAC. In some embodiments, either or both of time and level hysteresis can be utilized to avoid or reduce audible artifacts from dynamically changing the active cell population. [0463] In some embodiments, active cell population is not increased until a telescope threshold is exceeded for a programmable number of cycles, to avoid population chatter due to noise occasionally exceeding the threshold. In some embodiments, active cell population is not decreased until a signal peak remains below a telescope threshold for a programmable time to guarantee that a constant AC signal will not change the population size cycle to cycle and produce total harmonic distortion. [0464] In some embodiments, the DAC architecture 100 of Figure 43 can be configured such that the DEM functionality is accomplished with a variable length barrel shifter that drives a scrambling network. Barrel shifter operation can enforce an order on bit cell usage resulting in bit cell mismatch noise to be pushed out of band. The scrambling network can occasionally randomize the cell order to reduce tones and other artifacts caused by the barrel repeat rate. [0465] In some embodiments, the scrambling network can be implemented as a butterfly or Benes network fed by a linear-feedback shift register (LFSR). An output of the LFSR and its compliment can be distributed to randomize all of the switches in the scramble network. The LFSR can be clocked at a programmable time interval to set the randomization period. [0466] Referring to Figures 43 and 5 to 8, it is noted that in some embodiments, the DAC (100 or 1044) can be implemented as an 8-bit plus sign delta-sigma modulated DAC to produce a reference audio signal for the loop circuit of the PWM amplifier (1022 in Figure 7). Such a DAC preferably operates with very low noise and support a high dynamic range, with low distortion to meet a high performance THD specification, and with low power consumption to meet a low quiescent power specification. In some embodiments, a 512-unit cell having telescoping architecture as described herein can be utilized. [0467] In some embodiments, a DAC having a telescoping set of unit bit cells as described herein can be configured to operate in one of a number of modes. For example, four modes can be implemented, where a first mode utilizes the least amount of the unit bit cells, and second to fourth modes utilize successively greater numbers of unit bit cells. In the lowest telescope mode (first mode), the fewest current bit cells are active; and in the highest telescope mode (fourth mode in the 4-mode example), the most current bit cells are active. In some embodiments, the amplitude of the input signal and the audio operating mode can control which telescope mode the DAC is in at any given time. [0468] It is noted that for a given number of current bit cells in a DAC (e.g., 512 total bit cells for an 8-bit plus sign input), the bit cells match with each other to only a certain level. Thus, if such bit cells are addressed sequentially, distortion can be introduced to thereby limit performance. [0469] In some embodiments, and as described herein, a digital dynamic element matching (DEM) algorithm in a digital circuit (DEM block 1150 in Figures 5 to 7) can be configured to effectively shuffle and/or randomize the usage of bit cells when decoding the input signal (e.g., 8-bit signal) to mapping of the bit cells (e.g., among 512 bit cells). Such a functionality can provide significant improvement in distortion performance at the DAC output. [0470] In some embodiments, a bias DEM block can be implemented to provide analogous shuffling function on the reference current cell side to improve, for example 1/frequency noise performance and matching. In the context of the example four telescope modes of the DAC, the bias DEM block can include three telescope modes, and an operating mode can be selected from such three telescope modes based on, for example, signal-to-noise ratio (SNR) and input signal level. [0471] In some embodiments, the DAC of Figures 5 to 7 and 43 can utilize a local DAC reference voltage to drive the current source bit cells. Such reference can be configured for lower power and noise; however, may include a larger temperature dependence. Thus, in some embodiments, the local DAC reference voltage can be calibrated (e.g., periodically) against a trimmed main voltage reference to ensure that gain accuracy is maintained over a range of temperature. [0472] In some embodiments, the DAC’s absolute gain will have been trimmed in production testing, and such a trimmed gain can be utilized as a comparison for calibration. Such a calibration can occur in background while the audio amplifier circuit is operating in audio mode. If there is an updated needed or desired to the reference setting, an adjustment can be made and applied during, for example, the next audio signal zero crossing to minimize or reduce any artifacts. [0473] The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed. [0474] Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers. [0475] Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices. [0476] Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means. [0477] Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer- implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s). [0478] Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include multiple distinct computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the described functions. Each such computing device typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. Where the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid state memory chips and/or magnetic disks, into a different state. [0479] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. [0480] The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.