AUTOMATIC LAYOUT METHOD FOR PAD RING USED FOR OPTIMIZING ELECTROSTATIC DISCHARGING CAPACITY OF CHIP

Title:

AUTOMATIC LAYOUT METHOD FOR PAD RING USED FOR OPTIMIZING ELECTROSTATIC DISCHARGING CAPACITY OF CHIP

Document Type and Number:

WIPO Patent Application WO/2021/196574

Kind Code:

A1

Abstract:

An automatic layout method for a pad ring used for optimizing the electrostatic discharging capacity of a chip, comprising: determining, on the basis of information of a selected process library and of package constraint information, the types and number of signal lead modules of a chip, and, combined with designed total power consumption data, determining the types of power supply lead modules and a basic required number corresponding to each type of power supply lead modules; producing, on the basis of the types and the numbers of the signal lead modules and of that of the power supply lead modules and of the package constraint information, groups of lead modules to be laid out respectively of four boundaries; executing a first automatic layout with respect to each boundary, when a first boundary module is inserted, sequentially polling and calling a second subprogram and a third subprogram, respectively used for inserting the signal lead modules, a first power supply lead module and/or a second power supply lead module; and executing a second automatic layout on the basis of the size of a remaining gap when the first automatic layout is executed. This is used for optimizing the electrostatic discharging capacity of the chip.

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Inventors:

ZHAO SHAOFENG (CN)

Application Number:

PCT/CN2020/123587

Publication Date:

October 07, 2021

Filing Date:

October 26, 2020

Export Citation:

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Assignee:

ANHUI DONGKE SEMICONDUCTOR CO LTD (CN)

International Classes:

G06F30/392

Foreign References:

CN111446238A	2020-07-24
EP3503180A1	2019-06-26
CN101145169A	2008-03-19
CN110502799A	2019-11-26
JP2001298091A	2001-10-26
US6725439B1	2004-04-20

Attorney, Agent or Firm:

HECHWISE PATENT & TRADEMARK FIRM (CN)

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