BIAS CURRENT GENERATOR

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is an electronic device comprising circuitry for generating a bias current with a defined temperature coefficient (TC) and a corresponding method.

BACKGROUND OF THE INVENTION Integrated electronic circuits need all kinds of bias current or voltage generating stages. In order to provide specific temperature dependent effects and to compensate for temperature dependent behavior of the circuitry, bias current or bias voltage generators with positive or negative temperature coefficients (PTC, NTC) are used. The resistance of a device with an NTC decreases with rising temperature. Typically, these NTC-based current generators are combined with components having a positive temperature coefficient (PTC) having together reduced or no temperature dependency. One prior art solution for generating an NTC current uses a feedback loop to force a base-emitter voltage (V _BE ) of a bipolar transistor or a forward voltage of a diode across a resistor. This causes the current through the resistor to have the NTC of the bipolar transistor's base emitter voltage V _BE . If the feedback circuitry should have very low power consumption, the resistance of the resistor should be very large or the V _BE

has to be very small. However, the range and the flexibility of V _BE is very restricted and it typically amounts to 700 to 800 mV resulting in a resistance of several Mω for a target current of several hundred nA. A resistor having such a high resistance requires a lot of chip area if implemented as a typical sheet resistor.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an electronic device including circuitry for generating a current with a specific temperature coefficient requiring less chip area and less power consumption than the prior art.

According to an aspect of the present invention, an electronic device includes circuitry for generating a current with a predetermined temperature coefficient (TC) . For example, the circuitry includes an NTC component coupled to receive a bias current, a differential amplifier connected so as to buffer a voltage across the NTC component for providing a buffered output voltage based on the voltage across the NTC component, a resistor connected so as to receive an NTC current based on the differential amplifier output voltage, wherein the differential amplifier has a predetermined input related offset, so as to decrease the voltage drop across the resistor. Accordingly, in this aspect of the present invention the differential amplifier used to buffer the voltage having a

negative temperature coefficient has an offset, such that the output voltage is systematically reduced allowing a smaller resistor value to be used for the resistor coupled to the output of the differential amplifier. This principle is also applicable to a PTC component.

An input related offset can be implemented in many different ways in the differential amplifier. For example, the differential input pair of a differential amplifier implemented in a CMOS technology can be dimensioned such that one of the transistors of the differential pair has a substantially larger width or a larger width to length ratio than the other transistor. Using a ratio of an integer factor N of the width of the transistors makes implementation as an integrated circuit easier and more reliable. The NTC component can be a bipolar transistor or a forward biased diode. Advantageously, the differential amplifier can be a folded cascode transconductance amplifier. However, if the input stage of such a differential amplifier is modified to provide an input related offset in the output, the voltage drop of a resistor coupled to the output of the amplifier can be reduced. The resistor can have a smaller resistance and the area required to implement the resistor can thus be reduced. Preferably, the offset can lie between 300 mV and 500 mV. Although the present invention is described mainly with respect to an NTC component, it also possible to implement the circuitry with a PTC component.

According to an aspect of the present invention, a method generates a current with a predetermined temperature coefficient. The method preferably includes the steps of providing a voltage across an NTC component, buffering the voltage across the NTC component using a buffering device having an input related offset so as to reduce an output voltage of the buffering device and applying the reduced output voltage across a resistor.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of this invention are illustrated in the drawings, in which:

Figure 1 illustrates a simplified circuit diagram of an NTC current generator according to the prior art; Figure 2 illustrates a simplified circuit diagram of a first embodiment of the present invention;

Figure 3 illustrates a simplified circuit diagram of an amplifier according to an aspect of the present invention; and Figure 4 illustrates a simplified circuit diagram of a second preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Figure 1 shows a simplified block diagram of an NTC current generator according to the prior art. Bipolar transistor Tl has a base to emitter voltage V _BE . The transistor receives a bias current I _b i _as from a constant

current source. The base to emitter voltage V _BE is coupled to the positive input of a differential amplifier AMP. The output of the amplifier AMP is coupled to the gates of PMOS transistors Pi and P ₂ . The source of PMOS transistor Pi is coupled to a supply voltage V _C c and its drain is coupled to the negative input of the amplifier AMP and a resistor R. Due to the feedback connection of the amplifier AMP, the base to emitter voltage V _BE of bipolar transistor Tl also appears across resistor R. The output current I _C TAT at PMOS transistor P ₂ is used for further biasing purposes having the desired temperature coefficient (TC) . The TC of the output current I _CTAT can be negative. However, the NTC can also be partially compensated or completely compensated by a PTC of the resistor R. The area of the resistance can be reduced by reducing the voltage across the resistor R. However, since V _BE is technology dependent and not easily reduced, there is a need for a different solution as provided by the present invention.

Figure 2 shows a simplified circuit diagram of an embodiment of the present invention. The circuit includes mostly the same components as the prior art circuit shown in Figure 1. This invention includes voltage source V _O s at the positive input of the differential amplifier AMP. As with the circuit shown in Figure 1, bipolar transistor Tl is biased by the bias current source I _b i _as • Accordingly, the sum of the base to emitter voltage V _BE and the offset voltage V _O s appears at the positive input node of the

differential amplifier. As a consequence of the feedback connection at the output of the amplifier AMP, the voltage drop across the resistor R is reduced by the offset voltage V _0S at the positive input of the amplifier AMP. Due to this offset and the reduced voltage drop across the resistor R, the resistance of resistor R can be reduced. This reduction in resistance permits a reduction in the required chip area for the resistor R. However, the temperature behavior of the output current I _C TAT is the same as for the prior art circuit of Figure 1.

Figure 3 shows a simplified circuit diagram of a differential amplifier according to an aspect of the present invention. Figure 3 illustrates a folded cascode transconductance amplifier including a differential input stage having two PMOS transistors P6 and P7. The input transistors P6 and P7 have different dimensions, the width of the PMOS transistor P7 is N times the width of the PMOS transistor P6. This introduces an offset into the operational amplifier, as indicated in the Figure 2 by independent voltage source V _O s . This folded cascode operational amplifier can preferably be used as the differential amplifier AMP of Figure 2. The remaining transistors P4, P5, N5, N6, N7 and N8, as well as P3, are dimensioned as usual for this type of operational amplifier. A particular advantage of the folded cascode configuration is a small output offset and inherent stability, which make the folded cascode operational

amplifiers particularly useful for integrated circuit design. Dimensioning the input stages as indicated in Figure 3 with a preferably integral factor of N is easy to implement and allows a precisely predetermined desired offset.

Table 1 shows the exemplary area savings using the circuit of Figure 3 in an arbitrary CMOS technology.

Table 1

For this example, the base emitter voltage V _BE is 450 mV and the offset voltage V _os is 370 mV. The total supply current I _D D includes 10 nA output current (I _C TAT) and 7 nA amplifier current. The area includes the area for the bipolar transistor which is 1,000 μm ² . Accordingly, the resistor area can be reduced by up to about 20%. There are many different ways to introduce an offset into a differential amplifier. Figure 3 illustrates one

possibility where the input transistors have different dimensions. However, the output transistors in the two branches can also have different dimensions.

Figure 4 illustrates a simplified circuit diagram of another preferred embodiment of the present invention. A forward biased diode Dl is used to provide a voltage level with a negative temperature coefficient. As in Figure 2, the operational amplifier OPl has an additional offset voltage source V _O s coupled to its positive input. However, the feedback connection at the output of OPl is different. The output of operational amplifier OPl is directly coupled to the gate of NMOS transistor N9. The voltage between the source of N9 and resistor R is coupled to the negative input of the differential amplifier OPl. The PMOS transistors Pl and P2 are coupled in a current mirror configuration to provide an output current I _ODTS - The circuit of Figure 4 provides the same advantages as set out with respect to Figure 3.

Although the present invention was mainly described with respect to a NTC component, the NTC component can generally be replaced by a PTC component, which has a constant voltage drop.