DAS SARBASHIS (US)
DODDA AKHIL (US)
| WHAT IS CLAIMED IS: 1. A biomimetic audiomorphic device, comprising: a substrate to serve as a back-gate; an insulator or oxide layer formed on the substrate to serve as a back-gate dielectric; a semiconducting channel formed on the back-gate dielectric layer; metallic layers formed in and/or on the semiconducting channel to define a source contact and a drain contact; an insulator or oxide layer to serve as a top-gate dielectric; and a metallic layer formed on the top-gate dielectric to define a split-gate pair, the split-gate pair comprising a first gate and a second gate. 2. The device of claim 1, wherein: the first gate is formed between the source contact and the drain contact located on a first side of the device; the second gate is formed between the source contact and the drain contact on a second side of the device; and the first gate is physically separated from the second gate. 3. The device of claim 1, wherein the substrate is Si. 4. The device of claim 1, wherein the back-gate oxide layer is selected from the group consisting of SiCh, AI2O3, HfCL, or h-BN.. 5. The device of claim 1, wherein the semiconducting channel is an organic semiconductor material or an inorganic semiconductor material. 6. The device of claim 1, wherein the metallic layer formed on the top-gate dielectric is a stack of nickel or gold. 7. The device of claim 1, wherein the top-gate oxide layer is selected from the group consisting of Hydrogen silsesquioxane (HSQ), AI2O3, HfCh, or h-BN. 8. The device of claim 1, wherein, in operation: the back-gate is biased at a voltage VBG, the source contact is grounded, and the drain contact is biased at a drain-to- source voltage VDS; and the first split-gate is biased at a split-gate voltage VSGI, the second split-gate is biased at a split-gate voltage VSG2, and a source-to-drain current IDS flows through the semiconducting channel. 9. The device of claim 1, wherein the metallic layer formed on the top-gate dielectric defines a plurality of split-gate pairs. 10. The device of claim 9, wherein the plurality of split-gate pairs includes a first split-gate pair, a second split-gate pair, a third split-gate pair, a fourth split-gate pair, and a fifth split-gate pair. 11. The device of claim 10, wherein each split-gate pair is separated by a distance, d, and: the distance between the first split-gate pair and the second split-gate pair is di; the distance between the second split-gate pair and the third split-gate pair is di; the distance between the third split-gate pair and the fourth split-gate pair is d3; the distance between the fourth split-gate pair and the fifth split-gate pair is d4; and either di, d2, d3, d4 are equal to each other, or di, d2, d3, d4 are unequal to each other. 12. The device of claim 9, wherein each first gate and second gate of each split gate pair is separated by a distance, s, and the s for one split gate pair is different from the s for another split gate pair. 13. The device of claim 10, wherein each first gate and second gate of each split gate pair is separated by a distance, s, and: the distance between the first gate and the second gate of the first split-gate pair is si; the distance between the first gate and the second gate of the second split-gate pair is S2; the distance between the first gate and the second gate of the third split-gate pair is S3; the distance between the first gate and the second gate of the fourth split-gate pair is S4; the distance between the first gate and the second gate of the fifth split-gate pair is s ; and S5> S4, S4> S3, S3> S2, and S2> Sl. 14. The device of claim 1, further comprising a plurality of fullytop-gated field effect transistor (FET) devices or resistors. 15. A fullytop-gated field effect transistor (FET) device, comprises: a substrate to serve as a back-gate; an insulator or oxide layer formed on the substrate to serve as a back-gate dielectric; a semiconducting channel formed on the back-gate dielectric layer; metallic layers formed in and/or on the semiconducting channel to define a source contact and a drain contact; an insulator or oxide layer to serve as a top-gate dielectric; and a metallic layer formed on the top-gate dielectric to define the top-gate. 16. The device of claim 15, wherein, when in operation: the back-gate is biased at a voltage VBG, the source contact is grounded, and the drain contact is biased at a drain-to- source voltage VDS, the top-gate is biased at a voltage VTG, and a source-to-drain current IDS flows through the semiconducting channel. 17. The device of claim 15, further comprising: a plurality of fullytop-gated FET devices; and a biomimetic audiomorphic device, comprising: a substrate to serve as a back-gate; an insulator or oxide layer formed on the substrate to serve as a back-gate dielectric; a semiconducting channel formed on the back-gate dielectric layer; metallic layers formed in and/or on the semiconducting channel to define a source contact and a drain contact; an insulator or oxide layer to serve as a top-gate dielectric; and a metallic layer formed on the top-gate dielectric to define a plurality of split-gate pairs; wherein each individual split-gate is connected to the drain contact of an individual fullytop-gated FET device. |
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to and claims the benefit of priority of U.S. provisional application 62/880,983, filed July 31, 2019, the entire contents of which is incorporated herein by reference.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] This invention was made with government support under Grant No. FA9550-17-1-0018 awarded by the United States Air Force/ AFOSR. The Government has certain rights in the invention.
FIELD OF THE INVENTION
[0003] Embodiments relate to a biomimetic audiomorphic device. The device can include a field effect transistor (FET) having a split-gate architecture. Embodiments of the device can include multiple split-gates with different spacings between the split-gates of the split-gate architecture. Some embodiments include the integration of delay elements and tunable resistor-capacitance (RC) circuits for imitating interaural time delay neurons. Some embodiments include global back-gating structural features to provide neuroplasticity or reconfigurability aspects to the device.
BACKGROUND OF THE INVENTION
[0004] Supercomputers have become so powerful that they can easily surpass the performance and capacity of the human brain in processing speed and amount of information storage. However, there exists a gap in energy consumption and area efficiency between the human brain and the supercomputers with the supercomputers being at least 1000000X less efficient than the human brain. The emerging era of neuromorphic computing promises to shrink this gap by deploying artificial neural networks (ANNs). ANNs mimic the fundamental computing unit of brain i.e. neurons connected to other neurons via synapses. Neuromorphic chips, such as TrueNorth, Loihi, BrainScale and SpiNNaker are some examples of advancements in the area of artificial intelligence, however, these chips will still remain overwhelmingly power hungry when scaled up to the full capacity of human brain, which has -100 billion neurons connected via 1 quadrillion synapses operating at a miniscule -20 W power.
BRIEF SUMMARY OF THE INVENTION
[0005] Embodiments relate to a biomimetic audiomorphic device. The device can include a field effect transistor (FET) having a split-gate architecture. Embodiments of the device can include multiple split-gates with different spacings between the split-gates of the split-gate architecture. Some embodiments include the integration of delay elements and tunable resistor-capacitance (RC) circuits for imitating interaural time delay neurons. Some embodiments include global back-gating structural features to provide neuroplasticity or reconfigurability aspects to the device.
[0006] In an exemplary embodiment, the biomimetic audiomorphic device includes: a substrate to serve as a back-gate; an insulator or oxide layer formed on the substrate to serve as a back- gate dielectric; a semiconducting channel formed on the back-gate dielectric layer; metallic layers formed in and/or on the semiconducting channel to define the source and the drain contacts; an insulator or oxide layer to serve as a top-gate dielectric; a metallic layer formed on the top-gate dielectric to define the split-gate pair, the split-gate pair comprising a first gate and a second gate. The first gate is formed between the source and the drain located on a first side of the FET device; the second gate is formed between the source and the drain on a second side of the FET device; and the first gate is physically separated from the second gate.
[0007] In some embodiments, the substrate is Si; however, any substrate can be used. In addition, the substrate can be flexible or rigid.
[0008] In some embodiments, the back-gate oxide layer is SiCk; however, any oxide can be used such as AI2O3, HfCk, h-BN, etc.
[0009] In some embodiments, the semiconducting channel is M0S2; however, any organic or inorganic semiconductor can be used, such as other 2D materials, Si, oxide semiconductors, compound semiconductors, etc.
[0010] In some embodiments, the metallic layer is a stack of nickel or gold; however, any metal stack can be used. For instance, the source, drain, and gate contact can be metals, semi-metal, and heavily doped semiconducting materials.
[0011] In some embodiments, the top-gate oxide layer is Hydrogen silsesquioxane (HSQ);
however, any oxide can be used such as AI 2 O 3 , HfCk, h-BN, etc.
[0012] In some embodiments, the biomimetic audiomorphic device, when in operation: the back- gate is biased at a voltage VBG, source is grounded and drain is biased at a drain-to-source voltage VDS, the first split-gate is biased at a split-gate voltage VSGI, the second split-gate is biased at a split-gate voltage VSG2, and a source-to-drain current IDS flows through the channel.
[0013] In some embodiments, plurality of split-gate pairs are used.
[0014] Each split gate is physically separated from any other split gate. [0015] In some embodiments, each split-gate pair is separated by a distance, d, and: the distance between the first split-gate pair and the second split-gate pair is di; the distance between the second split-gate pair and the third split-gate pair is di; the distance between the third split-gate pair and the fourth split-gate pair is d 3 ; the distance between the fourth split-gate pair and the fifth split-gate pair is d4; and di = d2 = d3= d4.
[0016] In some embodiments, di = 400 nm, d2 = 400 nm, d 3 = 400 nm, and d 4 = 400 nm.
However, any spacing, d, between the split-gate pairs can be used.
[0017] In some embodiments, each first gate and second gate of each split gate pair is separated by a distance, s, and: the distance between the first gate and the second gate of the first split-gate pair is si; the distance between the first gate and the second gate of the second split-gate pair is S2; the distance between the first gate and the second gate of the third split-gate pair is S3; the distance between the first gate and the second gate of the fourth split-gate pair is S4; the distance between the first gate and the second gate of the fifth split-gate pair is S5; and s > S 4 , S 4 > S3, S 3 >
S2, and S2> si.
[0018] In some embodiments: si= 200 nm, S2 = 300 nm, S3 = 400 nm, S 4 = 500 nm, and S5 = 600 nm. However, any spacing, s, between the first gate and second gate in the split-gate pair can be used.
[0019] In some embodiments, the biomimetic audiomorphic device further includes a plurality of fullytop-gated field effect transistor (FET) devices or resistors made out of any technology.
[0020] In an exemplary embodiment, a fullytop-gated FET device includes: a substrate to serve as a back-gate; an insulator or oxide layer formed on the substrate to serve as a back-gate dielectric; a semiconducting channel formed on the back-gate dielectric layer; metallic layers formed in and/or on the semiconducting channel to define the source and the drain contacts; an insulator or oxide layer to serve as a top-gate dielectric; metallic layer formed on the top-gate dielectric to define the top-gate.
[0021] In some embodiments, the fully-top gated FET device, when in operation: the back-gate is biased at a voltage VBG, source is grounded and drain is biased at a drain-to-source voltage VDS, the top-gate is biased at a voltage VTG, and a source-to-drain current IDS flows through the channel.
[0022] In an exemplary embodiment, each individual split-gate is connected to the drain of an individual fullytop-gated FET device.
[0023] Further features, aspects, objects, advantages, and possible applications of the present invention will become apparent from a study of the exemplary embodiments and examples described below, in combination with the Figures, and the appended claims.
BRIEF DESCRIPTION OF THE FIGURES
[0024] The above and other objects, aspects, features, advantages, and possible applications of the present invention will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. It should be understood that like reference numbers used in the drawings may identify like components.
[0025] FIG. 1 shows how the path difference between the sound waves reaching the two ears is translated into interaural time difference (ITD) for an acoustic source located at an azimuth angle, Q , for a given head radius (r H ) and sound velocity (v s).
[0026] FIG. 2 shows ITD as a function of Q for different head sizes. [0027] FIG. 3 depicts the Jeffress model with three essential neural components: (1) the time delay neurons, (2) the coincidence detector neurons, and (3) a spatial computational map that correlates the two.
[0028] FIG. 4 shows a simple anatomical drawing of barn owl’s brainstem which bears astonishing similarity with the Jeffress model.
[0029] FIG. 5 shows exemplary schematics of an embodiment of the biomimetic audiomorphic device configured to simulate a solid-state coincidence detector neuron and an embodiment of a tunable resistor-capacitor (RC) circuit configured to simulate a delay neuron.
[0030] FIG. 6 shows an exemplary schematic of an embodiment of a fully integrated biomimetic audiomorphic device in order to emulate the neural computational map inside the auditory cortex of bam owl following the Jeffress model.
[0031] FIG. 7 shows an exemplary schematic of a fully top-gated M0S2 FET on a conventional Si substrate.
[0032] FIG. 8A shows the transfer characteristics, i.e. the source to drain current (IDS) as a function of the top-gate voltage (VTG) for a source to drain voltage of VDS = 1 V of an embodiment of the device of FIG. 7, and FIG. 8B shows a corresponding truth table.
[0033] FIG. 9 shows the schematic of a M0S2 FET with a split-gate architecture.
[0034] FIG. 10A shows the transfer characteristics, i.e. the source to drain current (I DS ) as a function of the split-gate voltage (V SG ) for a source to drain voltage of V DS = 1 V of an embodiment of the device of FIG. 9, and FIG. 10B shows the corresponding truth table.
[0035] FIG. 1 1 shows the source to drain current (IDS) versus time for random voltage pulses of amplitude -30 V applied to the split gates of FIG. 9. [0036] FIG. 12 shows a COMSOL multiphysics simulation of a 2D potential profile when -30V bias is applied to either one or both split-gates of the FET of FIG. 9.
[0037] FIG. 13 shows the ID potential profile along the channel width for different
combinations of two split-gate biases.
[0038] FIG. 14 shows the simulated transfer characteristics of the split-gated M0S2 FET using the Virtual Source (VS) model and the electrostatic potential profile, V CH (x) along the channel width obtained from the COMSOL simulations.
[0039] FIG. 15 shows the biomimetic audiomorphic device with a plurality of split gates.
[0040] FIG. 16 shows the transfer characteristics of the device when each split gate of the FIG. 15 are concurrently swept from 0V to -30V.
[0041] FIG. 17 shows the inhibition ratio (IR) color map for all possible combinations of the split-gates of the FIG. 15.
[0042] FIG. 18 shows the COMSOL simulation results for the ID potential profile across the channel width for different split-gate spacing.
[0043] FIG. 19 shows the angular precision (DQ) and number of analog levels ( N P ) as a function of AIR D for different values
[0044] FIG. 20 shows the output current from an embodiment of the biomimetic audiomorphic device when random voltage spikes of magnitude -30 V are applied to two spilt gates corresponding to different spatial pairs.
[0045] FIG. 21 shows the schematic of an artificial time delay neuron realized by connecting the gate of an embodiment of a split gate FET device to a drain of top-gated FET device. [0046] FIG. 22 shows the experimental transient responses of an embodiment of the artificial time delay neuron.
[0047] FIG. 23 shows transfer characteristics of a top-gated FET device at V DS = IV.
[0048] FIGS. 24A and 24B show an embodiment of the biomimetic audiomorphic device integrating the split-gate FET device architecture and an RC circuit architecture.
[0049] FIG. 25 shows an exemplary schematic of a FET device with global back-gating capability.
[0050] FIG. 26 shows the back-gate transfer characteristics for VDS = IV.
[0051] FIG. 27 shows the transfer characteristics of an embodiment of the biomimetic device when the split-gate pair are concurrently swept from 0V to -30V under different back-gate (V BG ) biases.
[0052] FIG. 28 shows the inhibition ratio (IR) as a function of V BG for different split-gate spacing extracted from the corresponding transfer characteristics.
[0053] FIG. 29 shows the back-gate transfer characteristics of a fully top-gated M0S2 FET for different top-gate voltages (VTG) at VDS = IV.
[0054] FIG. 30 shows the extracted IR from the VS model simulation results as a function of VBG for various split-gate spacing ranging from 50 nm to 600 nm.
[0055] FIG. 31 shows the color map of IR for all possible split-gate pairs of our biomimetic device under different back-gate biases.
DETAILED DESCRIPTION OF THE INVENTION
[0056] The following description is of an embodiment presently contemplated for carrying out the present invention. This description is not to be taken in a limiting sense but is made merely for the purpose of describing the general principles and features of the present invention. The scope of the present invention should be determined with reference to the claims.
[0057] In developing the biomimetic audiom orphic device 104, as well as the components and other aspects of the biomimetic audiom orphic device 104, the inventors used the auditory signal processing of a bam owl as a model. The ability to localize sound is an essential survival feature for predators and preys alike explaining why terrestrial vertebrates have two ears so that the interaural time difference (ITD) of low frequency sound waves can be used as a cue to determine the direction of its source. FIG. 1 shows how the path difference between the sound waves reaching the two ears is translated into ITD for an acoustic source located at an azimuth angle, Q , for a given head radius (r H ) and sound velocity (v s ). FIG. 2 shows ITD as a function of Q for different head sizes. Clearly, for typical size of animal heads it is imperative that the auditory information must be processed within hundreds of microseconds using neurons which can fire only once per few milliseconds. Therefore, auditory signal processing is a challenging computational task for any animal. Remarkably, this problem has been evolutionarily resolved using smart neural algorithms implemented through befitting neurobiological architectures. In this context, bam owls are model auditory systems owing to their extraordinary ability to determine the location of sound with a precision of 1-2 degrees even when hunting in total darkness. In 1948, Lloyd Jeffress published a seminal paper, where he formulated a model that describes how acoustic timing differences are represented as a“place” in an array of nerve cells or in other words how the brain transforms temporal coding into spatial coding. Remarkably, the key assumptions of his model are valid even today. In fact, the Jeffress model remains as the cornerstone for the neurophysiological understanding and development of most computational models for sound localization.
[0058] FIG. 3 depicts the Jeffress model with three essential neural components: (1) the time delay neurons, (2) the coincidence detector neurons, and (3) a spatial computational map that correlates the two. The coincidence neurons fire only when spikes arrive concurrently to the corresponding delay neurons. The length of the delay neurons from the left and right cochlear nuclei is equal up to the points X and Y. However, beyond these points these delay neurons are projected onto coincidence neurons in a ladder-like branching structure that runs in opposite directions. The delay neurons from the right side form a set of collaterals so that the axonal length to the coincidence neuron is longer for cell 7 than for cell 1 and vice versa for the delay neurons from the left side. Due to the finite speed of axonal conduction, these branching patterns constitute a map for the ITDs, and hence correlates to the spatial location of the sound source.
For example if a sound originates from straight ahead, it will reach the right and left cochlea at the same time, i.e. without any interaural delay (ITD = 0 ps). In this case only neuron 4 will receive coincident inputs since the total axonal path lengths are equal. However, if the sound originates from the left hemisphere, it will reach the left ear earlier than the right ear. In this case, coincidence will occur if the input signal from the left travels a longer path length than that from the right by an amount that exactly offsets the acoustic delay, e.g., at cell 1. Similarly, if the sound originates from the right hemisphere, coincidence will occur e.g., at cell 7. Therefore, the spatial projection of the right and left delay neurons onto the coincidence neurons form a computational map where each coincidence neuron represents a specific ITD corresponding to an azimuth. [0059] FIG. 4 shows a simple anatomical drawing of barn owl’s brainstem which bears astonishing similarity with the Jeffress model. In the bam owl, the axons of secondary nerve fibers from the nucleus magnocellularis (NM) provide the delay lines. These monaural channels originate from left and right cochlear nuclei and converge on binaural tertiary nerve fibers which serve as coincidence detectors in the nucleus laminaris (NL). Neurons in NL only discharge on receiving coincident spikes from their monaural, excitatory afferents.
[0060] FIG. 5 shows exemplary schematics of an embodiment of the biomimetic audiomorphic device 104 configured to simulate a solid state coincidence detector neuron and an embodiment of a tunable resistor-capacitor (RC) circuit 102 configured to simulate a delay neuron. As will be explained in detail herein, embodiments of the biomimetic audiomorphic device 104 can include a split-gated M0S2 field effect transistor (FET) architecture used to achieve the functionality of coincidence detector neuron, wherein the tunable resistor-capacitor (RC) circuit 102 is used to mimic delay neurons.
[0061] FIG. 6 shows an exemplary schematic of an embodiment of a fully integrated biomimetic audiomorphic device 104 in order to emulate the neural computational map inside the auditory cortex of barn owl following the Jeffress model. As can be seen from FIG. 6, the biomimetic audiomorphic device 104 includes multiple FET devices 100 having multiple split-gates 106 with different widths of the ungated region on a single channel 108. The channel is connected to the source 110 and drain 112 terminals of the biomimetic audiomorphic device 104 to realize the computational map. Each split-gate 106 is connected to a delay line resistor with the resistance value designed in accordance with the spatial location of the corresponding split-gate 106. With such a configuration, a single biomimetic audiom orphic device 104 can perform biomimetic audiomorphic computing by concurrently performing digital and analog computations.
[0062] In the exemplary embodiments, M0S2 is selected as the semiconducting material for the FET device 100 channel 108 material. It should be noted that selection of M0S2 as the semiconducting channel material is exemplary only. It should be understood that embodiments of the biomimetic audiomorphic device 104 need not be restricted to a M0S2 FET, rather any semiconducting material that allows for the implementation of the split-gate FET geometry can be used.
[0063] It is relatively straightforward to recognize that a coincident neuron acts like a two input AND gate because it fires maximum number of output spikes only when it receives signals from both the left and the right delay neurons at the same time. Coincidence circuits are known for their ability to greatly minimize the chance of a false detection. If the probability of falsely identifying a noise pulse as a genuine signal by one detector is P, then the probability of false detection when two detectors detect the signal pulse simultaneously is P 2 . Therefore, if P = 0.1, then P 2 = 0.01. Thus, the probability of false detection can be significantly reduced by the use of coincidence detection.
[0064] FIG. 7 shows an exemplary schematic of a fully top-gated M0S2 FET on a conventional Si substrate. The semiconducting M0S2 channel is few atomic layers thick and is connected to Ni/Au metal contacts that serve as the source/drain terminals. 120 nm of hydrogen
silsesquioxane (HSQ) is used as the top-gate dielectric and Ni/Au is used as the top-gate electrode. [0065] FIG. 8A shows the transfer characteristics of the device - e.g., source to drain current (IDS) versus top-gate voltage (VTG) for a drain bias, VDS = IV. The device is normally ON at VTG = 0V due to unintentional n-type doping and metal Fermi level pinning close to the conduction band of M0S2 and can be gradually turned OFF by applying negative VTG. A high current ON/OFF ratio of ~10 6 is achieved and the device can be treated as a one-input-one-output digital element represented by the truth table shown in FIG. 8B. Evidently this device cannot represent an AND logic.
[0066] On the contrary, FIG. 9 shows the schematic of a M0S2 FET device 100. The FET device 100 includes a M0S2 semiconducting material exfoliated on Si/Si0 2 gate stack. An oxide layer 116 can be formed in and/or on at least a portion of the source 110 and at least a portion of the drain 112 so as to span a length between the source 110 and the drain 112. The semiconducting region M0S2 108 which is underneath the oxide layer 116 is the active region of operation and lies between source 110 and drain 112. A metallic layer 118 can be formed on top of the oxide layer 116, wherein the metallic layer 118 and the oxide layer 116 form a split-gate 106. The split-gate 106 includes a first gate 106a formed between the source 110, the drain 112, and a M0S2 semiconducting material 108 on a first side 122 of the FET device 100. The split-gate 106 includes a second gate 106b formed between the source 110, the drain 112, and a M0S2 semiconducting channel material 108 on a second side 124 of the FET device 100. The first gate 106a is physically separated from the second gate 106b. In this configuration, the source 110 may be connected to ground so that in operation, the drain 112 is biased at a drain-source voltage VDS, the first gate 106a is biased at a split-gate voltage VSGI, the second gate 106b is biased at a split-gate voltage VSG2, and a drain-source current IDS flows through the channel 108. The source 110 and drain 112 voltages are biased at 0 and IV respectively and the current IDS flows from drain 112 to source 110. The split gates VSGI 106a and VSG2 106b correspondingly modulate the drain to source current when biases are applied.
[0067] FIG. 10A shows the transfer characteristics of the M0S2 FET device 100 - e.g., source to drain current (IDS) versus split-gate voltage (VSG) for a drain bias, VDS = 1 V under two different conditions. One curve depicts the M0S2 FET device 100 characteristics when one of the split- gates 106 is swept from 0V to -30V, while the other split-gate 106 is held at a constant bias of 0V. The other curve depicts the M0S2 FET device 100 characteristics when both split-gates 106 are simultaneously swept from 0V to -30V. Unlike the fully top-gated case, IDS is relatively high when one of the split-gate 106 is at -30V. In other words, the M0S2 FET device 100 cannot be turned OFF by one split-gate 106 and can be considered as always ON. However, when both split-gates 106 reach -30V simultaneously, the M0S2 FET device 100 reaches OFF state with current ON/OFF ratio of ~10 6 . Furthermore, the M0S2 FET device 100 can be considered as a two-input-one-output digital element represented by the truth table shown in FIG. 10B, which can be identified as NAND logic. FIG. 11 shows that the output current from the M0S2 FET device 100 is completely suppressed only when VSGI and VSG2, of magnitude -30 V, arrive at the two corresponding spilt-gates 106, concurrently. FIG. 11 confirms that a split-gated M0S2 FET device 100 can be used as a coincidence detector neuron.
[0068] n order to mimic the computational map constructed by the coincidence neurons in the auditory cortex of barn owl, the inventors fabricated a biomimetic audiom orphic device 104 structure shown in FIG. 15. FIG. 15 shows a FET device 100 with a plurality of split-gates 106. For instance, the FET device 100 can include a first split-gate 106, a second split-gate 106, a third split-gate 106, a fourth split-gate 106, and a fifth split-gate 106, each split-gate 106 having a first gate 106a and a second gate 106b architecture described above. The use of five split-gates 106 is exemplary, and it is understood that any number of split-gates 106 can be used. In an exemplary embodiment, the five split-gates 106 are distributed along a length of the channel 108, separated by spacing d. For instance, the spacing between the first split-gate 106 and the second split-gate 106 can be di. The spacing between the second split-gate 106 and the third split-gate 106 can be d2. The spacing between the third split-gate 106 and the fourth split-gate 106 can be d 3. The spacing between the fourth split-gate 106 and the fifth split-gate 106 can be d 4. Any of di, d2, d 3 , d 4 , can be equal to another or different. It is contemplated for each of di, d2, d 3 , d 4 to be equal to each other so as to have consistent or constant lateral spacing between each split-gate 106. The distance between the first gate 106a and the second gate 106b of each split-gate 106 can be s. Thus, the first split-gate 106 can have si, the second split-gate can have S2, the third split-gate can have S3, the fourth split-gate can have S 4 , and the fifth split-gate can have s . Each of si, S2, S3, S4, S5 should be different from each other. It is contemplated for each of s > S 4 , S 4 >
S3, S 3 > S2, S2> si so as to monotonically increase s of each split-gate 106 from the source 110 to the drain 112. In an exemplary embodiment, each of di, d2, d 3 , d 4 = 400 nm, and si= 200 nm, S2 = 300 nm, S3 = 400 nm, S4 = 500 nm, and S5 = 600 nm.
[0069] FIG. 16 shows the transfer characteristics of the device when each of the five split-gates 106 are concurrently swept from 0V to -30V. Note that a split-gate 106 can, in principle, be constructed by combining any one of the first gates 106a with any other second gate 106b within the 10-gate structure. In fact there exists N(N + l)/2 distinct pairs of split-gates 106 in total which in the exemplary case is 15, since N = 5. A parameter called inhibition ratio (IR) is defined as follows:
[0070] IR is the ratio of current through the FET device 100 corresponding to VSG = 0V and VSG = -30V, concurrently applied to any given split-gate 106. FIG. 17 shows the IR color map for all possible combinations of the split-gates 106. Noticeably the IRs are significantly larger for split- gate pairs that are vertically aligned (diagonal elements in the color map). Being vertically aligned means that the first gate 106a and the second gate 106b are of the same split-gate 106. It is contemplated for these pairs to be used as individual coincidence detector neurons in the biomimetic audiomorphic device 104. Furthermore, within these vertically aligned pairs, the one with minimum split-gate spacing, s, has the maximum IR and vice versa. From the map, it is clear that the IR drops almost exponentially as a function of the split-gate spacing, s. This is interesting since the IR is mostly determined by the current that flows through the ungated region at VSG = -30V. Note that at this VSG, the gated regions are switched OFF. Although the electrostatic potential of the ungated region due to the split-gate potential diminishes linearly with the split-gate spacing, the exponential dependence in IR can be explained from the fact that the device is biased close to the subthreshold regime, where the device current is an exponential function of the channel potential. Note that the IR color map can be used to identify the split- gate pair where the coincidence took place, or in other words the device constructs a spatial map for the coincidence detection. [0071] FIG. 20 shows the output current from the FET device 100 when random voltage spikes of magnitude -30 V are applied to two spilt-gates 106 corresponding to different spatial pairs. All pairs detect coincidence by suppressing the device current. Furthermore, the suppression is maximum with an IR of ~10 5 when coincidence occurred in the split-gate pair corresponding to spacing, s = 200 nm, and minimum with an IR of -450 for spacing, s = 600 nm. Clearly, individual split-gate pairs perform digital computation for coincidence detection (NAND logic), while, the FET device 100 as a whole uses analog IR values for determining the spatial location of the coincidence. As such, embodiments of the biomimetic audiomorphic device 104 using this FET device 100 can seamlessly combine digital and analog computation - a feature that is abundant in biological neural networks. It should be further noted that the number of split-gate pairs or coincidence neurons, Ap, determines the number of analog computation levels which in turn determines the angular precision, DQ, of the biomimetic audiomorphic device following the relationship,
[0072] From this expression, it may appear that the angular precision can be made arbitrarily small by increasing the number of analog levels. However, a large number of analog levels would require a wider analog range for the current suppression or IR, or in other words it necessitates a semiconducting channel with large current ON/OFF ratio. If the minimum required difference between the analog IR values corresponding to two consecutive split-gate pairs is AIR D , then N P and hence DQ will be determined by the following expression:
ON
/l OFF AIR D
iVp = ; DQ = 180°
AIR [2]
D ON
/i OFF [0073] FIG. 19 shows DQ and N P as a function of AIR D for different values 0 f Note
that a small value for AIR D results in greater precision but also requires larger number of split- gate pairs. Furthermore, small AIR D can be more susceptible to noise. Interestingly, the same precision can be achieved for a larger AIR D by increasing the ON/OFF ratio. Nevertheless, the biomimetic audiomorphic device 104 can be designed to offer orders of magnitude better precision than the barn owl. The biomimetic audiomorphic device 104 also offers advantages in device footprint and scalability.
[0074] As described in the Jeffress model, the auditory cortex exploits the finite axonal conduction velocity for transforming the binaural acoustic information encoded via ITDs into a spatial computational map for sound localization. However, unlike the solid state electronic circuits where the signal propagation through metallic interconnects occur at a very high speed, axonal signal propagation is significantly slower. This is because the propagation of action potential along the length of an axon requires periodic charging of the leaky axoplasomic membrane. In vertebrate axons, the myelin sheath improves the axonal insulation and action potentials are regenerated only at the nodes of Ranvier through high density sodium ion- channels.
[0075] FIG. 21 shows the schematic of an artificial time delay neuron realized by connecting the gate 106 of a first FET device 100 to a drain of a second FET device. The first FET device 100 is a split-gated FET device (FIG. 9) and the second FET device is a fully top-gated FET device (FIG. 7). This facilitates constructing a simple RC circuit 102 by the gate capacitance (CG) and channel resistance (ACH) of the corresponding FET device. [0076] FIG. 22 shows the experimental transient responses of the artificial time delay neuron, which can be captured using equation 3:
[0077] In FIG. 22, the different transient responses correspond to different time constants or delays (T c ) achieved by biasing the resistive FET device (the fully top-gated FET device) in different regimes of operations as shown FIG. 23. The time constant was found to vary from -800 ps at VTG = -15V to -200 ms at VTG = -30V corresponding to 7?CH values varying from 4.4 MW to 0.9 GQ, respectively. The gate capacitance due to large gate metal pads and other parasitic contributions was 180±20 pF. The time constant can be reduced by reducing the 7?CH by biasing the FET device further into the ON-state.
[0078] FIG. 24 shows an embodiment of the biomimetic audiomorphic device 104 using embodiments of the FET device 100 and RC circuit architectures. The biomimetic audiomorphic device 104 includes a FET device 100 (having a split gate architecture) in which each split-gate 106 is connected to the drain of a corresponding fully top-gated FET device. For instance, the first split-gate 106 is connected to the drain of a first fully top-gated FET device (having a sourcei, draini, and gatei), the second split-gate 106 is connected to the drain of a second fully top-gated FET (having a source2, draim, and gate2), the third split-gate 106 is connected to the drain of a third fully top-gated FET device (having a sources, drains, and gates), the fourth split- gate 106 is connected to the drain of a fourth fully top-gated FET device (having a source^ drai , and gate 4 ), and the fifth split-gate 106 is connected to the drain of a fifth fully top-gated FET device (having a sources, drains, and gates). Thus, the first split-gate 106 can have its first gate 106a and its second gate 106b connected to drains and draini of the first fully top-gated FET device on either side, respectively. The second split-gate 106 can have its first gate 106a and its second gate 106b connected to drai and draim of the second fully top-gated FET device on either side, respectively. The third split-gate 106 can have its first gate 106a and its second gate 106b connected to drains and drains of the third fully top-gated FET device on either side, respectively. The fourth split-gate 106 can have its first gate 106a and its second gate 106b connected to drai and draim of the fourth fully top-gated FET device on either side, respectively. The fifth split-gate 106 can have its first gate 106a and its second gate 106b connected to drains and draini of the fifth fully top-gated FET device on either side, respectively. Each of soured, source2, sources, source^ sources of the first, second, third, fourth, and fifth fully top-gates FETs can be connected to each other at a node.
[0079] Note that the resistances of the fully top-gated FET devices connected to the bottom halves of the split-gates increase monotonically from left to right and vice versa for the top halves of the split-gates. Thus, in the exemplary embodiment in which ss> S4, S4> S3, S3> S2, S2> si, the first fully top-gated FET device has a resistance of Ri, the second fully top-gated FET device has a resistance of R 2 , the third fully top-gated FET device has a resistance of R 3 , the fourth fully top-gated FET device has a resistance of R 4 , and the fifth fully top-gated FET device has a resistance of R5, wherein Rs> R4, R-s> R3, R3> R2, R2> Ri for the top halves of the split- gates and vice versa for the bottom halves. This facilitates imitating the organization of delay axons in the auditory cortex of the barn owl. The required resistance values can be achieved by designing the length and width of the fully top-gated FET devices accordingly. [0080] One of the remarkable features of the brain is its plasticity. For example bam owls survive by hunting small rodents in the open countryside in Europe. However, there is a significant change in the ground cover available to its prey species between winter and summer. The bam owl must, therefore, become more precise and alert in sound localization in winter than in summer by reversibly changing its brain morphology. Brain morphology can also change due to adaptation to the local environment. For example, the precision in sound localization differs between the bam owls found in the Mediterranean versus Europe or North America. Therefore, it may be desirable to introduce neuroplasticity into the biomimetic audiomorphic device 104.
[0081] FIG. 25 shows an exemplary schematic of a FET device 128 with global back-gating capability. This is achieved by including a back-gate dielectric to form a heavily doped back- gate 120 or back-gate electrode. A top oxide layer 116 is formed in and/or on at least a portion of the source 110. The top oxide layer 116a is formed on the top surface and is formed in and/or on at least a portion of the drain 112. In some embodiments, the top oxide layer 116 (e.g., HSQ, AI2O3, HfCE, h-BN) spans a length between the source 110 and the drain 112. The bottom surface of the substrate 114 includes a bottom oxide layer 116b. The bottom oxide layer 116b can be S1O2, but other materials can be used such as AI2O3, HfCh, h-BN, etc. In some embodiments, the bottom surface of the bottom oxide layer 116b includes a polycrystalline silicon layer 126. The bottom oxide layer 116b and the polycrystalline layer 126 form the back- gate 120. In the exemplary FET device 128, the back-gate dielectric is 285 nm of S1O2 and the back-gate electrode 126 is heavily doped Si.
[0082] FET device 128 is configured to have a split gate architecture similar to the embodiment described in the FIG. 9 example. The split-gate 106 includes a first gate 106a formed between the source 110, the drain 112, and a M0S2 semiconducting material 108 on a first side 122 of the FET device 128. The split-gate 106 includes a second gate 106b formed between the source 110, the drain 112, and a M0S2 semiconducting material 108 on a second side 124 of the FET device 128. The first gate 106a is physically separated from the second gate 106b. The top oxide layer 116a is be formed in and/or on at least a portion of the source 110 and at least a portion of the drain 112 so as to span a length between the source 110 and the drain 112. The semiconducting region M0S2 108 which is underneath the oxide layer 116a is the active region of operation and lies between source 110 and drain 112. A metallic layer 118 is formed on top of the top oxide layer 116a, wherein the metallic layer 118 and the top oxide layer 116a form the split-gate 106.
In this configuration, the source 110 may be connected to ground so that in operation, the drain 112 is biased at a drain-source voltage VDS, the first gate 106a is biased at a split-gate voltage VSGI, the second gate 106b is biased at a split-gate voltage VSG2, a drain-source current IDS flows through the channel 108, and the back-gate 120 is biased at a back-gate voltage VBG. The source 110 and drain 112 voltages are biased at 0 and IV respectively and the current IDS flows from drain to source. The split gates VSGI 106a and VSG2 106b correspondingly modulate the drain to source current when biases are applied. The back-gate voltages (VBG) is used to modulate the conductivity of the channel.
[0083] FIG. 26 shows the back-gate 120 transfer characteristics for VDS = IV. The back-gate 120 has full electrostatic control over the entire channel, which is reflected in the large current ON/OFF ratio of 10 6 . The back-gate 120 threshold voltage was found to be VTB = -12V.
[0084] FIG. 27 shows the transfer characteristics of the FET device 128 when the split-gate pair with 200 nm spacing is concurrently swept from 0V to -30V under different back-gate 120 (V BG ) biases. Clearly, the inhibition ratio (IR) changes significantly and non-monotonically as a function of VBG as shown in FIG. 28. This can be explained from the fact that when, VBG »
VTB, the FET device 128 is in the deep ON-state and hence the current through the ungated region remains high even for VSG = -30V resulting in low IR. As VBG approaches VTB, but still remains above threshold, the current through the device for VSG = 0V only reduces linearly. However, now it becomes relatively easier for the split-gates to switch the ungated channel region from ON state to subthreshold and reduce the device current exponentially for VSG = -30V resulting in an increased IR. Once VBG goes below VTB, the entire device enters subthreshold operation. Now the current through the device for VSG = 0V also reduces exponentially resulting in a decrease in IR. Finally, for VBG « VTB, the entire device is in the deep subthreshold regime with current levels beyond the detection limits of the measurement apparatus and as such the effect of VSG becomes inconsequential.
[0085] FIG. 28 shows the IR as a function of VBG for different split-gate pairs. The non monotonic trend is observed for all split-gate pairs, however, the VBG value for which a given split-gate pair achieves maximum inhibition ratio decreases monotonically as the split-gate spacing increases. This is expected since larger split-gate spacing translates into weaker split- gate control of the ungated region and hence it requires significant electrostatic aid from the back-gate 120. In other words, the back-gate bias should be close to the back-gate threshold so that the impact of the split-gate pair is stronger in the ungated region. In a dual-gated FET, the coupling between the top/split-gate and the back-gate is critical in understanding the impact of one on the other. [0086] FIG. 29 shows the back-gate transfer characteristics of a fully top-gated M0S2 FET for different top-gate voltages (VTG) at VDS = IV. Clearly, the back-gate threshold voltage, VTB, depends on VTG, which can be explained form the principle of charge balance, i.e. the inversion charge induced by the top-gate must be compensated by the back-gate and vice versa.
[0087] FIG. 30 shows the extracted IR from the VS model simulation results as a function of VBG for various split-gate spacing ranging from 50 nm to 600 nm. To mimic the experimental conditions, the minimum OFF current through the device was restricted to 50 pA/pm corresponding to the leakage floor of the measurement instrument. Clearly, the simulated split- gate transfer characteristics and the IR plots show remarkable similarity with the experimental results. Therefore, it can be concluded that the back-gate bias can be used to tune the IR by orders of magnitude and hence can be used to imitate neuroplasticity.
[0088] FIG. 31 shows the color map of IR for all possible split-gate pairs of our biomimetic device under different back-gate biases. Note that a large difference in the magnitude of IR among the diagonal elements is desirable for easier detection of the location of coincidence and hence the localization of the sound source. Clearly, VBG = 14 V provides the maximum IR contrast and hence the corresponding color map can be related to the hyper-attentive state of the bam owl. As expected, the IR contrasts in the color maps diminish monotonically as VBG becomes more positive i.e. the device is biased in the deep ON-state. Therefore, the IR color maps corresponding to VBG = 18 V, 22 V and 26 V can be correlated to the attentive, wakeful and resting state of the bam owl, respectively.
[0089] In the conclusion, the inventors have successfully demonstrated the biomimicry of the neural computational algorithm in the auditory cortex of barn owl. The inventors developed a biomimetic audiom orphic device 104 using multiple split-gates on a single semiconducting M0S2 channel connected to source/drain contacts for emulating the spatial map of coincidence detector neurons and tunable RC circuits for imitating the time delay neurons following the Jeffress model of sound localization. One of the unique features of this biomimetic
audiomorphic device 104 is the fact that it seamlessly combines digital and analog computation, which is abundant in biological neural networks. In short, individual split-gate pairs perform digital computation using NAND logic for determining spiking coincidence, while the biomimetic audiomorphic device 104 as a whole uses analog values for the inhibition ratio (IR) to determine the spatial location of the coincidence. Further, artificial time delay neurons realized using the semiconducting channel resistance and gate capacitance of M0S2 FETs allow biomimicking of finite axonal conduction velocity, which is essential for translating the ITDs into a spatial computational map. In addition, global back-gating capability adds tunable and reversible neuroplasticity to the biomimetic audiomorphic device 104.
[0090] It should be understood that the disclosure of a range of values is a disclosure of every numerical value within that range, including the end points. It should also be appreciated that some components, features, and/or configurations may be described in connection with only one particular embodiment, but these same components, features, and/or configurations can be applied or used with many other embodiments and should be considered applicable to the other embodiments, unless stated otherwise or unless such a component, feature, and/or configuration is technically impossible to use with the other embodiment. Thus, the components, features, and/or configurations of the various embodiments can be combined together in any manner and such combinations are expressly contemplated and disclosed by this statement. [0091] It will be apparent to those skilled in the art that numerous modifications and variations of the described examples and embodiments are possible considering the above teachings of the disclosure. The disclosed examples and embodiments are presented for purposes of illustration only. Other alternate embodiments may include some or all of the features disclosed herein. Therefore, it is the intent to cover all such modifications and alternate embodiments as may come within the true scope of this invention, which is to be given the full breadth thereof.
[0092] It should be understood that modifications to the embodiments disclosed herein can be made to meet a particular set of design criteria. Therefore, while certain exemplary
embodiments of the device and methods of using and making the same disclosed herein have been discussed and illustrated, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.