Title:
BIPOLAR TRANSISTOR AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/112486
Kind Code:
A1
Abstract:
In this bipolar transistor, a mesa structure including a collector layer, a base layer, and an emitter layer that are stacked on a substrate is formed. An emitter electrode electrically connected to the emitter layer is disposed on the mesa structure. Further, a base electrode electrically connected to the base layer is disposed on the mesa structure. The collector electrode is disposed so as to surround the mesa structure in a plan view. The collector electrode is electrically connected to the collector layer. The emitter electrode includes a first portion and a second portion. In a plan view, the base electrode surrounds the first portion of the emitter electrode, and the second portion of the emitter electrode surrounds the base electrode.
Inventors:
SASAKI KENJI (JP)
INOUE KOJI (JP)
TAKAHASHI SHINNOSUKE (JP)
GOTO SATOSHI (JP)
KONDO MASAO (JP)
INOUE KOJI (JP)
TAKAHASHI SHINNOSUKE (JP)
GOTO SATOSHI (JP)
KONDO MASAO (JP)
Application Number:
PCT/JP2022/039394
Publication Date:
June 22, 2023
Filing Date:
October 21, 2022
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01L29/737; H01L21/331; H01L21/8222; H01L27/082
Foreign References:
| JP2001230261A | 2001-08-24 | |||
| JP2010503999A | 2010-02-04 | |||
| US6236071B1 | 2001-05-22 | |||
| JP2008098581A | 2008-04-24 | |||
| JP2016103635A | 2016-06-02 | |||
| JP2010267944A | 2010-11-25 |
Attorney, Agent or Firm:
KITAYAMA Mikio et al. (JP)
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