Title:
BIT LIKLIHOOD CALCULATION METHOD AND DEMODULATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2003/077426
Kind Code:
A1
Abstract:
A Viterbi calculation unit (106) performs a Viterbi calculation in each state by adding a branch metric to a path metric output from a metric selection unit (105) and selecting a path of the least addition result and extracts a remaining path of the least path metric and a second path of the second least path metric. A liklihood calculation unit (107) compares each bit of the remaining path to corresponding bits of the second path and sets the likelihood of bits of different values lower than the bits of the identical value. The likelihood calculation unit calculates likelihood of each bit constituting each symbol of the remaining path according to the relationship between the remaining path and the second path and by utilizing the mapping rule of the modulation signal. Thus, when demodulation is performed by using Viterbi equalization in order to increase the error correction ability, it is possible to calculate the Viterbi likelihood with a high accuracy.
Inventors:
SAITO YOSHIKO (JP)
UESUGI MITSURU (JP)
UESUGI MITSURU (JP)
Application Number:
PCT/JP2003/002769
Publication Date:
September 18, 2003
Filing Date:
March 10, 2003
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
SAITO YOSHIKO (JP)
UESUGI MITSURU (JP)
SAITO YOSHIKO (JP)
UESUGI MITSURU (JP)
International Classes:
H03M13/41; G06F11/10; H04L25/03; H04L27/22; (IPC1-7): H03M13/41
Foreign References:
| JP2000252840A | 2000-09-14 | |||
| JPH04219028A | 1992-08-10 | |||
| JPH04369124A | 1992-12-21 | |||
| JPH06284018A | 1994-10-07 | |||
| JP2000216835A | 2000-08-04 | |||
| JP2002198826A | 2002-07-12 | |||
| JP2002314436A | 2002-10-25 | |||
| JP2002330187A | 2002-11-15 |
Attorney, Agent or Firm:
Washida, Kimihito (Shintoshicenter Bldg. 24-1 Tsurumaki 1-chome Tama-shi, Tokyo, JP)
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