Title:
BLOCK RAM HAVING MULTIPLE CONFIGURABLE WRITE MODES FOR USE IN A FIELD PROGRAMMABLE GATE ARRAY
Document Type and Number:
WIPO Patent Application WO2001091296
Kind Code:
A3
Abstract:
A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.
Inventors:
PANG RAYMOND C
YOUNG STEVEN P
YOUNG STEVEN P
Application Number:
PCT/US2001/016113
Publication Date:
January 23, 2003
Filing Date:
May 17, 2001
Export Citation:
Assignee:
XILINX INC (US)
International Classes:
G11C7/10; G11C11/413; G11C8/16; G11C11/41; H03K19/173; H03K19/177; (IPC1-7): H03K19/177
Foreign References:
| EP0281215A2 | 1988-09-07 | |||
| US5933023A | 1999-08-03 | |||
| US5559450A | 1996-09-24 |
Other References:
XILINX APPLICATION NOTE: VIRTEX FPGAS (XCV SERIES), 29 December 1999 (1999-12-29), XP002207197, Retrieved from the Internet [retrieved on 20020723]
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