BODILY IMPLANT MICROELECTRODE AND BODILY IMPLANT MICROELECTRODE FABRICATION METHOD

FIELD OF THE INVENTION

The present disclosure relates to an electrode or microelectrode to be implanted in or penetrating into a bodily part to provide signals to the bodily part or to capture or receive signals from the bodily part. The present disclosure also relates to a device or implant comprising one or more of such microelectrodes. The present disclosure also relates to a fabrication method for fabricating the microelectrode and/or the device or implant.

The microelectrode is, for example, a microfabricated structure that is a 3D CMOS-compatible microelectrode, for example, for recording/stimulation in implantable devices.

BACKGROUND

Presently, numerous research groups worldwide develop implantable technologies in particular for clinical application where a device or implant is implanted in or penetrated into a bodily part via electrodes or microelectrodes attached to the device or implant. In general, the implant or device includes an electronic unit and, for example, a neural interface based for on penetrating microelectrodes. A key challenge is integrating these two components together.

In the case of miniaturized implantable devices, the electronics is usually based on CMOS dies and the recording/sensing/stimulation is performed with penetrating microelectrodes penetrating into a bodily part of a human or animal. In the future the electronics will be wirelessly supplied and extremely miniaturized (i.e. no batteries).

The integration between the electronics and the microelectrodes is extremely challenging (especially when the implant size is stringent - sub-mm range). The only adopted solution currently is the manual (or semi-manual) integration of the microelectrodes into CMOS pads (i.e. using conductive epoxy or pressuring systems for the connection). This approach is extremely complex, non-reproducible, user-dependent, mechanically unstable and with high variability electrically.

The article entitled “Fabrication technique of a compressible biocompatible interconnect using a thin film transfer process” by Aarts et al, published in the Journal of Micromechanics and Microengineering 21.7 (2011 ): 074012 concerns a compressible multifunctional interconnect for out-of-plane MEMS structures that has been fabricated using a thin film transfer bonding P3734PC00 - dpt technique and bio-tolerable materials. The bulk material of the stretchable film consists of photo-patternable poly-dimethylsiloxane and is fabricated on a carrier substrate. The film is bonded to a slim-base platform. The carrier substrate of the thin film is released using an aluminum anodic dissolution technique. Probe arrays can be assembled perpendicularly into a slim-base platform. Once the probes are assembled a non-separable electrical connection is established. The approach taken can be considered a relatively long and complex procedure, with possible alignment problems, and no scalability in size seems possible. Additionally, the microelectrode cannot be post-processed or this is significantly complex or difficult.

The article entitled “A neural probe process enabling variable electrode configurations" by Kindlundh, Maria, Peter Norlin, and Ulrich G. Hofmann published in Sensors and Actuators B: Chemical 102.1 (2004): 51-58 concerns the use of direct write laser lithography (DWL) in one mask layer enabling on-demand processing of wafers with semi-custom designs at a reasonable cost and lead time. The DWL is used to define windows in a top isolation layer of the device, thus, selecting which electrodes, out of a standardized electrode array, should be active. In addition, the active electrode area can be varied. The concept is evaluated using a 64-site neural probe design and manufacturing process. This approach does not favor scalability in size, provides only 2D structures and is not CMOS compatible.

The article entitled “Massively parallel microwire arrays integrated with CMOS chips for neural recording” by Obaid, Abdulmalik, et al published in Science Advances 6.12 (2020) discloses that while planar silicon-based CMOS devices in conventional electronics scale rapidly, neural interface devices have not kept pace. The approach disclosed is to interface silicon-based chips with three-dimensional microwire arrays, providing the link between rapidly-developing electronics and high-density neural interfaces. The system consists of a bundle of microwires mated to large-scale microelectrode arrays, such as camera chips. The modular design enables a variety of microwire types and sizes to be integrated with different types of pixel arrays, connecting the rapid progress of commercial multiplexing, digitization and data acquisition hardware together with a three-dimensional neural interface. This approach, however, is susceptible to have alignment difficulties, concerns a complex procedure and equipment, the microelectrode is unable to be post-processed or it is difficult to do so, mechanical stability is a potential issue as there being dedicated instruments for every electrode- type.

The article entitled “CHIME: CMOS-hosted in vivo microelectrodes for massively scalable neuronal recordings” by Kollo Mihaly et al, published in Frontiers in neuroscience 14 (2020): P3734PC00 - dpt

834 concerns a manual attachment of microwires into ultra-miniaturized CMOS pads using silver conductive epoxy. The inconveniences of such an approach are low yield, manual procedure, low reproducibility, possible mechanical stability issues and likely poor and variable impedance. Additionally, the microelectrode cannot be post-processed.

3D integration of non-flat objects is complex. Manual integration (or semi-manual integration) is the principally proposed solution.

SUMMARY

It is therefore one aspect of the present disclosure to provide a bodily implantable device or probe device and microelectrode fabrication method according to claim 1 , and a bodily implantable device or probe device according to claim 32.

Other advantageous features can be found in the dependent claims.

The innovative solution of the present disclosure permits fabrication of microelectrodes directly though CMOS processes and fabrication in 2D according to a preferred microelectrode size and path (multiple channels, different lengths, different shapes).

After full CMOS fabrication by the preferred foundry, the silicon underneath the electrodes can be removed during, for example, post-processing (for example, by dry etching).

The solution of the present disclosure also allows for different post-processing operations (such as covering with different materials) which is extremely difficult with normal or known techniques.

After the entire post-processing, the microelectrodes are freestanding and can be tilted by, for example, 90° to be ready for implantation.

The electrical connection is guaranteed by the (CMOS) fabrication itself completely eliminating the electrical issues of traditional methods and known microelectrodes.

Moreover, the solution of the present disclosure also allows for multichannel fabrication.

With the solution of the present disclosure there is no more the need to integrate two different objects together (electronic unit and microelectrode). With the structure and microelectrode of P3734PC00 - dpt the present disclosure the two objects are co-fabricated during the same fabrication process and are integrated-by-fabrication or fabricated to be of unitary construction.

Some key advantages are:

• 2D ad-hoc design (permitting different configuration, shapes, sizes)

• Possibility to post-process the microelectrodes with different materials (no limitation with respect to choices)

• Multiple channels in small space

• CMOS compatibility (high fabrication yield)

• High reproducibility

• User-independent (no alignment problem or difficulties)

• High mechanical stability

• Optimal impedance

The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description with reference to the attached drawings showing some preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate the presently preferred embodiments of the invention, and together with the general description given above and the detailed description given below, serve to explain features of the invention.

Figures 1 a and 1 b schematically show an exemplary bodily implantable device or probe device of the present disclosure comprising, for example, two microelectrodes, where Figure 1 b shows the two microelectrodes oriented to a position for implantation or penetration into a body.

Figure 2 shows exemplary materials used in the fabrication method of the bodily implantable device or probe device and the microelectrodes of the present disclosure.

Figures 3a to 3m show exemplary steps of a fabrication method of the bodily implantable device or probe device and the microelectrodes of the present disclosure. L1 , for example, can be 1500pm; L2, for example, can be 300pm; L3, for example, can be 150pm; hi , for example, P3734PC00 - dpt can be 100p.m; h2, for example, can be 300pm.

Figures 4a and 4b schematically show another exemplary bodily implantable device or probe device of the present disclosure in which microelectrodes are located at (substantially) a 90° angle to one another in contrast to the embodiment of Figures 1a and 1 b in which the microelectrodes are located at (substantially) a 180° angle to one another, and Figure 4b shows the two microelectrodes oriented to a position for implantation or penetration into a body.

Figures 5a and 5b schematically show yet another exemplary bodily implantable device or probe device of the present disclosure in which four microelectrodes are present, and Figure 4b shows the microelectrodes oriented to a position for implantation or penetration into a body.

Herein, identical reference numerals are used, where possible, to designate identical elements that are common to the Figures. Also, the images are simplified for illustration purposes and may not be depicted to scale.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

Exemplary embodiments of a bodily implantable device or a bodily probe device 1 including microelectrodes 3 of the present disclosure are shown, for example, in Figures 1 a, 1 b, 3I, 3m, 4a, 4b, 5a and 5b.

The device 1 includes, for example, a device body 4 including at least one silicon substrate or layer 5. The silicon substrate or layer 5 may include, for example, at least one electronic device or unit 7 (see, for example, Figure 1A and 3I).

The electronic device or unit 7 and/or the silicon substrate or layer 5 includes integrated electronics and/or electronic circuits. The silicon substrate or layer 5, may for example, have undergone processing to fabricate integrated electronics and/or electronic circuits using, for example, one or more processing steps such as (photo)lithography, doping implantation, annealing, material deposition, material removal via etching and/or polishing.

The silicon substrate or layer 5 may, for example, have undergone processing to fabricate integrated electronics and/or electronic circuits using preferably CMOS processing.

Such processing is, for example, carried out prior to the fabrication of the device 1 with P3734PC00 - dpt microelectrodes 3, as disclosed in below in relation with Figures 3a to 3m.

The device 1 is, for example, a device that may be implanted fully inside a human or animal body or organ and destined to remain implanted inside the a human or animal body or organ once placed therein following, for example, a surgical procedure.

The device 1 may alternatively be implanted partially inside the a human or animal body or organ by penetrating or inserting the microelectrode(s) into the a human or animal body or organ while the device body 4 remains partially or fully outside the body or organ. That is, the electronic device or unit 7 and/or the silicon substrate or layer 5 remain partially or fully outside the body or organ, for example, contacting the skin or external tissue.

For example, the microelectrodes 3 may be penetrating microelectrodes, for example, penetrated into brain tissue and provide and/or receive signals from targeted or specific zones of the brain. The device 1 thus, for example, is a neural interface device.

Figures 1 a and 1 b show an exemplary embodiment of a bodily implantable or probe device 1 of the present disclosure which includes a first microelectrode 3 and a second microelectrode 3. The first and second microelectrodes 3 are located opposite one another. The microelectrodes 3 may be located side-by-side as for example shown in Figures 4a and 4b. The device 1 is not limited to including two microelectrodes 3 and may include only one microelectrode 3, or include a higher number of microelectrodes 3, for example between 2 and 10, but can also include more than ten microelectrodes 3 depending on the size of the device 1. Figures 5a and 5b show an exemplary device 1 including four microelectrodes.

The one or the plurality of electrodes or microelectrodes 3 are configured to sense or capture a signal provided by one or more entities of the human or animal body and/or configured for providing a stimulation signal to one or more entities of the human or animal body.

The one or the plurality of electrodes or microelectrodes 3 are in electrical communication and connection with the electronic device or unit 7 (and the electronics and/or electronic circuits therein). The electronic device or unit 7 may thus be configured to receive or generate signals (for example, stimulation signals) and provide such signals to the one or more microelectrodes 3 that communicate these signals to specific or targeted entities or areas of the human or animal body. The microelectrodes 3 are configured to measure or sense (electrical) signals generated by the human or animal body and to communicate the signal to the electronic device or unit 7 for recording, processing and/or further transfer to an external device or system by P3734PC00 - dpt wireless communication.

The device 1 is a bodily implantable device or a probe device for probing areas of the human or animal body.

The device 1 may be included in or may be, for example, a biomedical implant, a neural implant, a cardiovascular implant, an intracortical stimulator/recorder or a sensing platform.

The bodily implantable device or a probe device 1 includes at least one or a plurality of microelectrode 3 for bodily penetration. The one or plurality of microelectrodes 3 are mechanically connected or mechanically attached to the silicon substrate or layer 5, and/or mechanically connected or mechanically attached to the at least one electronic device or unit 7.

The mechanical connection or attachment is, for example, through a chemical adhesion, and/or diffusive adhesion.

The microelectrode 3 or each microelectrode is of unitary construction with the at least one electronic device or unit 7, and/or is of unitary construction with the silicon substrate or layer 5. That is, the electronic device or unit 7 and the microelectrodes 3 form, and are fabricated to form or define, a one-piece or monobloc structure. The microelectrodes 3 of the one-piece or monobloc structure are bendable or rotatable to form a 3D structure to be inserted by penetration of the microelectrodes 3 into the human or animal body.

The microelectrode 3 is displaceable or rotatable towards the silicon substrate or layer 5 and/or electronic device or unit 7, while remaining attached to the silicon substrate or layer 5 and/or electronic device or unit 7. This place, for example, the microelectrode or each microelectrode 3 (or portion thereof) in a non-parallel orientation with respect to a plane or planar direction of extension of the silicon substrate or layer 5, or outer surface of the device body 4.

The microelectrodes 3 may, for example, extend (substantially) parallel to each other and (substantially) perpendicularly away from the device body 4 (or the silicon substrate or layer 5 and/or electronic device or unit 7).

The microelectrodes 3 are attached to the silicon substrate or layer 5 and/or to the at least one electronic device or unit 7.

The microelectrode 3 rotates about an articulation zone 9 located, for example, between (i) the P3734PC00 - dpt silicon substrate or layer 5 and/or electronic device or unit 7 and (ii) an elongated electrical channel 11 of the microelectrode 3.

Figures 1a schematically shows an exemplary bodily implantable device or probe device 1 where the microelectrodes 3 are in a first (or planar/deployed) position in which the microelectrodes 3 extend (substantially) parallel to each other. The microelectrodes 3 are fabricated to be located in this first position (see, for example, Figure 3I).

The microelectrodes may then be displaced or rotated to a second position as seen in Figure 1 b. In the second position, the microelectrodes 3 are located in an enclosure position that (further) encloses the device body 4. This forms a more compact device 1 that better embraces the contours of the body and protrudes less therefrom.

The device 1 may, for example, in this second position then be implanted or inserted into the human or animal body by, for example, penetrating the microelectrodes 3 into the body.

The microelectrodes 3 include one or a plurality of elongated electrical channels 11 extending along the microelectrode 3 (see, for example, Figures 3I and 3m).

The microelectrode 3 includes an insulator material 15 on a first side S1 of the elongated electrical channel 11 that defines one or a plurality of active sites or areas 17 of the microelectrode 3. The elongated insulator material 15 includes an opening 18 (see, for example, Figure 3e) exposing conducting material of the active site 17 and a portion of the elongated electrical channel 11 permitting contact with bodily tissue and electrical contact with the channel 11.

An electrode performance enhancing material 23 may, for example, be included in the opening 18 of the active site or area 17. For example, the electrode performance enhancing material 23 may comprise or consist of Iridium oxide, or carbon nanotubes, or platinum/iridium, or gold, or platinum-black, or poly(3,4-ethylenedioxythiophene) polystyrene sulfonate PEDOT SS.

The elongated insulator material 15 is provided on the elongated electrical channels 11 to delimit one or a plurality of openings 18 defining one or a plurality of active sites or areas 17 of the microelectrode 3.

The plurality of active sites or areas 17 are, for example, distributed along an elongated direction of extension of the microelectrode 3. P3734PC00 - dpt

Each elongated electrical channel 11 may include multiple openings 18 and active sites 17 distributed along the elongated electrical channel 11 , and/or groupings of multiples active sites 17, the groupings being distributed along the length of the elongated electrical channel 11.

Each microelectrode 3 may include multiple elongated electrical channels 11 and thus the microelectrode 3 may include a high number of active sites 17.

A further or second elongated insulator material 19 (see, for example, Figure 3I) is included and located on a second side S2 of the elongated electrical channel 11 to enclose or sandwich the elongated electrical channel 11 in insulator material from the opposing side S2.

The elongated electrical channel or channels 11 include at least one conducting material CM that extends to contact and attach to the silicon substrate or layer 5 and/or to the electronic device or unit 7.

Alternatively or additionally, the elongated second elongated insulator material 19 extends from the at least one conducting material or electrical channel 11 to contact and attach to the silicon substrate or layer 5 and/or to the electronic device or unit 7.

The elongated second elongated insulator material 19 may extend from the at least one conducting material CM or electrical channel 11 to contact and surround the silicon substrate or layer 5 and the electronic device or unit 7.

The bodily implantable or probe device 1 may include a microelectrode notch 21 located between the microelectrode 3 and the silicon substrate or layer 5 and/or to the electronic device or unit 7 (see, for example Figure 3I).

The microelectrode notch 21 is defined or delimited, for example, by the second insulator material 19. The microelectrode notch 21 delimits a space into which the microelectrode 3 (or a portion thereof) can be received when rotated or displaced towards the silicon substrate or layer 5 and/or to the electronic device or unit 7, and to the second position.

The electronic device or unit 7 includes a non-covered upper zone 25 uncovered by the microelectrode or microelectrodes 3. The upper zone 25 may, for example, include electrical connections between the electronic device or unit 7 and the conducting material CM of the electrical channels 11 of the microelectrodes 3. Alternatively or additionally, the upper zone 25 may, for example, include at least one coil or antenna for wireless communication with external P3734PC00 - dpt devices or systems, the electronic device or unit 7 being configured to carry out wireless communication. Alternatively or additionally, the upper zone 25 may, for example, include an outer insulating material defining an outer surface of the upper zone 25, or covering the upper zone 25. The device 1 may be configured to function as a wireless implant.

The at least one conducting material CM for forming the elongated electrical channel 11 of the microelectrode 3 may, for example, comprise or consist of aluminum. Other materials for the conducting material CM may, for example, comprise or consist of copper, or gold, or platinum.

The insulator material 15 provided on the conducting material to define the active site or area 17 and openings 18 of the microelectrode 3, may, for example, comprise or consist of silicon dioxide. Other materials for the insulator material 15 may comprise or consist of silicon nitrite, or silicon carbide, or parylene-C.

The second or further insulator material 19 provided on the exposed elongated surface of the conducting material of the elongated electrical channel 11 of the microelectrode 3 may, for example, comprise or consist of Parylene-C. Other materials for the insulator material 19 may comprise or consist of silicon dioxide, or silicon nitrite, or silicon carbide.

Advantageously, the fabrication of the device 1 is CMOS-compatible permitting to a miniaturized implant or device to be fabricated and permitting scalability of the device fabrication.

The present disclosure also concerns a fabrication method for producing the device 1 , and concerns a bodily implantable device 1 and microelectrode fabrication method, or a probe device 1 and microelectrode fabrication method.

The fabrication method permits the provision of a microfabricated structure for 3D CMOS- compatible microelectrodes for recording/stimulation in implantable devices.

The device 1 and microelectrode fabrication method develops a device in which the microelectrodes are in the first position (Figure 1 a) or what may be considered a device 1 including microelectrodes of a 2D structure which will be used as probes for, for example, sensing/recording/stimulating. Figures 3a to 3I show exemplary step of the fabrication method permitting to produce the device 1 and microelectrodes 3.

The fabrication and development may, for example, be done during a CMOS layout phase of P3734PC00 - dpt the chip design, that is, the design of the electronic device or unit 7. This allows integrating the electronic design with optimization of the device’s or probe’s active sites 17 location (as well as the number of channels 11 ) and granting optimal impedance and matching with the circuits of the device 1. As an example, this is highlighted by the two microelectrodes 3 (with, for example, standard Michigan-probe geometry) shown in Figure 1a.

Following standard CMOS fabrication processes for example, the first side or front-side structure can be realized by the series of material evaporation, photolithography and etching steps.

The device 1 and microelectrode fabrication method comprises providing the at least one silicon substrate or layer 5 including, for example, the at least one electronic device or unit 7, the at least one silicon substrate or layer 5 comprising the first side S1 and the second side S2, the first side S1 being opposite the second side S2.

The first side S1 is, for example, a silicon frontside and the second side S2 is, for example, a silicon backside.

The electronic device or unit 7, may, for example, define a portion of the first side S1 of the silicon substrate or layer 5.

On the first side S1 of the silicon substrate or layer 5, at least one conducting material CM for forming the at least one elongated electrical channel 11 of the microelectrode or of each microelectrode, is provided or deposited.

The conducting material CM provided on the first side S1 of the silicon substrate or layer 5 is patterned or delimited using photolithography and etching to form the elongated electrical channel 11 of the microelectrode 3.

For example, a commercial 300 pm-thick silicon substrate 5 (Figure 3a) is used, a 4 pm-thick and 1500-pm long metal (for example, Aluminum) is evaporated (Figure 3b) onto the silicon substrate 5 and then patterned though lithography (Figure 3c shows deposited photoresist PR used for the patterning) and then etching is carried out to pattern the conducting material and determine the profile of the conducting material of the electrical channels 11 as well as the number of electrical channels 11 in each microelectrode 3. The photoresist PR is then removed (Figure 3d). P3734PC00 - dpt

As seen in the exemplary embodiment of Figure 3, the conducting material provided on the first side of the silicon substrate or layer 5 is patterned and processed using lithography and etched to provide a first elongated electrical channel 11 of the first microelectrode 3 (left) and a second elongated electrical channel 11 of a second microelectrode 3 (right). The first microelectrode and second microelectrodes are, for example, located opposite one another.

The insulator material 15 is deposited or provided on the conducting material CM and processed to define one or more active sites or areas 17 and openings 18 of the microelectrode 3. As mentioned previously, the active site or area 17 permits sensing or capturing a signal provided by a bodily entity and/or permits the provision of a stimulation signal to a bodily entity. The insulator material 15 provided on the conducting material CM is patterned or delimited using lithography and etching to define the active sites or areas 17 of the microelectrode 3.

In the same manner as that for the conducting material CM, the insulating layer 15 (for example, SiO?) is evaporated onto the conducting material CM, and patterned and etched (Figure 3e) to expose only the active areas 17 of the microelectrodes 3. For example, a 150pm- long tip TP that can, for example, be used for intracortical microstimulation.

As seen in the exemplary embodiment of Figure 3e, the insulator material 15 is provided on the conducting material CM of the first microelectrode 3 (left) to define at least one active site or area 17, and is provided on the conducting material CM of the second microelectrode 3 (right) to define at least one active site or area 17 of the second microelectrode 3.

An electrode performance enhancing material 23 may, for example, be deposited or provided in the opening 18 of the active site or area 17. The active area 17 and exposed conducting material CM may, for example, be coated with other materials to improve the electrode performances. As an example, Iridium Oxide is evaporated, patterned and etched (Figure 3f) to increase the charge injection capacity of the microelectrode 3, which is advantageous in the case of stimulating being performed by the device 1 .

Alternatively, Carbon-Nano-Tubes may be deposited permitting to increase the electrochemical active area and improve the sensitivity of the microelectrode 3 in the case of sensing being carried out by the probe device 1 .

At least one portion or zone 25 on the first side S1 of the silicon substrate or layer 5 remains microelectrode material-free or microelectrode-free. P3734PC00 - dpt

The silicon material in-between the two microelectrodes, produced by the patterning or structuring of the first side S1 , remains, for example, uncovered by any layer (Figure 3f) involved in the fabrication of the microelectrode 3, and is where the active region of the implant or device 1 in which the electronic circuitry or electronic device or unit 7 is preferably integrated (for example, produced following a standard CMOS process).

The silicon material or substrate 5 and/or the electronic device or unit 7 includes the noncovered upper zone 25 uncovered by the microelectrode or microelectrodes 3. As previously mentioned, the upper zone 25 may, for example, be provided with electrical connections between the electronic device or unit 7 and the conducting material CM of the electrical channels 11 of the microelectrodes 3. Alternatively or additionally, The upper zone 25 may, for example, be provided with at least one coil or antenna for wireless communication with external devices or systems, the electronic device or unit 7 being configured to carry out wireless communication. The provision of these elements may be carried out prior to the fabrication of the microelectrodes 3 or following the fabrication of the microelectrodes.

Patterning and processing using lithography and etching is carried out on the first side S1 to provide the microelectrodes 3 and to provide the non-covered upper zone 25 uncovered by the one or more microelectrodes. The electronic device or unit 7 may thus include the noncovered upper zone 25 which is uncovered by the microelectrode 3 or parts thereof.

The fabrication method of the present disclosure further includes providing a protection material or layer 27 onto the first side S1 of the silicon substrate or layer 5 to protect the first side S1 and the structured microelectrodes 3 present on the first side S1.

The front-side S1 can be protected by, for example, a protective layer of Parylene-C, for example, 5-pm-thick (Figure 3g).

The protection material or layer 27 also advantageously acts as an etch-stop material during etching of the second side S2 of the silicon substrate or layer 5. The layer of Parylene-C is thus also used as a stop layer during, for example, the backside dry etching process.

Providing the protection material or layer 27 onto the structured or patterned first side S1 includes, for example, providing the protection material or layer 27 onto the insulator material 15, onto the conducting material CM on the silicon substrate or layer 5 and onto the silicon substrate or layer 5 to protect the first side S1 . P3734PC00 - dpt

The silicon material underneath the microelectrodes 3 is then etched to realize free-standing or suspended electrodes.

The fabrication method of the present disclosure further includes etching the silicon material of the second side S2 of the silicon substrate or layer 5 to form an elongated projection 29 extending away from the silicon substrate or layer 5 (or the remaining material thereof). The elongated projection 29 comprises the conducting material CM and may also comprise the insulator material 15 deposited or provided on the conducting material CM and processed to define one or more active sites or areas 17 and openings 18.

Etching the silicon material of the second side S2 of the silicon substrate or layer 5 is also carried out to expose an elongated surface 31 of the conducting material CM of the elongated projection 29.

As shown in the exemplary embodiment of Figure 3i, the silicon material of the second side S2 of the silicon substrate or layer 5 is etched to (i) form first and second elongated projections 29 extending away from the silicon substrate or layer, and (ii) expose the elongated surface 31 of the conducting material CM of the first and second elongated projections 29.

The elongated projection 29 produced by etching is, for example, attached to the first side S1 of the silicon substrate or layer 5. The elongated projection 29 is, for example, attached to the electronic device or unit 7.

Prior to etching the silicon material of the second side S2 of silicon substrate or layer 5, a patterning of the silicon material of the second side S2 is carried out by defining a location of a pattern on the second side S2 relative to alignment markers on the first side S1 of the silicon substrate or layer 5. This may be done, for example, using infra-red IR imaging.

To pattern or structure the second side or backside S2, second side S2 or backside photolithography is done in a similar manner to that of the first side or frontside S1 to obtain the desired pattern or structuring on the back side S2 (Figure 3h). An alignment process between frontside and backside design or structure is performed. This alignment can be done, for example, during a layout printing sub-step. In particular, the employment of dedicated markers, for example, crosses on the frontside S1 allows a backside mask to be aligned to the frontside S1 using IR imaging provided by an IR camera system that allows framing of the crosses and alignment of the pattern or structure on the second side S2 relative to these markers. P3734PC00 - dpt

After the backside S2 is patterned, silicon material backside etching is performed (Figure 31). Etching the silicon material of the second side S2 of the silicon substrate or layer 5 comprises carrying out dry etching of the silicon substrate or layer 5. For example, a cycle of isotropic dry etching is carried out followed by a protective film deposition. This cycle is, for example, repeatedly carried out to obtain a high aspect ratio etched silicon material or structure.

This can be done using, for example, a Deep Reactive Ion Etching (for example, a AMS200 by ALE International SAS, Colombes, France) for Silicon (Si) or Silicon on Insulator (SOI) wafers.

The silicon etch is, for example, carried out using a pulsed method (for example, a Bosch process).

This isotropic dry etching procedure is advantageously fully CMOS-compatible.

The etching, using for example Bosch Technology, is a plasma etching process permitting a high aspect ratio of the etched material to be obtained.

The etching method includes cyclic isotropic etching followed by fluorocarbon-based protective film deposition via rapid gas switching. The SFe plasma cycle etches silicon, whereas the C4F8 plasma cycle forms a protective layer.

The Bosch process is a cyclic succession of two steps: CF4 and SFe. SFe is a gas used as an etchant for Silicon, while CF4 is a gas used to passivate the already etched walls to achieve the requested anisotropy etching level, as for example described in reference [1]:

[1] Gao, Feng, et al. "Smooth silicon sidewall etching for waveguide structures using a modified Bosch process." Journal of Micro/Nanolithography, MEMS, and MOEMS 13.1 (2014): 013010 the contents of which are fully incorporated herein by reference.

The succession of the two gases is called “loop” and the sequence of loops determines the so- called “scallopings”, which can resemble “waves” on the etched surface. These can be reduced by adjusting exposure parameters for the gases, such as exposure time for every loop, as for example described in reference [2]:

[2] J-m. Thevenoud, B. Mercier, T. Bourouina, F. Marty, M. Puech, and N. Launay. Drie Technology: From Micro To Nanoapplications. 2007 (cit. on p. 56) the contents of which are fully incorporated herein by reference. P3734PC00 - dpt

Reasonable etching rate are between 600 nm/loop and 800 nm/loop to enable deep silicon etching with a high aspect ratio.

Both the SFe plasma cycle and the C4F8 plasma cycle are tuned to enable deep silicon etching with a high aspect ratio.

The protective film has a thickness permitting to withstand the SFe plasma cycle required for highly anisotropic silicon etching (for example, a 6.5s SFe pulse can be chosen).

The etching rate is about 4.5pm/s with this approach, and the selectivity to the mask is > 75:1 for the photoresist PR layer (or, alternatively > 150:1 for the SiO? layer).

As mentioned, the protection material or layer 27 that is, for example, Parylene-C acts as stop layer for the etching process, hence, once this layer 27 is reached no more etching is expected for this process.

The etching of the silicon material of the second side S2 of the silicon substrate or layer 5 is carried out to define an etched notch 33 (Figures 3i to 3k) between the elongated projection 29 and the etched silicon substrate or layer 5.

Then, photoresist used to pattern the second side S2 and that is present or remaining on the second side or back S2, after the etching the silicon material of the second side S2 mentioned above, is removed.

A further second side S2 or backside dry etching is then performed to reduce the thickness of the remaining silicon located below or protected by the photoresist. This is reduced to a thickness of, for example, 100 pm to determine or define the active region, of the device 1 , in which the electronic circuitry or electronic device or unit 7 is preferably integrated (Figure 3j). Etching of the second side S2 of the silicon substrate or layer 5 is carried out such that the integrity of the electronic device or unit 7 is preserved. The etched silicon substrate or layer 5 (Figures 3i to 3m) remaining after the etching process may, for example, define a volume or area larger than the electronic device or unit 7, or a volume or area (substantially) equal or corresponding to that of the electronic device or unit 7.

The fabrication method of the present disclosure further includes removing the protection material or layer 27 from the first side S1 of the silicon substrate or layer. This material removal, exposes, for example, the insulator material 15 (Figure 3k) and exposes the active sites or P3734PC00 - dpt areas 17 that can now directly contact bodily tissue when introduced therein.

The protection material or layer 27 on the first side S1 is removed, for example, by plasma removal (Figure 3k).

The protection material or layer 27, for example, Parylene-C on the front side S1 is removed using high-power plasma process, for example, a TePla GiGAbatch Microwave plasma stripper (more details of which are disclosed in reference [3]:

[3] Yilmaz, Mustafa, et al. "Superplastic behavior of silica nanowires obtained by direct patterning of silsesquioxane-based precursors." Nanotechnology 28.11 (2017): 115302, which is fully incorporated herein by reference).

The high-power configuration is able to strip a significant amount of polymer material per second (for example, about 1.2 pm/s).

Preferably after the removal of the protection material or layer 27, the fabrication method of the present disclosure further includes the step of providing or depositing the second or further insulator material 19 on the exposed (elongated) surface 31 of the conducting material CM to isolate the elongated electrical channel 11 of the microelectrode 3.

The second or further insulator material 19 is provided on the second side S2 of the silicon substrate or layer 5 (Figure 3I).

As seen in the exemplary embodiment of Figure 3I, the further insulator material 19 is provided on the exposed elongated surface 31 of the conducting material to isolate the elongated electrical channel 11 of the first (left) and second (right) microelectrodes 3, and also provided on the etched surface of the silicon substrate or layer.

The second or further insulator material 19 is also, for example, provided or deposited on the etched silicon substrate or layer 5. For example, the etched silicon substrate or layer 5 that has been etched before and also following the remaining photoresist removal on the second side S2 to determine or define the active region, of the device 1 , in which the electronic circuitry or electronic device or unit 7 is preferably integrated.

The second or further insulator material 19 comprises or consists of, for example, Parylene-C, which is deposited on the back side S2 permitting to isolate the microelectrodes’ backside S2 and to protect the entire structure (Figure 3I). P3734PC00 - dpt

The second or further insulator material 19 is provided on the exposed elongated surface 31 of the at least one conducting material CM of the elongated projection 29 and also on the etched silicon substrate or layer 5 to provide a microelectrode notch 21 (see, for example, Figure 3I) between the elongated projection 29 and the silicon substrate or layer 5 (or the remaining material thereof).

The microelectrode notch 21 is defined or delimited by the further insulator material 19 provided on the exposed elongated surface 31 of the conducting material CM and by the further insulator material 19 provided on the etched silicon substrate or layer 5.

At this point the two designed microelectrodes 3 of the device 1 , as shown in the exemplary embodiment of Figure 3I, are largely freestanding (silicon underneath the electrodes 3 is absent along a major part of the extension length of the microelectrodes 3).

The elongated projection 29 is displaceable or rotatable towards the silicon substrate or layer 5 and/or towards the electronic device or unit 7 to place the microelectrode 3 in a non-parallel orientation with respect to the silicon substrate or layer 5 and the electronic device or unit 7. As shown, for example, in Figures 1 b and 3m, the elongated projection 29 or microelectrode 3 is displaced or rotated towards the silicon substrate or layer 5 and/or the electronic device or unit 7 to place the microelectrode in the non-parallel orientation.

That is, the probes or microelectrodes 3 of the planer or 2D structure of Figure 3I can then be tilted by, for example, 90° (Figure 3m) and the final 3D structure result is shown in Figure 3m as well as in Figure 1 b.

This exemplary 90° bending is easily done with, for example, tweezers or through dedicated substrates with ad-hoc holes (with the same size of the chip, for example, 300 pm) for the automatic bending of the freestanding probes or microelectrodes 3 once inserted inside. As a result, the designed-2D probes or microelectrodes 3 are tilted and ready to be implanted (Figure 1 b and Figure 3m).

This same process permits different electrode geometries can be constructed. As an example, two microelectrodes are respectively designed at 90° (instead of 180°), as shown in Figures 4a and 4b before and after the bending.

Of course, more than two microelectrodes can be fabricated. Four microelectrodes are, for example, designed in Figures 5a and 5b before and after the bending. P3734PC00 - dpt

The length of the microelectrodes (i.e. in the exemplary embodiment an exemplary length is (approximately) 1500 pm for each microelectrode) can be different for different microelectrodes of the same device 1 .

Also, the directly exposed area 17, 23 of the electrodes 3 (for example, the Iridium Oxide layer 23 in the process flow of Figure 3) can be designed and patterned in multiple different positions, and/or at different heights and/or in different geometries to customize the probe or microelectrode 3 based on requirements of the final application.

Moreover, multiple exposed areas 17, 23 can be designed by simply respecting the design rules in terms of instrument/mask resolution (which is usually in the nm-range). This means that the system can be used with electrodes 3 comprising an enormous number of exposed areas 17, 23 (for both recording, stimulating, sensing). This is currently not possible with known standard 3D integration techniques.

Implementations described herein are not intended to limit the scope of the present disclosure but are just provided to illustrate possible realizations.

While the invention has been disclosed with reference to certain preferred embodiments, numerous modifications, alterations, and changes to the described embodiments, and equivalents thereof, are possible without departing from the sphere and scope of the invention. Accordingly, it is intended that the invention not be limited to the described embodiments and be given the broadest reasonable interpretation in accordance with the language of the appended claims. The features of any one of the above described embodiments may be included in any other embodiment described herein.