Title:
BRANCH PREDICTION CIRCUIT AND INSTRUCTION PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2021/059906
Kind Code:
A1
Abstract:
[Problem] To provide a branch prediction circuit capable of performing branch prediction for a wide range of addresses while limiting the amount of required hardware and reductions in processing speed. [Solution] This branch prediction circuit is configured to include a branch target address storage section 1, a higher order address storage section 2, an address generation section 3, and a branch instruction execution section 4. The branch target address storage section 1 stores a first address of a branch instruction executed in the past, a lower order address of a second address of an instruction to be executed next, and information pertaining to a reference target for a higher order address of the second address and to whether or not reference is needed. The higher order address storage section 2 stores the higher order address of the second address. The address generation section 3 generates the second address when a third address of an instruction to be newly executed matches the first address, the second address being generated by joining the higher order address and the lower order address on the basis of the information pertaining to the reference target for the higher order address of the second address and to whether or not reference is necessary. The branch instruction execution section 4 provides an instruction for speculative execution of the instruction having the second address.
Inventors:
ASANO HIROKI (JP)
Application Number:
PCT/JP2020/033283
Publication Date:
April 01, 2021
Filing Date:
September 02, 2020
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
G06F9/38
Domestic Patent References:
| WO2007099605A1 | 2007-09-07 |
Foreign References:
| JP2013004101A | 2013-01-07 | |||
| US20090249048A1 | 2009-10-01 | |||
| JP2014109953A | 2014-06-12 |
Other References:
KOBAYASHI, RYOTAROET AL.: "A Branch Target Buffer with a Two-level Table Scheme", TRANSACTIONS OF INFORMATION PROCESSING SOCIETY OF JAPAN, vol. 41, no. 5, 15 May 2000 (2000-05-15), pages 1351 - 1359
Attorney, Agent or Firm:
SHIMOSAKA Naoki et al. (JP)
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