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Title:
BURIED CONTACT THROUGH FIN-TO-FIN SPACE FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2023/045484
Kind Code:
A1
Abstract:
Fabrication methods and resulting structures are disclosed to provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. A buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.

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Inventors:
WANG JUNLI (US)
ANDERSON BRENT (US)
Application Number:
PCT/CN2022/103768
Publication Date:
March 30, 2023
Filing Date:
July 05, 2022
Export Citation:
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Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
International Classes:
H01L21/8234; H01L29/417
Foreign References:
US20210280474A12021-09-09
US20200135578A12020-04-30
US20200203210A12020-06-25
US20180294267A12018-10-11
CN111968969A2020-11-20
US20200135634A12020-04-30
Attorney, Agent or Firm:
CCPIT PATENT AND TRADEMARK LAW OFFICE (CN)
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