Title:
CACHE CROSSBAR ARBITRATION
Document Type and Number:
WIPO Patent Application WO2005020079
Kind Code:
A3
Abstract:
A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured. to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.
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Inventors:
OLUKOTUN KUNLE A (US)
Application Number:
PCT/US2004/024869
Publication Date:
January 12, 2006
Filing Date:
July 30, 2004
Export Citation:
Assignee:
SUN MICROSYSTEMS INC (US)
OLUKOTUN KUNLE A (US)
OLUKOTUN KUNLE A (US)
International Classes:
G06F9/38; G06F12/08; G06F13/16; (IPC1-7): G06F12/08; G06F13/36; G06F13/16
Foreign References:
| US6532509B1 | 2003-03-11 |
Other References:
YUVAL TAMIR ET AL: "SYMMETRIC CROSSBAR ARBITERS FOR VLSI COMMUNICATION SWITCHES", IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 4, no. 1, January 1993 (1993-01-01), pages 13 - 27, XP000381322, ISSN: 1045-9219
PATENT ABSTRACTS OF JAPAN vol. 013, no. 291 (P - 893) 6 July 1989 (1989-07-06)
PATENT ABSTRACTS OF JAPAN vol. 013, no. 291 (P - 893) 6 July 1989 (1989-07-06)
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