Title:
CACHE MEMORY DEVICE AND CACHE MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2005/008501
Kind Code:
A1
Abstract:
A cache memory device includes a cache memory (12) based on the set associative method having a plurality of ways and a hit way history data storage section (90) for storing hit way history data corresponding to the way and address selected from a plurality of ways by a memory access in the past. In the hit way history data storage section (90), a way is searched by using as a key the address index section <13:4> during memory access and the way is output as a prediction way.
Inventors:
CHIBA TAKUMA (JP)
Application Number:
PCT/JP2003/009237
Publication Date:
January 27, 2005
Filing Date:
July 22, 2003
Export Citation:
Assignee:
FUJITSU LTD (JP)
CHIBA TAKUMA (JP)
CHIBA TAKUMA (JP)
International Classes:
G06F12/08; G06F12/0864; (IPC1-7): G06F12/08
Foreign References:
| EP0581425A1 | 1994-02-02 | |||
| JPS59218690A | 1984-12-08 | |||
| JPH10320275A | 1998-12-04 |
Other References:
Nicolaescu D. et al. "Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors, Proceedings of Conference and Exhibition on Design", Automation and Test in Europe 2003 (DATE'03), 03 MArch, 2003, pages 1064 - 1068
Batson B. et al, "Reactive-Associative Caches", Proceedings of International Conference on Parallel Architectures and Compilation Techniques 2001, 08 September, 2001, pages 49 - 60
Batson B. et al, "Reactive-Associative Caches", Proceedings of International Conference on Parallel Architectures and Compilation Techniques 2001, 08 September, 2001, pages 49 - 60
Attorney, Agent or Firm:
Sakai, Hiroaki (Kasumigaseki Building 2-5, Kasumigaseki 3-chom, Chiyoda-ku Tokyo, JP)
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